CN109300788A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109300788A CN109300788A CN201710611498.9A CN201710611498A CN109300788A CN 109300788 A CN109300788 A CN 109300788A CN 201710611498 A CN201710611498 A CN 201710611498A CN 109300788 A CN109300788 A CN 109300788A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 121
- 238000000034 method Methods 0.000 title claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 238000005530 etching Methods 0.000 claims abstract description 57
- 239000007789 gas Substances 0.000 claims description 90
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 45
- 229910052710 silicon Inorganic materials 0.000 claims description 45
- 239000010703 silicon Substances 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 42
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 20
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 13
- 229910052796 boron Inorganic materials 0.000 claims description 13
- 229910052986 germanium hydride Inorganic materials 0.000 claims description 13
- 229910052785 arsenic Inorganic materials 0.000 claims description 12
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 12
- 239000013078 crystal Substances 0.000 claims description 11
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 10
- 229910007264 Si2H6 Inorganic materials 0.000 claims description 10
- 229910000070 arsenic hydride Inorganic materials 0.000 claims description 10
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 10
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims description 10
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 10
- 125000004437 phosphorous atom Chemical group 0.000 claims description 10
- 229910015844 BCl3 Inorganic materials 0.000 claims description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 9
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 9
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 9
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 8
- -1 boron ion Chemical class 0.000 claims description 7
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 7
- 239000012495 reaction gas Substances 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 239000012159 carrier gas Substances 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 5
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 4
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 4
- VGRFVJMYCCLWPQ-UHFFFAOYSA-N germanium Chemical compound [Ge].[Ge] VGRFVJMYCCLWPQ-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 2
- 230000008569 process Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910001439 antimony ion Inorganic materials 0.000 description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000003763 carbonization Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The present invention provides a kind of semiconductor structure and forming method thereof, wherein the forming method includes: offer substrate, and the substrate includes adjacent first area and second area；The first epitaxial layer is formed in the substrate first area, the first epitaxial layer top surface is higher than the first area substrate surface；The second epitaxial layer is formed in the substrate second area, the second epitaxial layer top surface is higher than the second area substrate surface；First epitaxial layer and the second epitaxial layer are performed etching, spacing between first epitaxial layer and the second epitaxial layer is increased.Increase spacing between first epitaxial layer and the second epitaxial layer, can prevent first epitaxial layer and the second epitaxial layer from contacting, reduce the leakage current between the first epitaxial layer and the second epitaxial layer, improve semiconductor structure performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
With the rapid development of semiconductor processing technology, semiconductor devices is towards higher component density, and higher collection
The direction of Cheng Du is developed.Transistor is just being widely used at present as most basic semiconductor devices, therefore with semiconductor device
The raising of the component density and integrated level of part, the size of transistor are also smaller and smaller.With the reduction of transistor size, on chip
The quantity of semiconductor devices be consequently increased, the spacing between semiconductor devices is gradually reduced.
Epitaxial growth refers to that one layer of growth has certain requirements, list identical with Substrate orientation on single crystalline substrate (substrate)
Crystal layer.Epitaxial growth technology is the basic fundamental in semiconductor technology, has important application during forming monocrystal.Outside
Growth process has in the positive and negative electrode for forming diode, the techniques such as source and drain doping layer of MOS transistor to be widely applied.
However, the performance for the semiconductor structure that the prior art is formed by epitaxial growth technology is poor.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, can improve to be formed by and partly lead
The performance of body structure.
To solve the above problems, technical solution of the present invention provides a kind of forming method of semiconductor structure, comprising: provide lining
Bottom, the substrate include adjacent first area and second area；The first epitaxial layer is formed in the substrate first area；Institute
It states substrate second area and forms the second epitaxial layer；The first epitaxial layer side wall and the second epitaxial layer side wall are performed etching, increased
Add spacing between first epitaxial layer and the second epitaxial layer.
Optionally, first epitaxial layer is located in the first area substrate surface or the first area substrate；Institute
The second epitaxial layer is stated to be located in the second area substrate surface or the second area substrate.
Optionally, the substrate includes substrate and the fin that is located on the first area and second area substrate；
First epitaxial layer is located in the first area fin or first area fin portion surface；Second epitaxial layer is located at described
In second area fin or second area fin portion surface.
Optionally, the material of first epitaxial layer is silicon, SiGe or silicon carbide；The material of second epitaxial layer is
Silicon, SiGe or silicon carbide.
Optionally, the substrate includes substrate and the fin in the substrate, and the fin top surface is (100)
Crystal face；Alternatively, the substrate is planar substrate, the substrate surface is (100) crystal face.
Optionally, the first area is used to form MOS transistor, and the second area is used to form MOS transistor.
Optionally, the technique performed etching to the first epitaxial layer side wall and the second epitaxial layer side wall includes: each to same
Property dry etch process or wet-etching technology.
Optionally, the technique performed etching to the first epitaxial layer side wall and the second epitaxial layer side wall includes isotropism
Dry etch process；The etching gas of the isotropic dry etch includes: Cl2, one of HCl and HBr or a variety of groups
It closes.
Optionally, the etching gas of the isotropic dry etch further include: Ar, N2、O2、H2、SiH4、Si2H6、GeH4
And Ge2H6One of or multiple combinations.
Optionally, the technological parameter performed etching to the first epitaxial layer side wall and the second epitaxial layer side wall includes: institute
The flow for stating etching gas is 50sccm~1000sccm；Bias power is 0W~1200W；Etching temperature is 600 DEG C~1000
℃。
Optionally, the technique performed etching to the first epitaxial layer side wall and the second epitaxial layer side wall includes wet etching
Technique, the etching liquid of the wet etching include: H2O2Solution, HF solution, NH4OH solution, NaOH solution, KOH solution, HCl are molten
Liquid and NH4One of F solution or multiple combinations.
Optionally, after being performed etching to the first epitaxial layer side wall and the second epitaxial layer side wall, described the of removal
The thickness of one epitaxial layer and the second epitaxial layer is greater than 0nm and is less than or equal to 30nm.
Optionally, after being performed etching to the first epitaxial layer side wall and the second epitaxial layer side wall, further includes: described
First epitaxial layer top surface forms the first extra play；The second extra play is formed in the second epitaxial layer top surface.
Optionally, the material of first extra play is silicon, SiGe or germanium；The material of second extra play is silicon, silicon
Germanium or germanium.
Optionally, there is the first doped source in first epitaxial layer, there is the second doped source in second epitaxial layer；
There is the first additional source, first additional source is identical as the conduction type of first doped source in first extra play；
There is the second additional source, second additional source is identical as the conduction type of second doped source in second extra play.
Optionally, forming first extra play and the technique of the second extra play includes top epitaxial growth technology, and
Doping in situ is carried out to the first extra play and the second extra play in the top epitaxial growth technology, in first extra play
The first additional source is mixed, mixes the second additional source in second extra play.
Optionally, the material of first extra play and the second extra play includes silicon or SiGe；First additional source and
Second additional source includes boron atom, boron ion or BF2+ ion；The material of first extra play and the second extra play includes silicon
Or silicon carbide, first additional source and the second additional source include phosphonium ion, arsenic ion, phosphorus atoms or arsenic atom.
Optionally, the reaction gas for forming first extra play and the second extra play includes: semiconductor source gas, doping
Source gas, carrier gas and etching gas；The semiconductor source gas includes dichlorosilane, SiH4、Si2H6、GeH4Or Ge2H6；Institute
Stating doped source gas includes BCl3、B2H6、AsH3Or PH3；The carrier gas includes: H2Or N2；The etching gas include HCl or
Cl2。
Optionally, the material of first extra play and the second extra play is silicon；First additional source and second adds
Source is boron atom；It includes SiH that the technological parameter for forming first extra play and the second extra play, which includes: semiconductor source gas,4,
Doped source gas includes BCl3；Reaction pressure is 1torr~100torr；Reaction temperature is 500 DEG C~800 DEG C；Alternatively, described
The material of first extra play and the second extra play is germanium silicon, and the first additional source and the second additional source are boron atom, the semiconductor
Source gas includes: silicon source gas and ge source gas, and the silicon source gas includes dichlorosilane or SiH4, the ge source gas packet
Include GeH4, the doped source gas includes: B2H6Or BCl3；Alternatively, the material of first extra play and the second extra play is
Silicon, first additional source and the second additional source are phosphorus atoms or arsenic atom；The semiconductor source gas includes SiH4Or Si2H6；
The doped source gas includes: AsH3Or PH3；Alternatively, the material of first extra play and the second extra play be germanium silicon, first
Additional source and the second additional source are phosphorus atoms or arsenic atom, and the semiconductor source gas includes silicon source gas and ge source gas, institute
Stating silicon source gas includes dichlorosilane or SiH4, the ge source gas includes GeH4, the doped source gas includes: AsH3Or
PH3。
Technical solution of the present invention also provides a kind of semiconductor structure formed by above-mentioned forming method.
Compared with prior art, technical solution of the present invention has the advantage that
In the forming method for the semiconductor structure that technical solution of the present invention provides, to the first epitaxial layer side wall and second
Epitaxial layer side wall performs etching, and increases spacing between first epitaxial layer and the second epitaxial layer.Increase by first epitaxial layer
And second spacing between epitaxial layer, can prevent first epitaxial layer and the second epitaxial layer from contacting, reduce the first epitaxial layer with
Leakage current between second epitaxial layer improves semiconductor structure performance.
Further, the first extra play is formed in the first epitaxial layer top surface, can increased in the substrate of first area
Stress improve formed semiconductor structure performance to increase the migration rate of carrier in the substrate of first area.Described
Second epitaxial layer top surface forms the second extra play, can increase the middle stress of second area substrate, to increase by the secondth area
The migration rate of carrier in the substrate of domain improves formed semiconductor structure performance.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of the forming method of semiconductor structure；
Fig. 2 to Fig. 8 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Specific embodiment
There are problems for the semiconductor structure that the prior art is formed, such as: it is poor to be formed by semiconductor structure performance.
Now in conjunction with a kind of forming method of semiconductor structure, analyze semiconductor structure performance that the forming method is formed compared with
The reason of difference:
Fig. 1 is a kind of structural schematic diagram of the forming method of semiconductor structure.
Referring to FIG. 1, provide substrate 100, the substrate 100 include adjacent the first area A and the second area B, described first
Fin 101 is respectively provided on area's A substrate 100 and second area's B substrate 100；The shape on the firstth area A and second area's B substrate 100
At isolation structure 102, the isolation structure 102 covers 101 partial sidewall of fin；By the first epitaxial growth technology in institute
It states in first area's A fin 101 and forms the first epitaxial layer 111；By the second epitaxial growth technology in the secondth area B fin 101
The second epitaxial layer 112 of middle formation.
Wherein, in order to increase the integrated level of formed semiconductor structure, the firstth area A fin 101 and adjacent second
Spacing between area's B fin 101 is smaller.It is formed after first epitaxial layer and the second epitaxial layer, first epitaxial layer 111
And the second spacing between epitaxial layer 112 is smaller or contacts with each other, and causes between the first epitaxial layer 111 and the second epitaxial layer 112
Leakage current it is larger, to be easy to influence the performance of formed semiconductor structure.
To solve the technical problem, the present invention provides a kind of forming methods of semiconductor structure, comprising: to described the
One epitaxial layer side wall and the second epitaxial layer side wall perform etching, and increase spacing between first epitaxial layer and the second epitaxial layer.
Increase spacing between first epitaxial layer and the second epitaxial layer, can prevent first epitaxial layer and the second epitaxial layer from connecing
Touching reduces the leakage current between the first epitaxial layer and the second epitaxial layer, improves semiconductor structure performance.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 2 to Fig. 8 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Referring to FIG. 2, providing substrate, the substrate includes adjacent first area I and second area II.
The first area I is used to form the first semiconductor devices；The second area II is used to form the second semiconductor
Device.
In the present embodiment, first semiconductor devices is MOS transistor, specifically, first semiconductor devices is
PMOS transistor.In other embodiments, first semiconductor devices can also be NMOS transistor, diode or three-level
Pipe.
In the present embodiment, second semiconductor devices is MOS transistor, specifically, second semiconductor devices is
PMOS transistor.In other embodiments, second semiconductor devices can also be NMOS transistor, diode or three-level
Pipe.
In the present embodiment, the substrate includes substrate 200 and the fin 201 in the substrate 200.In other implementations
In example, the substrate can also be planar substrate, such as silicon substrate, germanium substrate or silicon-Germanium substrate.
In the present embodiment, the material of the substrate 200 and fin 201 is silicon, SiGe or germanium.
In the present embodiment, 200 surface of substrate is (100) crystal face, and 201 top surface of fin is (100) crystal face.
In other embodiments, the substrate is planar substrate, and the substrate surface is (100) crystal face.
The forming method further include: isolation structure 202 is formed in the substrate 200, the isolation structure 202 covers
201 partial sidewall of fin, 202 surface of isolation structure are lower than 201 top surface of fin.
In the present embodiment, the material of the isolation structure 202 is silica.In other embodiments, the isolation structure
Material be silicon oxynitride.
Referring to FIG. 3, subsequent step schematic diagram of Fig. 3 Fig. 2 on the basis of cutting line 21-22, in the present embodiment, described
Semiconductor device is MOS transistor, the method for the formation of the semiconductor structure further include: in the first area I substrate
Upper formation first grid structure 230；Second grid structure is formed on the second area II substrate.
Specifically, the first grid structure is across the first area I fin 201, and cover the first area I fin
102 atop part of portion and partial sidewall surface；The second grid structure is covered across the second area II fin 201
201 atop part of second area II fin and partial sidewall surface.
The first grid structure includes: the first gate dielectric layer on the first area I substrate；Positioned at described
First grid 231 on one gate dielectric layer；The first mask layer 232 on the first grid 231.
The second grid structure includes: the second gate dielectric layer on the second area I substrate；Positioned at described
Second grid on two gate dielectric layers；The second mask layer on the second grid.
The forming method further include: form the first side wall 233 for covering 230 sidewall surfaces of first grid structure；
Form second side wall on covering second grid structure side wall surface.
The material of first side wall 233 and the second side wall is silicon nitride.
In other embodiments, first semiconductor devices is diode or triode, second semiconductor devices
For diode or triode, the forming method does not include the steps that forming first grid structure and second grid structure.
It is subsequent to form the first epitaxial layer in the substrate first area I；It is formed outside second in the substrate second area II
Prolong layer.
In the present embodiment, first epitaxial layer is located in the first area I substrate, and second epitaxial layer is located at institute
It states in second area substrate.The step of forming first epitaxial layer and the second epitaxial layer is as shown in Figures 4 to 6.
Fig. 4 and Fig. 5 are please referred to, Fig. 4 is subsequent step schematic diagram on the basis of Fig. 3, and Fig. 5 is Fig. 4 along cutting line 25-26
Sectional view, form the first groove 204 in the first area I substrate of 230 two sides of first grid structure；Described second
The second groove 205 is formed in the second area II substrate of gate structure two sides.
First groove 204 is used for the first epitaxial layer of subsequent receiving, and second groove 205 accommodates second for subsequent
Epitaxial layer.
In the present embodiment, the technique for forming first groove 204 and the second groove 205 includes dry etch process and wet
The combination of one or both of method etching technics.
Referring to FIG. 6, Fig. 6 is the subsequent step schematic diagram on the basis of Fig. 5, in first groove 204 (as shown in Figure 5)
With the first epitaxial layer 211 of formation in the second groove 205 (as shown in Figure 5)；The second epitaxial layer is formed in second groove 205
212。
In the present embodiment, first semiconductor devices is MOS transistor, and first epitaxial layer 211 is used to form MOS
First source and drain doping layer of transistor.In other embodiments, when first semiconductor devices is diode, described first
Epitaxial layer is used as the positive or negative pole of diode；When first semiconductor devices is triode, first epitaxial layer is used
Do the collector, emitter or base stage of triode.
In the present embodiment, second semiconductor devices is MOS transistor, and second epitaxial layer 212 is used to form MOS
First source and drain doping layer of transistor.In other embodiments, when second semiconductor devices is diode, described second
Epitaxial layer is used as the positive or negative pole of diode；When second semiconductor devices is triode, second epitaxial layer is used
Do the collector, emitter or base stage of triode.
In the present embodiment, first epitaxial layer 211 is located in the first area I substrate.Specifically, outside described first
Prolong layer 211 to be located in the first area I fin 201.In other embodiments, the epitaxial layer may be located on first area
Substrate surface, specifically, first epitaxial layer can be located at the first area fin portion surface.
Second epitaxial layer 212 is located in the second area II substrate.Specifically, second epitaxial layer 212
In the second area II fin 201.In other embodiments, the epitaxial layer may be located on second area substrate table
Face, specifically, second epitaxial layer can be located at the second area fin portion surface.
In the present embodiment, first epitaxial layer 211 is located in the fin 201 of first grid structure two sides.
Second epitaxial layer 212 is located in the fin 201 of second grid structure two sides.
There is the first doped source in first epitaxial layer 211, there is the second doped source in second epitaxial layer 212.
The forming method further include: first epitaxial layer 211 and second epitaxial layer 212 are doped,
The first doped source is mixed in first epitaxial layer 211, mixes the second doped source in second epitaxial layer 212.
In the present embodiment, first semiconductor devices is for forming PMOS transistor, the material of first epitaxial layer 211
Material is SiGe.SiGe can provide compression for the channel of the first semiconductor devices, to increase by first semiconductor devices
Carrier mobility rate in channel.In other embodiments, the material of first epitaxial layer can also be germanium, silicon or carbonization
Silicon.
In the present embodiment, second semiconductor devices is for forming PMOS transistor, the material of second epitaxial layer 212
Material is SiGe.SiGe can provide compression for the channel of the second semiconductor devices, to increase by second semiconductor devices
Carrier mobility rate in channel.In other embodiments, the material of second epitaxial layer can also be germanium, silicon or carbonization
Silicon.
In the present embodiment, the first area I and second area II are used to form PMOS transistor, then described first mixes
The conduction type of miscellaneous source and the second doped source is p-type, such as boron atom.
In other embodiments, the first area I and second area II be used to be formed NMOS transistor, diode or
Triode, first doped source and the second doped source are N-type, such as phosphorus atoms or arsenic atom.
The technique for forming first epitaxial layer 211 and the second epitaxial layer 212 includes epitaxial growth technology.
In the present embodiment, by doping process in situ to 211 He of the first epitaxial layer in the epitaxial process
Second epitaxial layer 212 carries out doping in situ, mixes the first doped source in first epitaxial layer 211, in second extension
The second doped source is mixed in layer 212.
In other embodiments, first epitaxial layer and the second epitaxial layer can also be mixed by ion implanting
It is miscellaneous.If first semiconductor devices and the second semiconductor devices are PMOS transistor, first doped source and second is mixed
Miscellaneous source is boron ion or BF2 +Ion；If first semiconductor devices and the second semiconductor devices are NMOS transistor, described
First doped source and the second doped source are phosphonium ion, arsenic ion or antimony ion.
In the present embodiment, the technological parameter for forming first epitaxial layer 211 and the second epitaxial layer 212 includes: reaction gas
Body includes: semiconductor source gas, doped source gas, carrier gas and etching gas.Wherein, the semiconductor source gas includes silicon source gas
Body and ge source gas, silicon source gas include dichlorosilane (DCS), SiH4Or Si2H6, ge source gas includes: GeH4Or Ge2H6；
The doped source gas includes BCl3、B2H6；The carrier gas includes: H2Or N2；The etching gas includes HCl or Cl2。
In other embodiments, first doped source and the second doped source are phosphorus atoms, and the doped source gas includes
PH3；First doped source and the second doped source are arsenic atom, and the doped source gas includes AsH3。
It should be noted that during forming first epitaxial layer 211 and the second epitaxial layer 212, (100) crystal face
The speed of growth it is very fast, to make first epitaxial layer 211 and 212 side wall of the second epitaxial layer that there is tip, outside described first
The spacing prolonged between the tip of 212 side wall of 211 side wall of layer and the second epitaxial layer is smaller.
It should be noted that in other embodiments, first epitaxial layer can be located at the first area fin table
Face, second epitaxial layer are located at the second area fin portion surface, then form first epitaxial layer and the second epitaxial layer
Step can not include the steps that forming first groove and the second groove.
Referring to FIG. 7, being performed etching to 211 side wall of the first epitaxial layer and 212 side wall of the second epitaxial layer, described in increase
Spacing between first epitaxial layer 211 and the second epitaxial layer 212.
First epitaxial layer, 211 side wall and 212 side wall of the second epitaxial layer are performed etching, first epitaxial layer is increased
211 and second spacing between epitaxial layer 212, it can prevent first epitaxial layer 211 and the second epitaxial layer 212 from contacting with each other,
Reduce the leakage current between the first epitaxial layer 211 and the second epitaxial layer 212, so as to improve the performance of formed semiconductor structure.
In the present embodiment, the technique performed etching to first epitaxial layer 211 and the second epitaxial layer 212 includes each to same
Property dry etching.In other embodiments, the technique performed etching to first epitaxial layer and the second epitaxial layer includes wet process
Etching.
In the present embodiment, the etching gas of the isotropic dry etch includes: HCl or Cl2One or both of
Combination.In other embodiments, the etching gas performed etching to first epitaxial layer and the second epitaxial layer further includes H2、
SiH4、Si2H6、GeH4And Ge2H6One of or multiple combinations.
If the flow of the etching gas is excessive, it is easy to cause first epitaxial layer 211 and the second extension of removal
The thickness of layer 211 is excessive, so that the first half source and drain doping layers that make to be subsequently formed and the second source and drain doping layer is undersized, holds
The channel stress for easily reducing the first semiconductor devices and the second semiconductor devices, influences the performance of formed semiconductor structure；Such as
The flow of etching gas described in fruit is too small, is easily reduced etch rate, to increase technology difficulty.Specifically, in the present embodiment,
The flow of the etching gas is 100sccm~2000sccm.
If the bias power of etching process is excessive, it is easy to increase the directionality of etching process, to increase described first
The loss at 212 top of epitaxial layer 211 and the second epitaxial layer.Specifically, the bias power is 0W~1200W in the present embodiment.
If etching temperature is excessive, cause etch rate too fast, is easy to increase the control difficulty of etching process；If etching
Temperature is too low, is easily reduced etch rate, to reduce production efficiency.Specifically, etching temperature is 600 DEG C in the present embodiment
~1000 DEG C.
It in other embodiments, is wet process to the technique that first epitaxial layer 211 and the second epitaxial layer 212 perform etching
Etching, the etching liquid of the wet etching includes: H2O2Solution, HF solution, NH4OH solution, NaOH solution, KOH solution, HCl are molten
Liquid and NH4One of F solution or multiple combinations.Specifically, the etching liquid can be SC1, SC1 NH4OH and H2O2It is mixed
Close solution.
After being performed etching to 211 side wall of the first epitaxial layer and 212 side wall of the second epitaxial layer, if removal is described
The thickness of first epitaxial layer 211 and the second epitaxial layer 212 is excessive, is easily reduced the first source and drain doping layer and second being subsequently formed
The size of source and drain doping layer, to reduce the channel stress of the first semiconductor devices and the second semiconductor devices；If removal
The thickness of first epitaxial layer 211 and the second epitaxial layer 212 is too small, first epitaxial layer 211 and the second epitaxial layer 212 it
Between spacing it is smaller, be unfavorable for reducing the electric leakage between the first epitaxial layer 211 and the second epitaxial layer 212.Specifically, the present embodiment
In, first epitaxial layer 211 of removal and the thickness of the second epitaxial layer 212 are greater than 0 and are less than or equal to 30nm.
During being performed etching to first epitaxial layer 211 and the second epitaxial layer 212, first epitaxial layer
211 and 212 side wall of the second epitaxial layer be easy to be etched, make the spacing between first epitaxial layer 211 and the second epitaxial layer 212
Increase.
Referring to FIG. 8, forming the first extra play 221 in 211 top surface of the first epitaxial layer；In second extension
212 top surface of layer form the second extra play 222.
First extra play 221 constitutes the first source and drain doping layer, first source and drain with remaining first epitaxial layer 211
Doped layer is used as source region and the drain region of the first semiconductor devices；Second extra play 222 and remaining second epitaxial layer, 212 structure
At the second source and drain doping layer, the second source and drain doping layer is used as source region and the drain region of the second semiconductor devices.
First extra play 221 is for increasing the first source and drain doping layer for being formed by the first semiconductor devices along vertical
Size in 200 surface direction of substrate；The second source and drain that second extra play 222 is used to increase the second semiconductor devices is mixed
Diamicton is along perpendicular to the size in 200 surface direction of substrate.The first source and drain doping floor and the second source and drain doping area size
Increase, the stress in the first semiconductor devices and the second semiconductor device channel can be increased, so as to improve carrier mobility speed
Rate improves the performance of formed semiconductor structure.
In the present embodiment, first extra play 221 is identical as the material of second extra play 222.In other implementations
In, the material of first extra play and second extra play can not be identical.
In the present embodiment, first extra play 221 and the second extra play 222 are formed by same technique.By same
Technique forms first extra play 221 and the second extra play 222 being capable of simplification of flowsheet.In other embodiments, it is formed
After first extra play, second extra play is formed；Or formed after second extra play, it is additional to form first
Layer.
In the present embodiment, the material of first extra play 221 and the second extra play 222 is silicon.In other embodiments,
The material of first extra play and the second extra play can also be germanium, SiGe or silicon carbide.
Growth rate of the monocrystalline silicon on (100) crystal face is greater than the growth rate of other crystal faces.It is attached forming described first
During adding layer 221 and the second extra play 222, the growth rate of the first extra play 221 of 211 top surface of the first epitaxial layer
Greater than the growth rate of the first extra play 221 of 211 sidewall surfaces of the first epitaxial layer；Second epitaxial layer, 212 top
The growth rate of second extra play 222 on surface is greater than the life of the second extra play 222 of 212 sidewall surfaces of the second epitaxial layer
Long rate.Therefore, the thickness of the first extra play 221 of 211 top surface of the first epitaxial layer is larger, second epitaxial layer
The thickness of second extra play 222 of 212 top surfaces is larger；First extra play 221 of 211 sidewall surfaces of the first epitaxial layer
Thickness is smaller, and 222 thickness of the second extra play of 212 sidewall surfaces of the second epitaxial layer is smaller.Therefore, first extra play
221 and second extra play 222 can increase while guaranteeing the spacing between the first source and drain doping area and the second source and drain doping area
Add the stress in the first semiconductor devices and the second semiconductor device channel.
There is the first additional source, first additional source is led with first doped source in first extra play 221
Electric type is identical；There is the second additional source, second additional source and second doped source in second extra play 222
Conduction type is identical.
The technique for forming first extra play 221 and the second extra play 222 includes: top epitaxial growth technology.
It is additional to first extra play 221 and second in the top epitaxial growth process in the present embodiment
Layer 222 carries out doping in situ, mixes the first additional source in first extra play 211, mixes in second extra play 222
Enter the second additional source.
In other embodiments, it is additional that first can also be mixed in first extra play by ion implantation technology
Source, and the second additional source is mixed in the second extra play.If first semiconductor devices and the second semiconductor devices are
The material of PMOS transistor, first extra play and the second extra play is silicon or SiGe, first additional source and second attached
Adding source includes boron ion or BF2 +Ion；If first semiconductor devices and the second semiconductor devices are NMOS transistor, institute
The material for stating the first extra play and the second extra play is silicon or silicon carbide, first additional source and the second additional source include phosphorus from
Son, arsenic ion or antimony ion.
In the present embodiment, first additional source and the second additional source are identical.In other embodiments, described first is additional
Source and the second additional source can not be identical.
Specifically, first additional source and the second additional source are boron atom.In other embodiments, the epitaxial layer
Material is silicon carbide or silicon, and the material of first additional source and the second additional source can be phosphorus atoms or arsenic atom.
In the present embodiment, the reaction gas for forming first extra play 221 and the second extra play 222 includes: silicon source gas
Body and doped source gas.Specifically, the silicon source gas includes SiH4, the doped source gas includes BCl3.In other embodiments
In, the silicon source gas includes Si2H6, the doped source gas includes B2H6。
In other embodiments, the material of first extra play and the second extra play includes germanium or SiGe, the top
The reaction gas of epitaxial growth technology includes ge source gas, and the ge source gas includes GeH4Or Ge2H6；When described first additional
Source and the second additional source include the arsenic atomic time, and the reaction gas for forming first extra play and the second extra play includes AsH3；
When first additional source and the second additional source include phosphorus atoms, the reaction of first extra play and the second extra play is formed
Gas includes PH3.Form the reaction gas of first extra play and the second extra play further include: HCl or Cl2。
Specifically, the material of first extra play and the second extra play is germanium silicon, the first additional source and the second additional source
For boron atom, the semiconductor source gas includes: silicon source gas and ge source gas, the silicon source gas include dichlorosilane or
SiH4, the ge source gas includes GeH4, the doped source gas includes: B2H6Or BCl3；Alternatively, first extra play and
The material of two extra plays is silicon, and first additional source and the second additional source are phosphorus atoms or arsenic atom；The semiconductor source gas
Body includes SiH4Or Si2H6；The doped source gas includes: AsH3Or PH3；Alternatively, first extra play and the second extra play
Material be germanium silicon, the first additional source and the second additional source are phosphorus atoms or arsenic atom, and the semiconductor source gas includes silicon source
Gas and ge source gas, the silicon source gas include dichlorosilane or SiH4, the ge source gas includes GeH4, the doping
Source gas includes: AsH3Or PH3。
By adjusting the parameter of the grown on top technique, the first extra play 221 and the second extra play 222 can be made along vertical
It is directly larger in the growth rate of 200 surface direction of substrate, so as to guarantee the first extra play 221 and the second extra play 222
Between have it is at regular intervals under conditions of, keep the size of the first source and drain doping layer and the second source and drain doping layer larger, to increase
The channel stress of first semiconductor devices and the second semiconductor devices.Specifically, in the present embodiment, the top epitaxial growth
Technological parameter further include: growth temperature is 500 DEG C~800 DEG C；Pressure is 1torr~100torr.
With continued reference to Fig. 8, the embodiment of the present invention also provides a kind of semiconductor structure.
In the present embodiment, the semiconductor structure is formed by the forming method of a upper embodiment.It does not repeat herein.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, the substrate includes adjacent first area and second area；
The first epitaxial layer is formed in the substrate first area；
The second epitaxial layer is formed in the substrate second area；
The first epitaxial layer side wall and the second epitaxial layer side wall are performed etching, first epitaxial layer and the second extension are increased
Spacing between layer.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that first epitaxial layer is located at described
In first area substrate surface or the first area substrate；Second epitaxial layer be located at the second area substrate surface or
In the second area substrate.
3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the substrate includes substrate and difference
Fin on the first area and second area substrate；
First epitaxial layer is located in the first area fin or first area fin portion surface；
Second epitaxial layer is located in the second area fin or second area fin portion surface.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of first epitaxial layer is
Silicon, SiGe or silicon carbide；The material of second epitaxial layer is silicon, SiGe or silicon carbide.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that the substrate includes substrate and is located at
Fin in the substrate, the fin top surface are (100) crystal face；Alternatively, the substrate is planar substrate, the substrate
Surface is (100) crystal face.
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that the first area is used to form
MOS transistor, the second area are used to form MOS transistor.
7. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that the first epitaxial layer side wall and
The technique that second epitaxial layer side wall performs etching includes: isotropic dry etch technique or wet-etching technology.
8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the first epitaxial layer side wall and
The technique that second epitaxial layer side wall performs etching includes isotropic dry etch technique；
The etching gas of the isotropic dry etch includes: Cl2, one of HCl and HBr or multiple combinations.
9. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that the isotropic dry etch
Etching gas further include: Ar, N2、O2、H2、SiH4、Si2H6、GeH4And Ge2H6One of or multiple combinations.
10. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that the first epitaxial layer side wall
The technological parameter performed etching with the second epitaxial layer side wall includes: that the flow of the etching gas is 50sccm~1000sccm；
Bias power is 0W~1200W；Etching temperature is 600 DEG C~1000 DEG C.
11. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the first epitaxial layer side wall
The technique performed etching with the second epitaxial layer side wall includes wet-etching technology, and the etching liquid of the wet etching includes: H2O2It is molten
Liquid, HF solution, NH4OH solution, NaOH solution, KOH solution, HCl solution and NH4One of F solution or multiple combinations.
12. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that the first epitaxial layer side wall
After performing etching with the second epitaxial layer side wall, first epitaxial layer of removal and the thickness of the second epitaxial layer are small greater than 0nm
In equal to 30nm.
13. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that the first epitaxial layer side wall
After being performed etching with the second epitaxial layer side wall, further includes: form the first extra play in the first epitaxial layer top surface；?
The second epitaxial layer top surface forms the second extra play.
14. the forming method of semiconductor structure as claimed in claim 13, which is characterized in that the material of first extra play
For silicon, SiGe or germanium；The material of second extra play is silicon, SiGe or germanium.
15. the forming method of semiconductor structure as claimed in claim 13, which is characterized in that have in first epitaxial layer
First doped source has the second doped source in second epitaxial layer；
There is the first additional source, the conduction type phase of first additional source and first doped source in first extra play
Together；There is the second additional source, the conduction type phase of second additional source and second doped source in second extra play
Together.
16. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that formed first extra play and
The technique of second extra play includes top epitaxial growth technology, and in the top epitaxial growth technology to the first extra play and
Second extra play carries out doping in situ, mixes the first additional source in first extra play, mixes in second extra play
Enter the second additional source.
17. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that first extra play and second
The material of extra play includes silicon or SiGe；First additional source and the second additional source include boron atom, boron ion or BF2 +From
Son；The material of first extra play and the second extra play includes silicon or silicon carbide, first additional source and the second additional source
Including phosphonium ion, arsenic ion, phosphorus atoms or arsenic atom.
18. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that formed first extra play and
The reaction gas of second extra play includes: semiconductor source gas, doped source gas, carrier gas and etching gas；The semiconductor source
Gas includes dichlorosilane, SiH4、Si2H6、GeH4Or Ge2H6；The doped source gas includes BCl3、B2H6、AsH3Or PH3；
The carrier gas includes: H2Or N2；The etching gas includes HCl or Cl2。
19. the forming method of semiconductor structure as claimed in claim 18, which is characterized in that first extra play and second
The material of extra play is silicon；First additional source and the second additional source are boron atom；Form first extra play and second
The technological parameter of extra play includes: that semiconductor source gas includes SiH4, doped source gas includes BCl3；Reaction pressure be 1torr~
100torr；Reaction temperature is 500 DEG C~800 DEG C；
Alternatively, the material of first extra play and the second extra play is germanium silicon, the first additional source and the second additional source are that boron is former
Son, the semiconductor source gas include: silicon source gas and ge source gas, and the silicon source gas includes dichlorosilane or SiH4,
The ge source gas includes GeH4, the doped source gas includes: B2H6Or BCl3；
Alternatively, the material of first extra play and the second extra play is silicon, first additional source and the second additional source are phosphorus
Atom or arsenic atom；The semiconductor source gas includes SiH4Or Si2H6；The doped source gas includes: AsH3Or PH3；
Alternatively, the material of first extra play and the second extra play is germanium silicon, the first additional source and the second additional source are that phosphorus is former
Son or arsenic atom, the semiconductor source gas include silicon source gas and ge source gas, and the silicon source gas includes dichlorosilane
Or SiH4, the ge source gas includes GeH4, the doped source gas includes: AsH3Or PH3。
20. a kind of semiconductor structure that the forming method as described in claim 1 to claim 19 any one is formed.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101866859A (en) * | 2010-07-07 | 2010-10-20 | 北京大学 | Channel stress introducing method and field-effect transistor prepared through same |
| CN102511081A (en) * | 2009-09-24 | 2012-06-20 | 国际商业机器公司 | Method and structure for forming high-performance FETs with embedded stressors |
| CN103928328A (en) * | 2013-01-10 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | Forming method of fin field effect transistor |
| CN104078355A (en) * | 2013-03-28 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of fin field effect transistor |
| CN105514164A (en) * | 2014-10-14 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor and manufacturing method thereof |
| CN106158753A (en) * | 2014-11-06 | 2016-11-23 | 台湾积体电路制造股份有限公司 | The structures and methods of semiconductor device |
| CN106531797A (en) * | 2015-09-11 | 2017-03-22 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN106531737A (en) * | 2015-09-15 | 2017-03-22 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method thereof |
| US20170110558A1 (en) * | 2013-12-30 | 2017-04-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/Drain Structure of Semiconductor Device |
-
2017
- 2017-07-25 CN CN201710611498.9A patent/CN109300788A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102511081A (en) * | 2009-09-24 | 2012-06-20 | 国际商业机器公司 | Method and structure for forming high-performance FETs with embedded stressors |
| CN101866859A (en) * | 2010-07-07 | 2010-10-20 | 北京大学 | Channel stress introducing method and field-effect transistor prepared through same |
| CN103928328A (en) * | 2013-01-10 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | Forming method of fin field effect transistor |
| CN104078355A (en) * | 2013-03-28 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of fin field effect transistor |
| US20170110558A1 (en) * | 2013-12-30 | 2017-04-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/Drain Structure of Semiconductor Device |
| CN105514164A (en) * | 2014-10-14 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor and manufacturing method thereof |
| CN106158753A (en) * | 2014-11-06 | 2016-11-23 | 台湾积体电路制造股份有限公司 | The structures and methods of semiconductor device |
| CN106531797A (en) * | 2015-09-11 | 2017-03-22 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN106531737A (en) * | 2015-09-15 | 2017-03-22 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method thereof |
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