CN109300785A - A method of improving critical dimension uniformity - Google Patents
A method of improving critical dimension uniformity Download PDFInfo
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- CN109300785A CN109300785A CN201811082512.1A CN201811082512A CN109300785A CN 109300785 A CN109300785 A CN 109300785A CN 201811082512 A CN201811082512 A CN 201811082512A CN 109300785 A CN109300785 A CN 109300785A
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 121
- 239000002184 metal Substances 0.000 claims abstract description 121
- 238000005530 etching Methods 0.000 claims abstract description 27
- 238000000926 separation method Methods 0.000 claims abstract description 26
- 239000013078 crystal Substances 0.000 claims abstract description 17
- 238000001259 photo etching Methods 0.000 claims abstract description 9
- 238000012545 processing Methods 0.000 claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 230000002093 peripheral effect Effects 0.000 claims abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 239000004411 aluminium Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 7
- 239000007769 metal material Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 3
- 230000003667 anti-reflective effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
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- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The present invention provides a kind of method for improving critical dimension uniformity, belong to technical field of manufacturing semiconductors, it include: that separation layer is etched using one first light shield, to remove the separation layer for being located at metal grid region and continuum, and retain the separation layer for being located at separate areas, metal wiring layer positioned at metal grid region constitutes metal grid, constitutes step positioned at the peripheral metal structure and separation layer of separate areas, the first light shield has first etching window in corresponding metal grid region and continuum；It successively carries out photoetching treatment and subsequent processing obtains the target wafer with preset critical size.Beneficial effects of the present invention: the uniformity of crystal circle center's metal grid edge critical size is changed and improved, the control range of etching is increased, improves the stability of producing line.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of methods for improving critical dimension uniformity.
Background technique
During backside illuminated image sensor production, sequentially generate metal wiring layer, separation layer etc. on wafer, wafer by
Multiple grained regions 1 are constituted, by necessary technique after each crystal grain is centrally formed regular metal grid pattern, to wafer into
Row segmentation obtains independent crystal grain one by one, then the processing such as is packaged to crystal grain and obtains crystal grain finished product.
As shown in Figure 1, each grained region 1 is made of metal grid region 2 and nonmetallic lattice region 3, metal grid region 2
For rectangle, nonmetallic lattice region 3 is looped around the surrounding in metal grid region 2, and nonmetallic lattice region 3 is by separate areas 4 and continuum
Domain 5 is constituted, and separate areas 4 is rectangle and quantity is no more than three, and the every side in the front, rear, left and right in metal grid region 2 at most has one
A separate areas 4, and i.e. metal grid region 2 and discrete is separated by continuum 5 between metal grid region 2 and separate areas 4
It is not contacted between region 4.As shown in Figure 1, being respectively provided with the reality of a separate areas 4 for the front side in metal grid region 2 and right side
Example is applied, Fig. 1 is only the schematic diagram of one of grained region.There is the first metal in metal wiring layer in metal grid region 2,
There is the second metal, the metal wiring layer in metal grid region 2 is for generating above-mentioned metal grid in the metal wiring layer of separate areas 4
Pattern.
In the prior art, the material of metal wiring layer can use copper or can using the material of other metallic spacers
To use silicon nitride, it is assumed that the first metal and bimetallic material are copper, then crystal grain generates technique and includes:
Step a1, separation layer is performed etching using one first light shield 6, as shown in Fig. 2, be the schematic diagram of the first light shield 6,
Dash area is etching window, and the etching window shape is corresponding with metal grid region 2, and after etching, silicon nitride need to cover nonmetallic
Lattice region 3 (covering nonmetallic 3 purpose of lattice region is the second metal for covering separate areas 4), the silicon nitride quilt in metal grid region 2
Removal is that the metal grid region 2 among crystal grain is opened, and the second metal and silicon nitride positioned at nonmetallic lattice region 3, which are just formed, to be surround
The enclosed step in metal grid region 2, enclosed step height is higher than metal grid region 2, so that difference in height is formed, this
When, the metal wiring layer in metal grid region 2 constitutes metal grid pattern, carries out photoetching treatment later, and wherein photoetching treatment includes applying
Bottom anti-reflection layer, coating photoresist, spin coating developer solution, exposure, development, etching etc. are covered, due to the presence of closed step, position
Bottom anti-reflective figure layer at step can generate accumulation so as to cause homogeneity question；
Step a2, deposited metal aluminium layer performs etching metallic aluminum using one second light shield 7, as shown in figure 3, being the
The schematic diagram of two light shields 7, dash area are etching window, and the etching window shape and metal grid region 2 and separate areas 4 are right
It answers, after etching, removes the metallic aluminum in metal grid region 2 and separate areas 4, the step of separate areas 4 is not by remaining gold
It is fully wrapped around to belong to aluminium layer, at this point, the technique about metal grid pattern generation terminates.
When crystal grain is centrally formed regular metal grid pattern, photoetching treatment is carried out later, due to the presence of closed step,
Bottom anti-reflective figure layer at step can generate accumulation, and when carrying out photoetching treatment, developer solution is easy rebound and is deposited in gold
Possessive case border area, bigger than normal using metal grid border area critical size after etching, metal grid border area critical size is equal
The even bad defect that will lead to color exception of property.The means that production line uses at present are long etch times, pass through long etch
Time can make metal grid border area critical size meet design requirement, but it is less than normal to will lead to metal grid region critical size,
And difference due to etching machine and etching speed are not fixed, if the relatively low product of etching speed still will receive influence.Cause
This, by long etch times, it doesn't solve the problem fundamentally, and final products still will receive influence.
Summary of the invention
Aiming at the problems existing in the prior art, the present invention relates to a kind of optimization mask sets to improve critical dimension uniformity
Method.
The present invention adopts the following technical scheme:
A method of improving critical dimension uniformity and passes through suitable for the metal grid generation process of crystal grain generation step
Metal grid generation process is handled pretreatment wafer to obtain target wafer, and the pretreatment wafer includes wafer, formed
In the separation layer of metal wiring layer and the covering metal wiring layer on the wafer, the pretreatment wafer is by multiple crystalline substances
Grain region is constituted, and the grained region is constituted by metal grid region and around the nonmetallic lattice region in the metal grid region, institute
It states nonmetallic lattice region to be made of at least one separate areas and a continuum, the metal grid region and the separate areas
Between separated by the continuum, positioned at the separate areas the metal wiring layer constitute peripheral metal structure；It is described
Method includes:
Step S1, the separation layer is etched using one first light shield, the metal grid region and the company is located at removal
The separation layer in continuous region, and retain the separation layer being located at positioned at the separate areas, the institute positioned at metal grid region
It states metal wiring layer and constitutes metal grid, constitute platform positioned at the peripheral metal structure of the separate areas and the separation layer
Rank, first light shield have first etching window in corresponding the metal grid region and the continuum；
Step S2, it successively carries out photoetching treatment and subsequent processing obtains the target wafer with preset critical size.
Preferably, the metal wiring layer uses metal material, and the metal material includes copper.
Preferably, the separation layer uses isolation material, and the isolation material includes silicon nitride.
Preferably, the metal grid region is rectangle.
Preferably, the separate areas is rectangle and quantity is no more than three, and every side in the metal grid region is at most
It is distributed a separate areas.
Preferably, the quantity of the separate areas is two and is located at the adjacent two sides in the metal grid region.
Preferably, the subsequent processing in the step S2 includes:
Step b1, deposited metal aluminium layer, to cover the grained region；
Step b2, the metallic aluminum is etched using one second light shield, is located at removal described into metal grid region and institute
The metallic aluminum on the step of separate areas is stated, and retains the metallic aluminum for wrapping up the step surrounding, institute
Stating the second light shield has the second etching window of the step of the corresponding metal grid region and the separate areas.
Preferably, the method is suitable for the crystal grain generation step of backside illuminated image sensor production process.
Beneficial effects of the present invention: changing and improving the uniformity of crystal circle center's metal grid edge critical size, increases etching
Control range, improve the stability of producing line.
Detailed description of the invention
Fig. 1 is the schematic diagram of grained region in the prior art；
Fig. 2 is the schematic diagram for the first light shield that metal grid generation process uses in the prior art；
Fig. 3 is the structural schematic diagram for the second light shield that metal grid generation process uses in the prior art；
Fig. 4 is the structural representation for the first light shield that metal grid generation process uses in a preferred embodiment of the present invention
Figure；
Fig. 5 is the structural representation for the second light shield that metal grid generation process uses in a preferred embodiment of the present invention
Figure
Fig. 6 is to improve the flow chart of the method for critical dimension uniformity in a preferred embodiment of the present invention；
Fig. 7 is the flow chart of subsequent processing in a preferred embodiment of the present invention.
Specific embodiment
It should be noted that in the absence of conflict, following technical proposals be can be combined with each other between technical characteristic.
A specific embodiment of the invention is further described with reference to the accompanying drawing:
As shown in Fig. 1,4-7, a method of improving critical dimension uniformity, the metal grid suitable for crystal grain generation step
Generation process is handled to obtain target wafer, above-mentioned pretreatment wafer pretreatment wafer by metal grid generation process
Separation layer including wafer, the metal wiring layer being formed on above-mentioned wafer and the above-mentioned metal wiring layer of covering, above-mentioned pre- place
Reason wafer is made of multiple grained regions 1, and above-mentioned grained region 1 is by metal grid region 2 and around the non-of above-mentioned metal grid region 2
Metal grid region 3 is constituted, and above-mentioned nonmetallic lattice region 3 is made of at least one separate areas 4 and a continuum 5, above-mentioned gold
It is separated between possessive case region 2 and above-mentioned separate areas 4 by continuum 5, positioned at the above-mentioned metal wiring layer of above-mentioned separate areas 4
Constitute peripheral metal structure；The above method includes:
Step S1, above-mentioned separation layer is etched using one first light shield 8, with removal positioned at above-mentioned metal grid region 2 and continuously
The above-mentioned separation layer in region 5, and retain the above-mentioned separation layer for being located at above-mentioned separate areas 4, the above-mentioned gold positioned at metal grid region 2
Belong to wiring layer and constitute metal grid, constitutes step positioned at the above-mentioned peripheral metal structure of above-mentioned separate areas 4 and above-mentioned separation layer, on
State the first etching window that the first light shield 8 has corresponding above-mentioned metal grid region 2 and above-mentioned continuum 5；
Step S2, it successively carries out photoetching treatment and subsequent processing obtains the target wafer with preset critical size.
In the present embodiment, it pre-processes filling metal on wafer and forms metal wiring layer, by the quarter for improving the first light shield 8
Hatch frame is lost, after through each grained region 1 on the first light shield 8 etching pretreatment wafer, in each grained region 1
Step that form non-close, that edge metal structure by being located at separate areas 4 and remaining separation layer are constituted, not due to the step
It is enclosed construction, therefore, bottom anti-reflective figure layer would not be in the step of metal grid fringe region when subsequent progress photoetching treatment
Place forms accumulation, to avoid generating homogeneity question, avoids the formation for influencing metal grid edge critical size.It is mentioned with improvement
The uniformity of high crystal circle center's metal grid edge critical size, increases the control range of etching, it is excellent to improve stability of producing line etc.
Point.
In preferred embodiment, above-mentioned metal wiring layer uses metal material, and above-mentioned metal material includes copper.
In the present embodiment, the material of metal wiring layer, which can choose copper also, can choose other metal materials.
In preferred embodiment, above-mentioned separation layer uses isolation material, and above-mentioned isolation material includes silicon nitride.
In the present embodiment, the material of separation layer, which can choose silicon nitride also, can choose other isolation materials.
In preferred embodiment, above-mentioned metal grid region 2 is rectangle.
In preferred embodiment, above-mentioned separate areas 4 is rectangle and quantity is no more than three, above-mentioned metal grid region 2
Every side is at most distributed an above-mentioned separate areas 4.
In preferred embodiment, the quantity of above-mentioned separate areas 4 is two and is located at the adjacent of above-mentioned metal grid region 2
Two sides.
In preferred embodiment, the above-mentioned subsequent processing in above-mentioned steps S2 includes:
Step b1, deposited metal aluminium layer, to cover above-mentioned grained region 1；
Step b2, above-mentioned metallic aluminum is etched using one second light shield 9, above-mentioned metal grid region 2 and upper is located at removal
The above-mentioned metallic aluminum on the above-mentioned step of separate areas 4 is stated, and retains the above-mentioned metallic aluminum for wrapping up above-mentioned step surrounding, on
Stating the second light shield 9 has the second etching window of above-mentioned step of corresponding above-mentioned metal grid region 2 and above-mentioned separate areas 4.
In the present embodiment, by adjusting the etching opening of the second light shield 9, take subsequent film i.e. golden in the place of step
Belong to aluminium layer extension and do not etch, it is ensured that the position of step has subsequent aluminium fully wrapped around, is avoided that critical size is uneven in this way
It is avoided that there is residual in stepped locations again.The specific improvement mode of second light shield 9 is the etching opening for keeping corresponding separate areas 4
Size shape is constant, reduces the size of the etching opening in corresponding metal grid region 2.
In preferred embodiment, the above-mentioned crystal grain that the above method is suitable for backside illuminated image sensor production process generates step
Suddenly.
By description and accompanying drawings, the exemplary embodiments of the specific structure of specific embodiment are given, based on present invention essence
Mind can also make other conversions.Although foregoing invention proposes existing preferred embodiment, however, these contents are not intended as
Limitation.
For a person skilled in the art, after reading above description, various changes and modifications undoubtedly be will be evident.
Therefore, appended claims should regard the whole variations and modifications for covering true intention and range of the invention as.It is weighing
The range and content of any and all equivalences, are all considered as still belonging to the intent and scope of the invention within the scope of sharp claim.
Claims (8)
1. a kind of method for improving critical dimension uniformity passes through gold suitable for the metal grid generation process of crystal grain generation step
Possessive case generation process handles to obtain target wafer pretreatment wafer, and the pretreatment wafer includes wafer, is formed in
The separation layer of metal wiring layer and the covering metal wiring layer on the wafer, the pretreatment wafer is by multiple crystal grain
Region is constituted, and the grained region is constituted by metal grid region and around the nonmetallic lattice region in the metal grid region, described
Nonmetallic lattice region is made of at least one separate areas and a continuum, the metal grid region and the separate areas it
Between separated by continuum, positioned at the separate areas the metal wiring layer constitute peripheral metal structure；It is characterized in that,
The described method includes:
Step S1, the separation layer is etched using one first light shield, is located at the metal grid region and continuum to remove
The separation layer, and retain the separation layer for being located at the separate areas, the metal wiring layer positioned at metal grid region
Metal grid is constituted, constitutes step, first light positioned at the peripheral metal structure of the separate areas and the separation layer
Cover first etching window with corresponding the metal grid region and the continuum；
Step S2, it successively carries out photoetching treatment and subsequent processing obtains the target wafer with preset critical size.
2. the method according to claim 1, wherein the metal wiring layer uses metal material, the metal
Material includes copper.
3. the method according to claim 1, wherein the separation layer uses isolation material, the isolation material
Including silicon nitride.
4. the method according to claim 1, wherein the metal grid region is rectangle.
5. according to the method described in claim 4, it is characterized in that, the separate areas is that rectangle and quantity are no more than three,
Every side in the metal grid region is at most distributed the separate areas.
6. according to the method described in claim 4, it is characterized in that, the quantity of the separate areas is two and is located at the gold
The adjacent two sides in possessive case region.
7. the method according to claim 1, wherein the subsequent processing in the step S2 includes:
Step b1, deposited metal aluminium layer, to cover the grained region；
Step b2, the metallic aluminum is etched using one second light shield, is located at removal described into metal grid region and described point
The metallic aluminum on the step in vertical region, and retain the metallic aluminum for wrapping up the step surrounding, described the
Two light shields have the second etching window of the step of the corresponding metal grid region and the separate areas.
8. the method according to claim 1, wherein the method is suitable for backside illuminated image sensor production work
The crystal grain generation step of skill.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811082512.1A CN109300785B (en) | 2018-09-17 | 2018-09-17 | Method for improving uniformity of critical dimension |
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| CN201811082512.1A CN109300785B (en) | 2018-09-17 | 2018-09-17 | Method for improving uniformity of critical dimension |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066095A (en) * | 2013-01-14 | 2013-04-24 | 陆伟 | Image sensor and manufacturing method thereof |
| CN103065943A (en) * | 2013-01-10 | 2013-04-24 | 无锡华润上华半导体有限公司 | Critical size compensating method of deep groove etching process |
| CN103730349A (en) * | 2012-10-10 | 2014-04-16 | 中芯国际集成电路制造(上海)有限公司 | Method for forming contact hole |
| CN107230682A (en) * | 2016-03-24 | 2017-10-03 | 台湾积体电路制造股份有限公司 | BSI imaging sensors and forming method thereof |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730349A (en) * | 2012-10-10 | 2014-04-16 | 中芯国际集成电路制造(上海)有限公司 | Method for forming contact hole |
| CN103065943A (en) * | 2013-01-10 | 2013-04-24 | 无锡华润上华半导体有限公司 | Critical size compensating method of deep groove etching process |
| CN103066095A (en) * | 2013-01-14 | 2013-04-24 | 陆伟 | Image sensor and manufacturing method thereof |
| CN107230682A (en) * | 2016-03-24 | 2017-10-03 | 台湾积体电路制造股份有限公司 | BSI imaging sensors and forming method thereof |
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |