CN109298248B - Complex pulse modulation sequence measuring circuit and method based on FPGA - Google Patents
Complex pulse modulation sequence measuring circuit and method based on FPGA Download PDFInfo
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Abstract
The invention discloses a complex pulse modulation sequence measuring circuit and method based on FPGA, belonging to the technical field of test, comprising FPGA, a peak probe, a preamplifier, a post amplifier, ADC, a trigger unit, CPU, a memory and a display unit; the FPGA comprises a time base control unit and a trigger shielding unit. The invention realizes the stable measurement of a complex pulse modulation sequence through trigger shielding, realizes any pulse edge in the pulse sequence as a trigger edge through time delay triggering and event delay triggering functions, and completes the detail measurement of any pulse edge under a fast time base; the trigger shielding system is realized in the FPGA, an external circuit is not required to be added, the stability and the reliability are high, and the application range of the peak power analyzer is expanded.
Description
Technical Field
The invention belongs to the technical field of testing, and particularly relates to a complex pulse modulation sequence measuring circuit and method based on an FPGA.
Background
At present, a peak power analyzer can perform diode detection on a periodic pulse modulation signal to obtain a pulse envelope, and stable display of a signal waveform is realized through random sampling.
While radar, telemetry, magnetic resonance imaging and wireless communication applications such as TDMA, GSM and other complex modulation signals are shown in fig. 1, the pulse sequences are irregularly distributed in the time domain. Due to the non-periodicity of the pulse sequence, peak power analyzers cannot stably trigger this type of pulse signal.
For the complex pulse modulation sequence shown in fig. 1, it is a repeating periodic signal for a longer time, but not for a shorter time. The peak power analyzer can trigger at the rising edge of a pulse, but a pulse sequence has 3 trigger points in one period, and the trigger pulse is random, so that the aliasing phenomenon of a measurement waveform can occur in actual measurement.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides the FPGA-based complex pulse modulation sequence measuring circuit and method, which are reasonable in design, overcome the defects of the prior art and have good effects.
In order to achieve the purpose, the invention adopts the following technical scheme:
a complex pulse modulation sequence measuring circuit based on FPGA comprises FPGA, a peak probe, a preamplifier, a post amplifier, ADC, a trigger unit, CPU, a memory and a display unit; the FPGA comprises a time base control unit and a trigger shielding unit;
the peak probe is configured to be used for detecting and logarithmically amplifying the microwave millimeter wave pulse modulation signal to obtain a probe input signal;
a preamplifier configured for pre-amplifying a probe input signal;
a post-amplifier configured for post-amplifying the pre-amplified probe input signal;
an ADC configured to convert the post-amplified analog probe input signal to a digital signal;
the trigger unit is used for comparing the signal amplified by the preamplifier with a trigger level and generating a trigger signal;
a CPU configured to generate a sampling start signal to enable the time base control unit; when the time base control unit generates an acquisition completion signal and outputs the acquisition completion signal to the CPU, the CPU reads out and processes the required waveform data from the memory and outputs the processed waveform data to the display unit, and then sends a sampling start signal to the time base control unit again;
a memory configured to store waveform data;
a display unit configured to display a repetitive waveform;
the time base control unit is configured to receive an enabling signal sent by the CPU, send a sampling clock signal to the ADC, respond to a trigger signal, and generate an acquisition completion signal and output the acquisition completion signal to the CPU when an address counter of the time base control unit counts a preset value;
the trigger shielding unit is used for generating a trigger shielding signal, and the trigger shielding unit provides the same trigger pulse edge-to-time base control unit by adjusting the time interval of the trigger shielding signal;
the microwave millimeter wave pulse modulation signal enters a preamplifier after being detected and logarithmically amplified by a peak probe, a probe input signal enters a post amplifier after being preamplified, enters an ADC after being amplified by the post amplifier, and an analog probe input signal is converted into an n-bit parallel digital signal under a sampling clock of a time base control unit;
the signal amplified by the preamplifier is also input into the trigger unit, and compared with the trigger level to generate a trigger signal, the trigger signal is input into the time base control unit, at this time, the CPU generates a sampling start signal to enable the time base control unit, the time base control unit receives the enable signal and then sends a sampling clock signal to the ADC to respond to the trigger signal, at the same time, an address counter of the time base control unit is used for counting the sampling clock, n-bit parallel digital signals are stored in a memory under the sampling clock, a memory address is generated by the address counter, when the address counter counts to a preset value, the time base control unit generates an acquisition completion signal and outputs the acquisition completion signal to the CPU, the CPU reads out and processes the required waveform data from the memory and then outputs the waveform data to the display unit, then the CPU sends a sampling start signal to the time base control unit again to start a new round of data acquisition process;
the trigger signal is input to the trigger shielding unit at the same time, the trigger shielding unit generates a trigger shielding signal, other triggers are forbidden in the trigger shielding signal period in response to the rising edge of the trigger signal, the trigger shielding signal is always high in the period, the high time interval is controlled by the CPU, the trigger shielding unit provides the same trigger pulse edge to the time base control unit by adjusting the time interval of the trigger shielding signal, the CPU reads data from the memory at the same point of each acquisition period, and the repeated waveform is stably displayed on the display unit.
In addition, the invention also provides a method for measuring the complex pulse modulation sequence based on the FPGA, which adopts the circuit for measuring the complex pulse modulation sequence based on the FPGA and specifically comprises the following steps:
step 1: the microwave millimeter wave pulse modulation signal enters a peak probe, and enters a preamplifier after being subjected to wave detection and logarithmic amplification by the peak probe;
step 2: the preamplifier is used for carrying out preamplifier on the input signal of the probe and then dividing the input signal into two paths, wherein one path of the input signal is transmitted to the post amplifier, and the other path of the input signal is transmitted to the trigger unit;
and step 3: when the signal is transmitted to the post-amplifier, the post-amplifier performs post-amplification on the signal and then transmits the signal to the ADC, and the ADC converts the input signal of the analog probe into an n-bit parallel digital signal under the sampling clock of the time base control unit;
and 4, step 4: when the signal is transmitted to the trigger unit, the trigger unit compares the signal with a trigger level to generate a trigger signal, the signal is divided into two paths, one path is transmitted to the time base control unit, and the other path is transmitted to the trigger shielding unit;
and 5: when the signal is transmitted to the time base control unit, the CPU generates a sampling start signal to enable the time base control unit, the time base control unit receives the enable signal and then sends a sampling clock signal to the ADC response trigger signal, meanwhile, an address counter of the time base control unit is used for counting the sampling clock, n-bit parallel digital signals are stored in a memory under the sampling clock, a storage address is generated by the address counter, when the address counter counts to a preset value, the time base control unit generates an acquisition completion signal and outputs the acquisition completion signal to the CPU, the CPU reads and processes required waveform data from the memory and then outputs the waveform data to a display unit, and then the CPU sends the sampling start signal to the time base control unit again to start a new round of data acquisition process;
step 6: when the signal is transmitted to the trigger shielding unit, the trigger shielding unit generates a trigger shielding signal, other triggers are forbidden in the trigger shielding signal period in response to the rising edge of the trigger signal, the trigger shielding signal is always high in the period, the high time interval is controlled by the CPU, the trigger shielding unit provides the same trigger pulse edge to the time base control unit by adjusting the time interval of the trigger shielding signal, the CPU reads data from the memory at the same point of each acquisition period, and the repeated waveform stably displays on the display unit
The invention has the following beneficial technical effects:
the invention realizes the stable measurement of a complex pulse modulation sequence through trigger shielding, realizes any pulse edge in the pulse sequence as a trigger edge through time delay triggering and event delay triggering functions, and completes the detail measurement of any pulse edge under a fast time base; the trigger shielding system is realized in the FPGA, an external circuit is not required to be added, the stability and the reliability are high, and the application range of the peak power analyzer is expanded.
Drawings
Fig. 1 is a schematic diagram of a complex pulse modulation sequence.
Fig. 2 is a schematic block diagram of the circuit of the present invention.
Fig. 3 is a functional block diagram of the trigger mask unit in generating the trigger mask signal.
Fig. 4 is a timing diagram of the main signals in fig. 3.
Wherein, 10-peak probe; 12-a preamplifier; 14-a post-amplifier; 16-ADC; 18-a memory; 20-a trigger unit; 22-a time base control unit; 24-FPGA; 26-a CPU; 28-a display unit; 30-trigger shielding unit; 40-trigger shielding counting module; 42-first D flip-flop; 44-a second D flip-flop; 46-a first not gate; 48-AND gate; 50-a second not gate; 52-a time delay trigger module; event delay trigger module 54.
Detailed Description
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 2 is a functional block diagram of a peak power analyzer with a trigger mask function implemented within FPGA 24. The microwave millimeter wave pulse modulation signal enters a preamplifier 12 of a peak power analyzer host after being detected and logarithmically amplified by a peak probe 10, and the signal enters a post-amplifier 14 after being preamplified. The probe input signal is adjusted to the appropriate level by the pre-amplifier 12 and post-amplifier 14, enters the ADC16, and is converted to an n-bit parallel digital signal under the sampling clock of the time base control unit 22.
The signal from the preamplifier 12 is also input to the trigger unit 20, compared with the trigger level to generate a trigger signal (TRIG), which is input to the time base control unit 22, at which time the CPU26 generates a sampling start signal to enable the time base control unit 22. The time base control unit receives the enable signal and sends a sampling clock signal to the ADC16 in response to the trigger signal. At the same time, the sampling clock is counted using an address counter of the time base control unit 22, and the n-bit parallel digital signal is stored in the memory 18 under the sampling clock, the storage address being generated by the address counter. When the address counter counts to a preset value, the time base control unit generates a collection completion signal to the CPU26, and the CPU26 reads out the required waveform data from the memory and processes it to the display unit 28. The CPU then sends a sample start signal again to the time base control unit 22 to start a new round of data acquisition.
A trigger signal (TRIG) is simultaneously input to the trigger shielding unit 30, and the trigger shielding circuit generates a trigger shielding signal in response to a rising edge of the trigger signal. Other triggers are disabled during the trigger mask signal, during which time the trigger mask signal is high. The high time interval is controlled by the CPU26 and the trigger mask unit 30 may provide the same trigger pulse edge to the time base control unit 22 by adjusting the time interval of the trigger mask signal. The memory 18 starts data acquisition at the same point of each acquisition cycle, and therefore, the repetitive waveform can be stably displayed on the display unit 28.
Fig. 3 is a detailed functional block diagram of the trigger mask unit 30 of fig. 2, implemented in the FPGA24, for generating the trigger mask signal (HOLDOFF _ TRIG). The input end of the trigger mask counting module 40 includes a GATE signal GATE and a trigger mask counter HOLDOFF _ CNT, which are provided by the CPU26, the CLOCK signal CLOCK is generated by frequency multiplication of the external crystal oscillator input to the FPGA24, and the trigger mask signal HOLDOFF _ TRIG is output by the second D flip-flop 44. The trigger mask count block 40 outputs the TRIG _ CLR input to the D terminal of the first D flip-flop 42, and is also connected to the input terminal of the first NOT gate 46. The CLOCK input end of the D flip-flop is connected with a CLOCK signal CLOCK, the output Q end and the output end of the first NOT gate 46 are connected with the input end AND of an AND gate 48, the output end of the AND gate 48 is connected with the input end of a second NOT gate 50, the output end of the second NOT gate 50 is connected with the CLRN input end of the second D flip-flop 44, the D input end and the PRN input end of the second D flip-flop 44 are connected high, the CLOCK input end is connected with a TRIG, and the output end is a trigger mask signal HOLDOFF _ TRIG and is connected with the input end.
The trigger mask signal HOLDOFF _ TRIG enters the inputs of the TIME delay trigger block 52 and the event delay trigger block 54, the inputs of the TIME delay trigger block 52 further include a TIME delay GATE signal TIME _ GATE and a TIME delay counter TIME _ CNT, which are provided by the CPU26, and the TIME delay trigger block 52 outputs a TIME delay trigger signal TIME _ TRIG. The input of the EVENT delay trigger block 54 further includes an EVENT delay GATE signal EVENT _ GATE and an EVENT delay counter EVENT _ CNT, which are provided by the CPU26, and the EVENT delay trigger block 54 outputs an EVENT delay trigger signal EVENT _ TRIG. The TIME delay trigger signal TIME _ TRIG, the EVENT delay trigger signal EVENT _ TRIG, and the trigger mask signal HOLDOFF _ TRIG are input to the gate switch 56, and the system trigger signal SYS _ TRIG is output.
Fig. 4 is a timing diagram of main signals in fig. 3. When the GATE signal GATE input to the trigger mask count block 40 is pulled low, counting is started at a rising edge of the trigger mask signal HOLDOFF _ TRIG, the output TRIG _ CLR of the trigger mask counter 40 is pulled high, and when a preset value is counted, the TRIG _ CLR is pulled low. The output of the first D flip-flop 42 and the TRIG _ CLR are combined through an inverter and an and gate to generate the HOLDOFF _ CLR signal, which goes low and high for one clock cycle when the TRIG _ CLR signal goes low, and then is input to the CLRN input of the second D flip-flop 44. When TRIG _ CLR is low, the output HOLDOFF _ TRIG of the second D flip-flop 44 is low, when TRIG _ CLR is high, the second D flip-flop 44 is enabled, during which HOLDOFF _ TRIG is pulled high after detecting the rising edge of TRIG, and when TRIG _ CLR is pulled low again, HOLDOFF _ TRIG goes low. Thus the pulses of the trigger signal TRIG, which are dashed lines, are masked and HOLDOFF _ TRIG captures only the first pulse rising edge of the trigger signal TRIG.
When the GATE signal TIME _ GATE input to the TIME delay trigger block 52 is pulled low, the delay TIME starts to be counted at the rising edge of the trigger mask signal HOLDOFF _ TRIG, the TIME delay trigger signal TIME _ TRIG is pulled low after the counting is completed, the TIME delay trigger signal TIME _ TRIG is pulled high at the first rising edge of the trigger signal TRIG, and then the rising edge of the trigger mask signal HOLDOFF _ TRIG is continuously detected, so that the pulse signal after any delay TIME can be obtained.
When the GATE signal EVENT _ GATE input to the EVENT delay trigger module 54 is pulled low, the number of delay EVENTs (rising edge of the trigger signal TRIG) starts to be counted at the rising edge of the trigger mask signal HOLDOFF _ TRIG, the EVENT delay trigger signal EVENT _ TRIG is pulled low after the counting is completed, the EVENT delay trigger signal EVENT _ TRIG is pulled high at the first rising edge of the trigger signal TRIG, and then the rising edge of the trigger mask signal HOLDOFF _ TRIG is continuously detected, so that a pulse signal after any delay EVENT can be obtained.
It is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make modifications, alterations, additions or substitutions within the spirit and scope of the present invention.
Claims (1)
1. A complex pulse modulation sequence measuring method based on FPGA is characterized in that: the method comprises the following steps of adopting a complex pulse modulation sequence measuring circuit based on an FPGA, wherein the circuit specifically comprises the FPGA, a peak probe, a preamplifier, a post amplifier, an ADC, a trigger unit, a CPU, a memory and a display unit; the FPGA comprises a time base control unit and a trigger shielding unit;
the peak probe is configured to be used for detecting and logarithmically amplifying the microwave millimeter wave pulse modulation signal to obtain a probe input signal;
a preamplifier configured for pre-amplifying a probe input signal;
a post-amplifier configured for post-amplifying the pre-amplified probe input signal;
an ADC configured to convert the post-amplified analog probe input signal to a digital signal;
the trigger unit is used for comparing the signal amplified by the preamplifier with a trigger level and generating a trigger signal;
a CPU configured to generate a sampling start signal to enable the time base control unit; when the time base control unit generates an acquisition completion signal and outputs the acquisition completion signal to the CPU, the CPU reads out and processes the required waveform data from the memory and outputs the processed waveform data to the display unit, and then sends a sampling start signal to the time base control unit again;
a memory configured to store waveform data;
a display unit configured to display a repetitive waveform;
the time base control unit is configured to receive an enabling signal sent by the CPU, send a sampling clock signal to the ADC, respond to a trigger signal, and generate an acquisition completion signal and output the acquisition completion signal to the CPU when an address counter of the time base control unit counts a preset value;
the trigger shielding unit is used for generating a trigger shielding signal, and the trigger shielding unit provides the same trigger pulse edge-to-time base control unit by adjusting the time interval of the trigger shielding signal;
the microwave millimeter wave pulse modulation signal enters a preamplifier after being detected and logarithmically amplified by a peak probe, a probe input signal enters a post amplifier after being preamplified, enters an ADC after being amplified by the post amplifier, and an analog probe input signal is converted into an n-bit parallel digital signal under a sampling clock of a time base control unit;
the signal amplified by the preamplifier is also input into the trigger unit, and compared with the trigger level to generate a trigger signal, the trigger signal is input into the time base control unit, at this time, the CPU generates a sampling start signal to enable the time base control unit, the time base control unit receives the enable signal and then sends a sampling clock signal to the ADC to respond to the trigger signal, at the same time, an address counter of the time base control unit is used for counting the sampling clock, n-bit parallel digital signals are stored in a memory under the sampling clock, a memory address is generated by the address counter, when the address counter counts to a preset value, the time base control unit generates an acquisition completion signal and outputs the acquisition completion signal to the CPU, the CPU reads out and processes the required waveform data from the memory and then outputs the waveform data to the display unit, then the CPU sends a sampling start signal to the time base control unit again to start a new round of data acquisition process;
the trigger signal is input to the trigger shielding unit at the same time, the trigger shielding unit generates a trigger shielding signal, other triggers are forbidden in the trigger shielding signal period in response to the rising edge of the trigger signal, the trigger shielding signal is always high in the period, the high time interval is controlled by the CPU, the trigger shielding unit provides the same trigger pulse edge to the time base control unit by adjusting the time interval of the trigger shielding signal, the CPU reads data from the memory at the same point of each acquisition period, and the repeated waveform is stably displayed on the display unit; the method specifically comprises the following steps:
step 1: the microwave millimeter wave pulse modulation signal enters a peak probe, and enters a preamplifier after being subjected to wave detection and logarithmic amplification by the peak probe;
step 2: the preamplifier is used for carrying out preamplifier on the input signal of the probe and then dividing the input signal into two paths, wherein one path of the input signal is transmitted to the post amplifier, and the other path of the input signal is transmitted to the trigger unit;
and step 3: when the signal is transmitted to the post-amplifier, the post-amplifier performs post-amplification on the signal and then transmits the signal to the ADC, and the ADC converts the input signal of the analog probe into an n-bit parallel digital signal under the sampling clock of the time base control unit;
and 4, step 4: when the signal is transmitted to the trigger unit, the trigger unit compares the signal with a trigger level to generate a trigger signal, the signal is divided into two paths, one path is transmitted to the time base control unit, and the other path is transmitted to the trigger shielding unit;
and 5: when the signal is transmitted to the time base control unit, the CPU generates a sampling start signal to enable the time base control unit, the time base control unit receives the enable signal and then sends a sampling clock signal to the ADC response trigger signal, meanwhile, an address counter of the time base control unit is used for counting the sampling clock, n-bit parallel digital signals are stored in a memory under the sampling clock, a storage address is generated by the address counter, when the address counter counts to a preset value, the time base control unit generates an acquisition completion signal and outputs the acquisition completion signal to the CPU, the CPU reads and processes required waveform data from the memory and then outputs the waveform data to a display unit, and then the CPU sends the sampling start signal to the time base control unit again to start a new round of data acquisition process;
step 6: when the signal is transmitted to the trigger shielding unit, the trigger shielding unit generates a trigger shielding signal, other triggers are forbidden in the trigger shielding signal period in response to the rising edge of the trigger signal, the trigger shielding signal is always high in the period, the high time interval is controlled and realized by the CPU, the trigger shielding unit provides the same trigger pulse edge to the time base control unit by adjusting the time interval of the trigger shielding signal, the CPU reads data from the memory at the same point of each acquisition period, and the repeated waveform is stably displayed on the display unit.
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| CN112084731B (en) * | 2020-08-04 | 2024-03-29 | 中电科思仪科技股份有限公司 | FPGA digital circuit and method for improving peak power measurement trigger dynamic range |
| CN112051442B (en) * | 2020-08-05 | 2023-08-25 | 中电科思仪科技股份有限公司 | Method for improving time parameter measurement speed in microwave peak power measurement |
| CN112798857B (en) * | 2020-12-22 | 2022-10-11 | 中电科思仪科技股份有限公司 | Peak power multi-pulse parameter measuring method |
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