CN109285769A - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
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- CN109285769A CN109285769A CN201710595667.4A CN201710595667A CN109285769A CN 109285769 A CN109285769 A CN 109285769A CN 201710595667 A CN201710595667 A CN 201710595667A CN 109285769 A CN109285769 A CN 109285769A
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- 238000000034 method Methods 0.000 title claims abstract description 120
- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 150000002500 ions Chemical group 0.000 claims abstract description 256
- 238000000576 coating method Methods 0.000 claims abstract description 163
- 229910052751 metal Inorganic materials 0.000 claims abstract description 162
- 239000002184 metal Substances 0.000 claims abstract description 162
- 239000011248 coating agent Substances 0.000 claims abstract description 160
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 75
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 239000007787 solid Substances 0.000 claims abstract description 35
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 224
- 239000000463 material Substances 0.000 claims description 90
- 238000000137 annealing Methods 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 230000000903 blocking effect Effects 0.000 claims description 17
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 16
- 239000011229 interlayer Substances 0.000 claims description 13
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 238000011065 in-situ storage Methods 0.000 claims description 6
- 230000026267 regulation of growth Effects 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims 1
- 239000011241 protective layer Substances 0.000 description 19
- 125000006850 spacer group Chemical group 0.000 description 18
- 238000000926 separation method Methods 0.000 description 11
- -1 boron ion Chemical class 0.000 description 10
- 229910052732 germanium Inorganic materials 0.000 description 10
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000005036 potential barrier Methods 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910003697 SiBN Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
- H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A kind of semiconductor devices and forming method thereof, wherein method includes: offer substrate, and substrate includes the firstth area；The first doped region is formed in the firstth area of substrate；Doped with the first ion group in the first coating of the first doped region surface formation, the first coating, the first ion group includes that the first conductive ion and first stop ion；The first coating is set to form first metal silicide layer with the first ion group using the first silication technique for metal, first stops ion to be less than the solid solubility in the first coating in the solid solubility in the first metal silicide layer.The method improves the performance of semiconductor devices.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor devices and forming method thereof.
Background technique
MOS transistor is one of most important element in modern integrated circuits.The basic structure of MOS transistor includes: half
Conductor substrate；Positioned at the gate structure of semiconductor substrate surface；Source region in the semiconductor substrate of gate structure side；It is located at
Drain region in the semiconductor substrate of the gate structure other side.
The working principle of MOS transistor is: by applying voltage in gate structure, adjusting the electricity of gate structure bottom channel
Stream generates switching signal.
However, the performance for the semiconductor devices that the MOS transistor that the prior art is formed is constituted is poor.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor devices and forming method thereof, to improve the property of semiconductor devices
Energy.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, comprising: provide substrate, substrate
Including the firstth area；The first doped region is formed in the firstth area of substrate；The first coating is formed on the first doped region surface, first covers
Doped with the first ion group in cap rock, the first ion group includes that the first conductive ion and first stop ion；Using the first metal
Silicification technics makes the first coating form first metal silicide layer with the first ion group, and first stops ion in the first gold medal
The solid solubility belonged in silicide layer is less than the solid solubility in the first coating.
Optionally, first silication technique for metal includes: to form metal layer in first cover surface；It is moved back
Fire process makes the material of metal layer and the first coating react and form first metal silicide layer.
Optionally, annealing process is carried out, metal layer and the first cover surface material is made to react and form first gold medal
Belong to silicide layer, and forms the first metal silicide layer bottom with the first coating of part of metal layer reaction and be located at first
First middle layer on doped region surface；First metal silicide layer is located at the first interlayer surfaces；Carry out the process of annealing process
In, the part first in the first coating stops ion releasing and diffuses in the first doped region；First in first doped region
The first conductive ion in the first metal silicide layer of ion barrier and the first middle layer is stopped to diffuse in the first doped region.
Optionally, annealing process is carried out, reacts the first covering layer material of metal layer and metal layer bottom and shape completely
At first metal silicide layer, the first metal silicide layer is located at the first doped region surface；Carry out the process of annealing process
In, the part first in the first coating stops ion releasing and diffuses in the first doped region；First in first doped region
The first conductive ion in the first metal silicide layer of ion barrier is stopped to diffuse in the first doped region.
Optionally, the first conductive ion before carrying out first silication technique for metal, in first coating
Concentration be 1E18atom/cm3~5E21atom/cm3, the concentration of the first blocking ion is in first coating
1E17atom/cm3~1E21atom/cm3。
Optionally, the material of first coating is the silicon or germanium silicon doped with the first ion group.
Optionally, described first stops ion to be the combination of N ion, C ion or both.
Optionally, when firstth area is used to form P-type transistor, described first stops ion to be N ion；When described
When firstth area is used to form N-type transistor, described first stops ion to be C ion.
Optionally, when firstth area is used to form P-type transistor, the conduction type of first conductive ion is P
Type；When firstth area is used to form N-type transistor, the conduction type of first conductive ion is N-type.
Optionally, the method for forming first coating includes: to cover in the first doped region surface epitaxial growth first
Layer；The first ion group is adulterated in situ in the first coating during extension one coating of growth regulation.
Optionally, the first ion group further includes the first lattice alienation ion, and the first lattice alienation ion is in the first gold medal
The solid solubility belonged in silicide layer is less than the solid solubility in the first coating.
Optionally, the first lattice alienation ion is the combination of Sb ion, Ga ion or both.
Optionally, when firstth area is used to form P-type transistor, the first lattice alienation ion is Sb ion；Work as institute
When stating the firstth area and being used to form N-type transistor, the first lattice alienation ion is Ga ion.
Optionally, the first lattice alienation ion before carrying out first silication technique for metal, in the first coating
Concentration be 1E18atom/cm3~1E21atom/cm3。
Optionally, further includes: before forming the first doped region, first grid knot is formed in firstth area of substrate
Structure；After forming the first doped region, the first doped region is located in the substrate of first grid structure two sides.
Optionally, the substrate further includes the secondth area；The forming method of the semiconductor devices further include: forming first
After coating, and before carrying out the first silication technique for metal, the second doped region is formed in the secondth area of substrate；It is mixed second
The surface Za Qu forms the second coating, doped with the second ion group in the second coating, the second ion group include second it is conductive from
Son and second stops ion；The second coating is set to form second metal with the second ion group using the second silication technique for metal
Silicide layer, second stops ion to be less than the solid solubility in the second coating in the solid solubility in the second metal silicide layer.
Optionally, the second ion group further includes the second lattice alienation ion；Second lattice alienation ion is in the second gold medal
The solid solubility belonged in silicide layer is less than the solid solubility in the second coating.
Optionally, further includes: after forming the first coating and the second coating, and carrying out the first silication technique for metal
Before the second silication technique for metal, dielectric layer is formed, the dielectric layer covers the first coating, the second coating and substrate；
The first through hole for running through dielectric layer is formed in the dielectric layer, first through hole exposes the first cover surface；Form first
After through-hole, the first silication technique for metal is carried out；The second through-hole for running through dielectric layer is formed in the dielectric layer, the second through-hole is sudden and violent
Expose the second cover surface；After forming the second through-hole, the second silication technique for metal is carried out.
Optionally, the substrate includes semiconductor substrate and the fin in semiconductor substrate, and the fin includes position
The first fin in the firstth area of semiconductor substrate；When the firstth area is used to form P-type transistor, the material of first fin
Including monocrystalline Ge；When the firstth area is used to form N-type transistor, the material of first fin includes InGaAs.
Semiconductor devices is formed by using above-mentioned any one method the present invention also provides a kind of.
Compared with prior art, technical solution of the present invention has the advantage that
In the forming method for the semiconductor devices that technical solution of the present invention provides, doped with the first ion in the first coating
Group, the first ion group include the first conductive ion, and the first metal silicide layer by the first coating in the first metallic silicon chemical industry
Silicification reaction occurs under skill and is formed, therefore there is the first conductive ion, the first metal silicide in the first metal silicide layer
The resistance of layer is smaller.First ion group further includes the first blocking ion, and first stops ion in the first metal silicide layer
Solid solubility be less than solid solubility in the first coating, therefore, during the first silication technique for metal, the first coating
In part first stop ion can be precipitated and diffuse in the first doped region.First blocking ion occupies the first doped region surface
The interstitial void of material, the first blocking ion in the first doped region can stop in the first metal silicide layer first it is conductive from
Son diffuses in the first doped region, reduces the loss of the first conductive ion in the first metal silicide layer, partly leads to improve
The performance of body device.
Detailed description of the invention
Fig. 1 to Figure 10 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
Specific embodiment
As described in background, the performance for the semiconductor devices that the prior art is formed is poor.
A kind of method of the formation of semiconductor devices includes: offer substrate, has gate structure in the substrate；In grid
Doped region is respectively formed in the substrate of structure two sides；Doped with conductive ion in doped region surface formation coating, coating；
Coating is set to form the metal silicide layer with conductive ion using silication technique for metal.
However, the performance for the semiconductor devices that the above method is formed is poor, it has been investigated that, reason is:
Effect in coating doped with conductive ion includes: the resistance for reducing coating.Pass through metallic silicon chemical industry in this way
The resistance for the metal silicide layer that skill is formed is smaller.
In the entire manufacturing process of semiconductor devices, need after heat treatment.During heat treatment, metal silicide
Conductive ion in layer is easy to diffuse in doped region and around metal silicide layer in other structures under the driving of heat treatment,
The conductive ion in metal silicide layer is caused to have biggish loss, it is difficult to effectively reduce the resistance of metal silicide layer.
On this basis, the present invention provides a kind of forming method of semiconductor devices, forms the on the first doped region surface
One coating, doped with the first ion group in the first coating, the first ion group include the first conductive ion and first stop from
Son；Using the first silication technique for metal make the first coating formed have the first ion group the first metal silicide layer, first
Ion is stopped to be less than the solid solubility in the first coating in the solid solubility in the first metal silicide layer.The method makes partly to lead
The performance of body device improves.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 to Figure 10 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
With reference to Fig. 1, substrate is provided, substrate includes the first area A.
It is fin formula field effect transistor as example using semiconductor devices in the present embodiment.In other embodiments, it partly leads
Body device is triode or diode.
In the present embodiment, substrate includes semiconductor substrate 200 and the fin in semiconductor substrate 200.In other realities
It applies in example, substrate is the semiconductor substrate of plane formula.
The semiconductor substrate 200 can be monocrystalline silicon, polysilicon or amorphous silicon.Semiconductor substrate 200 be also possible to silicon,
The semiconductor materials such as germanium, SiGe.In the present embodiment, the material of semiconductor substrate 200 is monocrystalline silicon.
The fin is formed by patterned semiconductor substrate 200, alternatively, forming fin material on a semiconductor substrate
Layer, graphical fin material layer and form fin.
The material of the fin is identical with the material of semiconductor substrate 200.Alternatively, the material and semiconductor substrate of fin
200 material is not identical.
The semiconductor substrate 200 includes the first area A, correspondingly, fin includes being located at 200 first area A of semiconductor substrate
On the first fin 211.The semiconductor substrate 200 further includes the second area B, correspondingly, fin further includes being located at semiconductor to serve as a contrast
The second fin 212 on 200 second area B of bottom.In other embodiments, semiconductor substrate does not include the secondth area.
The firstth area A is used to form P-type transistor, and the second area B is used to form N-type transistor；Alternatively, the first area A is used
In forming N-type transistor, the second area B is used to form P-type transistor.
In the present embodiment, the firstth area A is used to form P-type transistor, correspondingly, the material of first fin 211
Electric conductivity for monocrystalline germanium, the first fin 211 is preferable；Second area B is used to form N-type transistor, correspondingly, second fin
The material in portion 212 is InGaAs, and the electric conductivity of the second fin 212 is preferable.
In the present embodiment, also there is separation layer 203, separation layer on the 200 first area A of semiconductor substrate and the second area B
The partial sidewall of 203 the first fins 211 of covering and the partial sidewall of the second fin 212.The top surface of the separation layer 203 is low
In the top surface of the first fin 211 and the top surface of the second fin 212.The material of the separation layer 203 includes oxidation
Silicon.
In the present embodiment, there is first grid structure 221 on the firstth area of substrate A, have on the secondth area of substrate B
Second grid structure 222.First grid structure 221 includes the first gate dielectric layer 223 on the firstth area of substrate A and is located at the
First gate electrode layer 224 on one gate dielectric layer 223.Second grid structure 222 includes the second gate on the secondth area of substrate B
Dielectric layer 225 and the second gate electrode layer 226 on the second gate dielectric layer 225.
Specifically, first grid structure 221 across the first fin 211, cover the first fin 211 atop part surface and
Partial sidewall surface.Second grid structure 222 is across the atop part surface and portion of the second fin 212, the second fin 212 of covering
Divide sidewall surfaces.The part that first gate dielectric layer 223 is located at first area's A separation layer, 203 part of the surface, covers the first fin 211
Top surface and partial sidewall surface.Second gate dielectric layer 225 is located at second area's B separation layer, 203 part of the surface, the second fin of covering
The atop part surface and partial sidewall surface in portion 212.In the present embodiment, the first gate dielectric layer 223 and the second gate dielectric layer 225
Material be silica.In other embodiments, the material of the first gate dielectric layer and the second gate dielectric layer is high K dielectric material (K
Greater than 3.9).The material of first gate electrode layer 224 and the second gate electrode layer 226 is polysilicon.
In the present embodiment, the top surface of first grid structure 221 also has first grid protective layer 231, the second gate
The top surface of pole structure 222 has second gate protective layer 232.The first grid protective layer 231 and second gate protective layer 232
Material is SiN, SiCN, SiBN or SiON.
With reference to Fig. 2, the first doped region 241 is formed in the firstth area of substrate A.
In the present embodiment, the first doped region 241 is located in the substrate of 221 two sides of first grid structure, specifically, the
One doped region 241 is located in the first fin 211 of 221 two sides of first grid structure.
In the present embodiment, when the firstth area A is used to form P-type transistor, the material of the first doped region 241 is doping
There is the germanium silicon of the first conductive ion, the conduction type of the first conductive ion is p-type, such as boron ion；When the firstth area A is used for shape
When at N-type transistor, the material of the first doped region 241 is the silicon doped with the first conductive ion, the conduction of the first conductive ion
Type is N-type, such as phosphonium ion.
The first conductive ion in first doped region 241 is doped into the first doped region 241 by way of ion implanting；
Alternatively, the first conductive ion in the first doped region 241 is doped into the first doped region 241 by way of adulterating in situ.
It should be noted that in the present embodiment, before forming the first doped region 241, further includes: in the firstth area of substrate A
With the first spacer material floor 251 is formed on the second area B, specifically, the first spacer material floor 251 is located at first area's A separation layer 203
Surface, 211 surface of the first fin, first grid structure 221 and first grid protective layer 231 side wall and first grid protective layer
231 top surface, the first spacer material floor 251 are also located at second area's B separation layer, 203 surface, 212 surface of the second fin,
The top surface of the side wall and second gate protective layer 232 of two gate structures 222 and second gate protective layer 232；It is etched back to first
The first spacer material floor 251 of area A is until expose top surface, the Yi Ji of first grid protective layer 231 and the first fin 211
The surface of one area's A separation layer 203；Later, etching is located at 221 side wall first of first grid structure 221 and first grid structure
First fin 211 of the two sides of spacer material layer 251, in 221 side wall first of first grid structure 221 and first grid structure
The first recess is formed in first fin 211 of the two sides of spacer material layer 251；With the first spacer material floor 251 of the second area B,
The first of first spacer material layer 251 of 231 side wall of first grid structure 221 and first grid protective layer, 211 side wall of the first fin
Spacer material layer 251 and first grid protective layer 231 are exposure mask, one doped region 241 of extension growth regulation in the first recess.
In the present embodiment, during etching the first fin 211 of 221 two sides of first grid structure, the has also been etched
First spacer material layer 251 of one fin, 211 side wall.
In other embodiments, when substrate does not include the secondth area, the first spacer material layer is not located at second and separates absciss layer
Surface, the second fin portion surface, the side wall of second grid structure and second gate protective layer and second gate protective layer top table
Face.
With reference to Fig. 3, the first coating 261 is formed on 241 surface of the first doped region, doped with the in the first coating 261
One ion group, the first ion group include that the first conductive ion and first stop ion.
The material of first coating 261 is the silicon or germanium silicon doped with the first ion group.
The concentration of first conductive ion is greater than the first conductive ion in the first doped region 241 in first coating 261
Concentration.
When the material of the first doped region 241 is the germanium silicon doped with the first conductive ion, the material of the first coating 261 is
Doped with the first ion group germanium silicon when, germanium ion molal quantity occupies silicon ion mole in the material germanium silicon of the first coating 261
Several ratios is the first ratio, and germanium ion molal quantity occupies the ratio of silicon ion molal quantity in the material germanium silicon of the first doped region 241
Example is the second ratio, and for the first ratio less than the second ratio, benefit includes: to be conducive to subsequent first coating, 261 silicification reaction
Meanwhile keeping the potential barrier between the first metal silicide layer being subsequently formed and the first doped region 241 lower.
The method for forming first coating 261 includes: in 241 the first coating of surface epitaxial growth of the first doped region
261；The first ion group is adulterated in situ in the first coating 261 during one coating 261 of extension growth regulation.
Described first stops ion to be the combination of N ion, C ion or both.
It is subsequent in the first silication technique for metal, first blocking ion can be precipitated and diffuse to from the first coating 261
In first doped region 241, first in the first doped region 241 stops ion for stopping the first conduction in the first coating 261
The ion of ion diffusion, the first blocking ion is selected according to the interstitial void of the first doped region 241.Due between the lattice of germanium silicon
Gap is greater than the interstitial void of silicon, and therefore, when the firstth area A is used to form P-type transistor, the material of the first doped region 241 is
Doped with the first conductive ion germanium silicon when, select first stop ion ionic radius it is larger, when the firstth area A be used for shape
At N-type transistor, when the material of the first doped region 241 is the silicon doped with the first conductive ion, first is selected to stop ion
Ionic radius is smaller.In a specific embodiment, when the firstth area A is used to form P-type transistor, first resistance
Gear ion is N ion；When the firstth area A is used to form N-type transistor, described first stops ion to be C ion.
When firstth area is used to form P-type transistor, the conduction type of first conductive ion is p-type；Work as institute
When stating the firstth area and being used to form N-type transistor, the conduction type of first conductive ion is N-type.
The effect of first conductive ion includes: the resistance for reducing the first coating 261 in first coating 261.
The resistance of first coating 261 reduces, and the resistance of subsequent first metal silicide layer reduces, correspondingly, the
Potential barrier between one metal silicide layer and the first doped region 241 reduces.
The concentration of the first conductive ion in first coating 261 is 1E18atom/cm3~5E21atom/cm3。
First in the first metal silicide layer being subsequently formed stops the solid solubility of ion less than in the first coating 261
First stops the solid solubility of ion, during subsequent progress corresponding annealing process, for being converted into the first metal silication
The first blocking ion in first coating 261 of nitride layer is precipitated from the first coating 261.
First stops the concentration of ion to be 1E17atom/cm in first coating 2613~1E21atom/cm3.Selection
The meaning of this range include: in the first coating 261 first stop ion doping it is in a saturated state, and reduce technique wave
Take.
In the present embodiment, the first ion group further includes the first lattice alienation ion.In other embodiments, first from
Subgroup does not include the first lattice alienation ion.
The effect of first lattice alienation ion include: subsequent the first lattice alienation being precipitated from the first coating 261 from
Son diffuses into the first doped region 241, is distorted the lattice of 241 surfacing of the first doped region, the first lattice of part
Alienation ion occupies the position of silicon or germanium in 241 lattice of the first doped region, and part silicon or germanium enter 241 lattice of the first doped region
In gap digit.241 surfacing of the first doped region can be further increased in this way stops the first conduction in the first coating 261
The ability of ion diffusion.
First lattice alienation ion is less than in the first coating 261 in the solid solubility in subsequent first metal silicide layer
Solid solubility.
The first lattice alienation ion is the combination of Sb ion, Ga ion or both.
In one embodiment, when firstth area is used to form P-type transistor, the first lattice alienation ion be Sb from
Son；When firstth area is used to form N-type transistor, the first lattice alienation ion is Ga ion.
The concentration of the first lattice alienation ion in first coating 261 is 1E18atom/cm3~1E21atom/
cm3。
Then, the first coating 261 is made to form first metal with the first ion group using the first silication technique for metal
Silicide layer, first stops ion to be less than the solid solution in the first coating 261 in the solid solubility in the first metal silicide layer
Degree.
In the present embodiment, further includes: after forming the first coating 261, and carry out the first silication technique for metal it
Before, the second doped region is formed in the secondth area of substrate B；In the second coating of the second doped region surface formation, the second coating
Doped with the second ion group, the second ion group includes that the second conductive ion and second stop ion.
With reference to Fig. 4, is formed after the first coating 261, form the second doped region 242 in the secondth area of substrate B；Second
242 surface of doped region forms the second coating 262, and doped with the second ion group in the second coating 262, the second ion group includes
Second conductive ion and second stops ion.
In the present embodiment, the second doped region 242 is located in the substrate of 222 two sides of second grid structure, specifically, the
Two doped regions 242 are located in the second fin 212 of 222 two sides of second grid structure.
In the present embodiment, when the secondth area B is used to form P-type transistor, the material of the second doped region 242 is doping
There is the germanium silicon of the second conductive ion, the conduction type of the second conductive ion is p-type, such as boron ion；When the secondth area B is used for shape
When at N-type transistor, the material of the second doped region 242 is the silicon doped with the second conductive ion, the conduction of the second conductive ion
Type is N-type, such as phosphonium ion.
The second conductive ion in second doped region 242 is doped into the second doped region 242 by way of ion implanting；
Alternatively, the second conductive ion in the second doped region 242 is doped into the second doped region 242 by way of adulterating in situ.
It should be noted that in the present embodiment, before forming the second doped region 242, further includes: in the firstth area of substrate A
With second side walling bed of material 252 is formed on the second area B, specifically, second side walling bed of material 252 is located at first area's A separation layer 203
Surface, 261 surface of the first coating, 251 surface of the first spacer material floor of the first area A, first grid protective layer 231 top table
Face, second side walling bed of material 252 are also located at the surface of the second area B first grid protective layer 231；It is etched back to the first side of the second area B
The walling bed of material 251 and second side walling bed of material 252 are until expose the top table of second gate protective layer 232 and the second fin 212
203 surface of face and second area's B separation layer；Later, etching is located at second grid structure 222 and second grid structure 222
Second fin 212 of the two sides of the first spacer material layer 251 and second side walling bed of material 252 of side wall, in second grid structure
222 and 222 side wall of second grid structure the first spacer material layer 251 and second side walling bed of material 252 two sides second
The second recess is formed in fin 212；With second side walling bed of material 252 of the first area A, 222 side wall of second grid structure first
The the first spacer material layer 251 and the second side wall of spacer material layer 251 and second side walling bed of material 252,212 side wall of the second fin
Material layer 252 and second gate protective layer 232 are exposure mask, two doped region 242 of extension growth regulation in the second recess.
In the present embodiment, during etching the second fin 212 of 222 two sides of second grid structure, the has also been etched
The the first spacer material layer 251 and second side walling bed of material 252 of two fins, 212 side wall.
The concentration of second conductive ion is greater than the second conductive ion in the second doped region 242 in second coating 262
Concentration.
The material of second coating 262 is the silicon or germanium silicon doped with the second ion group.
When the material of the second doped region 242 is the germanium silicon doped with the second conductive ion, the material of the second coating 262 is
Doped with the second ion group germanium silicon when, the molar ratio of germanium ion is mixed less than second in the material germanium silicon of the second coating 262
Germanium ion molar ratio in the material germanium silicon in miscellaneous area 242.Benefit includes: to be conducive to the same of subsequent second coating silicification reaction
When, keep the potential barrier between the second metal silicide layer being subsequently formed and the second doped region 242 lower.
The method for forming second coating 262 includes: in 242 the second coating of surface epitaxial growth of the second doped region
262；The second ion group is adulterated in situ in the second coating 262 during two coating 262 of extension growth regulation.
Described second stops ion to be the combination of N ion, C ion or both.
In a specific embodiment, when the secondth area B is used to form P-type transistor, described second stop from
Son is N ion；When the secondth area B is used to form N-type transistor, described second stops ion to be C ion.
When secondth area is used to form P-type transistor, the conduction type of second conductive ion is p-type；Work as institute
When stating the secondth area and being used to form N-type transistor, the conduction type of second conductive ion is N-type.
The effect of second conductive ion includes: the resistance for reducing the second coating 262 in second coating 262.
The resistance of second coating 262 reduces, and the resistance of subsequent second metal silicide layer reduces, correspondingly, the
Potential barrier between two metal silicide layers and the second doped region 242 reduces.
The concentration of the second conductive ion in second coating 262 is 1E18atom/cm3~5E21atom/cm3。
Second in the second metal silicide layer being subsequently formed stops the solid solubility of ion less than in the second coating 262
Second stops the solid solubility of ion, during carrying out subsequent corresponding annealing process, for being converted into the second metal silication
The second blocking ion in second coating 262 of nitride layer is precipitated from the second coating 262.
Second stops the concentration of ion to be 1E17atom/cm in second coating 2623~1E21atom/cm3.Selection
The meaning of this range include: in the second coating 262 second stop ion doping it is in a saturated state, and reduce technique wave
Take.
In the present embodiment, the second ion group further includes the second lattice alienation ion.In other embodiments, second from
Subgroup does not include the second lattice alienation ion.
The effect of second lattice alienation ion include: subsequent the second lattice alienation being precipitated from the second coating 262 from
Son diffuses into the second doped region 242, is distorted the lattice of 242 surfacing of the second doped region, the second lattice of part
Alienation ion occupies the position of silicon or germanium in 242 lattice of the second doped region, and part silicon or germanium enter 242 lattice of the second doped region
In gap digit.242 surfacing of the second doped region can be further increased in this way stops the second conduction in the second coating 262
The ability of ion diffusion.
Second lattice alienation ion is less than in the second coating 262 in the solid solubility in subsequent second metal silicide layer
Solid solubility.
The second lattice alienation ion is the combination of Sb ion, Ga ion or both.
In one embodiment, when the secondth area B is used to form P-type transistor, the second lattice alienation ion is Sb
Ion；When the secondth area B is used to form N-type transistor, the second lattice alienation ion is Ga ion.
The concentration of the second lattice alienation ion in second coating 262 is 1E18atom/cm3~1E21atom/
cm3。
In the present embodiment, further includes: forming the second coating 262 using the second silication technique for metal has the second ion
Second metal silicide layer of group, second stops solid solubility of the ion in the second metal silicide layer to be less than in the second coating
Solid solubility in 262.
In the present embodiment, after forming the first coating 261 and the second coating 262, and the first metal silication is being carried out
Before technique and the second silication technique for metal, dielectric layer is formed, the dielectric layer covers the first coating 261, the second coating
262 and substrate；The first through hole for running through dielectric layer is formed in the dielectric layer, first through hole exposes the first coating 261
Surface；After forming first through hole, the first silication technique for metal is carried out；It is formed in the dielectric layer and is led to through the second of dielectric layer
Hole, the second through-hole expose 262 surface of the second coating；After forming the second through-hole, the second silication technique for metal is carried out.
In the present embodiment, the first doped region 241, the first coating 261, the second doped region 242 and the second coating 262 exist
It is formed in same manufacturing process, so that forming 242 and of technique and the second doped region of the first doped region 241, the first coating 261
The technique of second coating 262 is compatible, is integrated with the transistor of the first area's A transistor and the second area B.
With reference to Fig. 5, after forming the first coating 261 and the second coating 262, dielectric layer 270, the dielectric layer are formed
270 the first coatings 261 of covering, the second coating 262 and substrate.
The dielectric layer 270 includes the first interlayer dielectric layer 271 and the second interlayer on the first interlayer dielectric layer 271
Dielectric layer 272.The material of the dielectric layer 270 is silica or low K (K is less than 3.9) dielectric material.
Specifically, forming the first interlayer dielectric layer 271, the first interlayer dielectric layer 271 is located on the first area A and the second area B,
First grid protective layer 231 and second gate protective layer 232 are removed during forming the first interlayer dielectric layer 271, expose the
The top surface of one gate structure 221 and the top surface of second grid structure 222；After forming the first interlayer dielectric layer 271, go
Except first grid structure 221, first grid opening is formed in first the first interlayer dielectric layer of area A 271, removes second grid structure
222, second gate opening is formed in second the first interlayer dielectric layer of area B 271；The first metal gates are formed in first grid opening
Structure 281 forms the second metal gate structure 282 in second gate opening；In the first metal gate structure 281, the second metal
The second interlayer dielectric layer 272 is formed on gate structure 282 and the first interlayer dielectric layer 271.
First doped region 241 is located in the substrate of 281 two sides of the first metal gate structure, specifically, first
Doped region 241 is located in the first fin 211 of 281 two sides of the first metal gate structure.Second doped region 242 is distinguished
In the substrate of 282 two sides of the second metal gate structure, specifically, the second doped region 242 is located at the second metal gates
In second fin 212 of 282 two sides of structure.
With reference to Fig. 6, the first through hole 271 for running through dielectric layer 270 is formed in the dielectric layer 270, first through hole 271 is sudden and violent
Expose 261 surface of the first coating；The second through-hole 272 for running through dielectric layer 270 is formed in the dielectric layer 270, second is logical
Hole 272 exposes 262 surface of the second coating.
It should be noted that eliminating the second of 261 surface of the first coating during forming first through hole 271
Spacer material layer 252 exposes the first coating 261.
In the present embodiment, further includes: the third through-hole 273 for running through dielectric layer 270 is formed in the dielectric layer 270, the
Three through-holes 273 expose the top surface of the first metal gate structure 281；It is formed in the dielectric layer 270 and runs through dielectric layer
270 fourth hole 274, fourth hole 274 expose the top surface of the second metal gate structure 282.
In the present embodiment, during forming first through hole 271, the second through-hole 272, third through-hole 273 and the are formed
Four through-holes 274, simplify technique.
After forming first through hole 271, the first silication technique for metal is carried out；After forming the second through-hole 272, the second metal is carried out
Silicification technics.
First silication technique for metal includes: in 261 forming metal layer on surface of the first coating；Carry out lehr attendant
Skill makes the material of metal layer and the first coating 261 react and form the first metal silicide layer.
In the present embodiment, during carrying out the first silication technique for metal, the second silication technique for metal is carried out, is simplified
Technique.
With reference to Fig. 7, in 261 forming metal layer on surface 290 of the first coating.
The metal layer 290 is located on the side wall of first through hole 271,261 surface of the first coating and dielectric layer 270.
In the present embodiment, metal layer 290 is also located at 272 side wall of the second through-hole, 262 surface of the second coating.
In the present embodiment, metal layer 290 is also located at side wall and bottom and the side of fourth hole 274 of third through-hole 273
Wall and bottom.
The material of the metal layer 290 is metal, such as Ti, Co or Ni.
The technique for forming metal layer 290 is depositing operation, such as sputtering technology or chemical vapor deposition process.
In the present embodiment, before subsequent progress annealing process, further includes: form barrier layer on the surface of metal layer 290
291, the material on the barrier layer 291 is titanium nitride or tantalum nitride.
With reference to Fig. 8, annealing process is carried out, reacts the material of metal layer 290 and the first coating 261 and being formed has the
First metal silicide layer 301 of one ion group.
In the present embodiment, annealing process is carried out, 261 material of the first coating of 290 bottom of metal layer 290 and metal layer is made
It reacts completely and forms first metal silicide layer 301 with the first ion group, the first metal silicide layer 301 is located at first
241 surface of doped region.During carrying out annealing process, the part first in the first coating 261 stops ion releasing and expands
It is dissipated in the first doped region 241.First in first doped region 241 stops the in the first metal silicide layer of ion barrier 301
One conductive ion diffuses in the first doped region 241.
In other embodiments, annealing process is carried out, metal layer and the first cover surface material is made to react and form tool
There is the first metal silicide layer of the first ion group, and makes part the of the first metal silicide layer bottom not with metal layer reaction
One coating forms the first middle layer for being located at the first doped region surface；First metal silicide layer is located at the first middle layer table
Face；During carrying out annealing process, the part first in the first coating stops ion releasing and diffuses to the first doped region
In.First in first doped region stops the first conductive ion in the first metal silicide layer of ion barrier and the first middle layer
It diffuses in the first doped region.
Since the first blocking ion is less than in the first coating 261 in the solid solubility in the first metal silicide layer 301
Solid solubility, therefore, during the first silication technique for metal, part first in the first coating 261 stops ion meeting
It is precipitated and diffuses in the first doped region 241.First blocking ion occupies the interstitial void of 241 surfacing of the first doped region,
The first blocking ion in first doped region 241 can stop the first conductive ion in the first metal silicide layer 301 to diffuse to
In first doped region 241, the loss of the first conductive ion in the first metal silicide layer 301 is reduced, to improve semiconductor
The performance of device.
It should be noted that in the present embodiment, during carrying out annealing process, part in the first coating 261 the
One blocking ion releasing simultaneously diffuses in the surfacing in the first doped region 241, and the first blocking ion will not be distributed in entirely
In first doped region 241, first stops the influence of the electric conductivity of the first doped region of ion pair 241 smaller.
In the present embodiment, annealing process is carried out, the material of metal layer 290 and the second coating 262 is also made to react and be formed
The second metal silicide layer 302 with the second ion group.
In the present embodiment, annealing process is carried out, 262 material of the second coating of 290 bottom of metal layer 290 and metal layer is made
It reacts completely and forms second metal silicide layer 302 with the second ion group, the second metal silicide layer 302 is located at second
242 surface of doped region.During carrying out annealing process, the part second in the second coating 262 stops ion releasing and expands
It is dissipated in the second doped region 242.Second in second doped region 242 stops the in the second metal silicide layer of ion barrier 302
Two conductive ions diffuse in the second doped region 242.
In other embodiments, annealing process is carried out, metal layer and the second cover surface material is made to react and form tool
There is the second metal silicide layer of the second ion group, and makes part the of the second metal silicide layer bottom not with metal layer reaction
Two coatings form the second middle layer for being located at the second doped region surface, and the first metal silicide layer is located at the second middle layer table
Face；During carrying out annealing process, the part second in the second coating stops ion releasing and diffuses to the second doped region
In.Second in second doped region stops the second conductive ion in the second metal silicide layer of ion barrier and the second middle layer
It diffuses in the second doped region.
It should be noted that during carrying out annealing process, the part second in the second coating hinders in the present embodiment
Gear ion releasing simultaneously diffuses in the surfacing in the second doped region, and the first blocking ion will not be distributed in entire second doping
Qu Zhong, second stops the influence of the electric conductivity of the second doped region of ion pair smaller.
It should be noted that in other embodiments, after forming first through hole, carrying out the first silication technique for metal；It carries out
After first silication technique for metal, the second through-hole is formed；After forming the second through-hole, the second silication technique for metal is carried out.
In the present embodiment, barrier layer 291 is formed before carrying out annealing process, during carrying out annealing process, resistance
291 guard metal layer 290 of barrier avoids metal layer 290 from aoxidizing.In other embodiments, barrier layer 291 is carrying out annealing process
It is formed later.In other embodiments, barrier layer is not formed.
With reference to Fig. 9, after carrying out the first silication technique for metal and the second silication technique for metal, in first through hole 271 (with reference to figure
8) and in the second through-hole 272 (referring to Fig. 8) and on dielectric layer 270 plug material layer 310 is formed.
The material of the plug material layer 310 is metal, such as tungsten.
In the present embodiment, plug material layer 310 is located at 291 surface of barrier layer.
The technique for forming plug material layer 310 is depositing operation, such as chemical vapor deposition process.
In the present embodiment, also in the side wall of third through-hole 273 (referring to Fig. 8) and bottom and the (reference of fourth hole 274
Side wall and bottom Fig. 8) forms plug material layer 310.
With reference to Figure 10, plug material layer 310, barrier layer 291 and metal layer 290 are planarized until exposing dielectric layer 270
Top surface, form the first plug 311 in first through hole 271, form the second plug 312 in the second through-hole 272,
Third plug 313 is formed in three through-holes 273, and the 4th plug 314 is formed in fourth hole 274.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor devices characterized by comprising
Substrate is provided, substrate includes the firstth area；
The first doped region is formed in the firstth area of substrate；
Doped with the first ion group, the first ion group packet in the first coating of the first doped region surface formation, the first coating
It includes the first conductive ion and first and stops ion；
Using the first silication technique for metal make the first coating formed have the first ion group the first metal silicide layer, first
Ion is stopped to be less than the solid solubility in the first coating in the solid solubility in the first metal silicide layer.
2. the forming method of semiconductor devices according to claim 1, which is characterized in that first silication technique for metal
It include: to form metal layer in first cover surface；Annealing process is carried out, keeps the material of metal layer and the first coating anti-
It answers and forms first metal silicide layer.
3. the forming method of semiconductor devices according to claim 2, which is characterized in that carry out annealing process, make metal
Layer and the first cover surface material react and form first metal silicide layer, and make the first metal silicide layer bottom
The first middle layer for being located at the first doped region surface is not formed with the first coating of part of metal layer reaction；First metal silication
Nitride layer is located at the first interlayer surfaces；During carrying out annealing process, the part first in the first coating stops ion analysis
Out and diffuse in the first doped region；First in first doped region stops in the first metal silicide layer of ion barrier and first
The first conductive ion in interbed diffuses in the first doped region.
4. the forming method of semiconductor devices according to claim 2, which is characterized in that carry out annealing process, make metal
Layer and the first covering layer material of metal layer bottom react completely and form first metal silicide layer, the first metal silication
Nitride layer is located at the first doped region surface；During carrying out annealing process, the part first in the first coating stops ion analysis
Out and diffuse in the first doped region；First leads in first blocking the first metal silicide layer of ion barrier in first doped region
Electron ion diffuses in the first doped region.
5. the forming method of semiconductor devices according to claim 1, which is characterized in that carrying out first metallic silicon
Before chemical industry skill, the concentration of the first conductive ion in first coating is 1E18atom/cm3~5E21atom/cm3, institute
The concentration for stating the first blocking ion in the first coating is 1E17atom/cm3~1E21atom/cm3。
6. the forming method of semiconductor devices according to claim 1, which is characterized in that the material of first coating
For the silicon or germanium silicon doped with the first ion group.
7. the forming method of semiconductor devices according to claim 1, which is characterized in that described first stops ion to be N
The combination of ion, C ion or both.
8. the forming method of semiconductor devices according to claim 7, which is characterized in that when firstth area is used to form
When P-type transistor, described first stops ion to be N ion；When firstth area is used to form N-type transistor, described first
Blocking ion is C ion.
9. the forming method of semiconductor devices according to claim 1, which is characterized in that when firstth area is used to form
When P-type transistor, the conduction type of first conductive ion is p-type；When firstth area is used to form N-type transistor,
The conduction type of first conductive ion is N-type.
10. the forming method of semiconductor devices according to claim 1, which is characterized in that form first coating
Method include: in first the first coating of doped region surface epitaxial growth；During extension one coating of growth regulation
The first ion group is adulterated in first coating in situ.
11. the forming method of semiconductor devices according to claim 1, which is characterized in that the first ion group is also wrapped
The first lattice alienation ion is included, solid solubility of the first lattice alienation ion in the first metal silicide layer is less than in the first covering
Solid solubility in layer.
12. the forming method of semiconductor devices according to claim 11, which is characterized in that the first lattice alienation from
Son is the combination of Sb ion, Ga ion or both.
13. the forming method of semiconductor devices according to claim 12, which is characterized in that when firstth area is used for shape
When at P-type transistor, the first lattice alienation ion is Sb ion；When firstth area is used to form N-type transistor, first is brilliant
Lattice alienation ion is Ga ion.
14. the forming method of semiconductor devices according to claim 11, which is characterized in that carrying out first metal
Before silicification technics, the concentration of the first lattice alienation ion in the first coating is 1E18atom/cm3~1E21atom/cm3。
15. the forming method of semiconductor devices according to claim 1, which is characterized in that further include: it is mixed in formation first
Before miscellaneous area, first grid structure is formed in firstth area of substrate；After forming the first doped region, the first doped region is located at the
In the substrate of one gate structure two sides.
16. the forming method of semiconductor devices according to claim 1, which is characterized in that the substrate further includes second
Area；The forming method of the semiconductor devices further include: after forming the first coating, and carrying out the first metallic silicon chemical industry
Before skill, the second doped region is formed in the secondth area of substrate；The second coating, the second coating are formed on the second doped region surface
In doped with the second ion group, the second ion group includes that the second conductive ion and second stop ion；Using the second metal silication
Technique makes the second coating form second metal silicide layer with the second ion group, and second stops ion in the second metallic silicon
Solid solubility in compound layer is less than the solid solubility in the second coating.
17. the forming method of semiconductor devices according to claim 16, which is characterized in that the second ion group is also wrapped
Include the second lattice alienation ion；Solid solubility of the second lattice alienation ion in the second metal silicide layer is less than in the second covering
Solid solubility in layer.
18. the forming method of semiconductor devices according to claim 16, which is characterized in that further include: forming first
After coating and the second coating, and before carrying out the first silication technique for metal and the second silication technique for metal, medium is formed
Layer, the dielectric layer cover the first coating, the second coating and substrate；The through dielectric layer is formed in the dielectric layer
One through-hole, first through hole expose the first cover surface；After forming first through hole, the first silication technique for metal is carried out；Institute
The second through-hole for being formed in dielectric layer and running through dielectric layer is stated, the second through-hole exposes the second cover surface；Form the second through-hole
Afterwards, the second silication technique for metal is carried out.
19. the forming method of semiconductor devices according to claim 1, which is characterized in that the substrate includes semiconductor
Substrate and the fin in semiconductor substrate, the fin include the first fin in the firstth area of semiconductor substrate；When
When firstth area is used to form P-type transistor, the material of first fin includes monocrystalline Ge；When the firstth area is used to form N-type crystalline substance
When body pipe, the material of first fin includes InGaAs.
20. a kind of according to claim 1 to the semiconductor devices that 19 any one methods are formed.
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| CN105990137A (en) * | 2015-01-30 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof, and semiconductor structure and forming method thereof |
| CN106409770A (en) * | 2015-07-31 | 2017-02-15 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
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| US20030186532A1 (en) * | 2002-03-26 | 2003-10-02 | Tung-Po Chen | Method of forming a titanium-containing glue layer |
| CN105336660B (en) * | 2014-07-30 | 2018-07-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
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| US20060121660A1 (en) * | 2004-12-08 | 2006-06-08 | Samsung Electronics Co., Ltd. | Semiconductor device having carbon-containing metal silicide layer and method of fabricating the same |
| CN101346799A (en) * | 2006-01-18 | 2009-01-14 | 东京应化工业株式会社 | Film-forming composition |
| US20080199999A1 (en) * | 2007-02-21 | 2008-08-21 | Texas Instruments Incorporated | Formation of a Selective Carbon-Doped Epitaxial Cap Layer on Selective Epitaxial SiGe |
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