CN109274941A - Multichannel video decoding Face datection recognition methods based on FPGA - Google Patents
Multichannel video decoding Face datection recognition methods based on FPGA Download PDFInfo
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- CN109274941A CN109274941A CN201811240804.3A CN201811240804A CN109274941A CN 109274941 A CN109274941 A CN 109274941A CN 201811240804 A CN201811240804 A CN 201811240804A CN 109274941 A CN109274941 A CN 109274941A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
- H04N7/181—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast for receiving images from a plurality of remote sources
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V20/00—Scenes; Scene-specific elements
- G06V20/40—Scenes; Scene-specific elements in video content
- G06V20/41—Higher-level, semantic clustering, classification or understanding of video scenes, e.g. detection, labelling or Markovian modelling of sport events or news items
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/16—Human faces, e.g. facial parts, sketches or expressions
- G06V40/161—Detection; Localisation; Normalisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/16—Human faces, e.g. facial parts, sketches or expressions
- G06V40/172—Classification, e.g. identification
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Oral & Maxillofacial Surgery (AREA)
- Human Computer Interaction (AREA)
- Health & Medical Sciences (AREA)
- General Health & Medical Sciences (AREA)
- Signal Processing (AREA)
- Computational Linguistics (AREA)
- Software Systems (AREA)
- Studio Devices (AREA)
- Image Processing (AREA)
Abstract
The present invention relates to Face datection identification technology fields, the in particular multichannel video decoding Face datection recognition methods based on FPGA, it include FPGA mainboard, it is characterized in that, FPGA mainboard accesses multichannel video decoding chip and all the way clock module, multichannel video decoding chip accesses corresponding multi-path high-definition camera by communication interface, the output end of FPGA mainboard accesses CCIR656 video interface, CCIR656 video interface accesses video solution code converter, video solution code converter accesses FPGA subplate, FPGA subplate accesses memory module, video display module, FPGA subplate creates face database in memory module, FPGA subplate triggering property is connected with timer, timer is to resource manager registration information, and synchronized links have background data base system.The present invention, as main control chip, is completed to show and switch while multi-channel video picture, realizes that the cascade configuration of two FPGA, plurality of positions carry out real-time face detection using two panels FPGA.
Description
Technical field
The present invention relates to Face datection identification technology fields, more particularly to the multichannel video decoding Face datection based on FPGA
Recognition methods.
Background technique
Recognition of face is a kind of biological identification technology for carrying out identification based on facial feature information of people.With camera shooting
Machine or camera acquire image or video flowing containing face, and automatic detection and tracking face in the picture, and then to detection
The face that arrives carries out a series of the relevant technologies of face recognition, usually also referred to as Identification of Images, face recognition.
In the prior art, for industry spot because environment is complicated, requirement of real-time is high, it is often necessary to one or more weights
It wants position to carry out Face datection simultaneously, and wherein width picture full screen display can be switched when needed.
Summary of the invention
The purpose of the present invention is to solve disadvantages existing in the prior art, and the multi-channel video based on FPGA proposed
Decode Face datection recognition methods.
To achieve the goals above, present invention employs following technical solutions:
Multichannel video decoding Face datection recognition methods based on FPGA, includes FPGA mainboard, which is characterized in that described
FPGA mainboard accesses multichannel video decoding chip and clock module, the multichannel video decoding chip are connect by communication interface all the way
Enter corresponding multi-path high-definition camera, the output end of the FPGA mainboard accesses CCIR656 video interface, the CCIR656
Video interface accesses video solution code converter, and the video solution code converter accesses FPGA subplate, and the FPGA subplate access is deposited
Module, video display module are stored up, the FPGA subplate creates face database, the FPGA subplate triggering property connection in memory module
There is timer, the timer is to resource manager registration information, and synchronized links have background data base system.
Preferably, the FPGA subplate extracts image in memory module, and carries out unitized processing, searches by face database
Rope compares and analyzes, and triggers timer to resource manager registration information.
Preferably, the CCIR656 video interface has 8 data line transmitting data in parallel, transmits the YCbCr of 4:2:2
Outside video flowing, and there is control signal used in row, field synchronization.
Preferably, the FPGA mainboard accesses UART communication module, sends corresponding control instruction by the serial ports of PC machine,
FPGA mainboard switches respective channel picture after receiving.
Preferably, the memory module is under the action of corresponding control sequential, successively by display caching, in memory module
Data are sequential read out, and are output to video and are shown on mould.
Preferably, the background data base system carries out verification result processing.
Preferably, pass through I2C bus under the control of the FPGA mainboard and complete configuration and initial.
Preferably, the video solution code converter carries out the YCrCb 4:2:2 formatted data that video decoding chip exports
Conversion.
Compared with prior art, the invention proposes the multichannel video decoding Face datection recognition methods based on FPGA, tools
Have it is following the utility model has the advantages that
The present invention has the detection of real-time video human face, can either meet the particular surroundings of industry spot application, has body
Small, low in energy consumption, the customized feature of product, but multiple spot can be carried out acquisition and Display on the same screen simultaneously and to it is therein all the way into
Row switching.
The present invention is completed to show and switch while multi-channel video picture, be realized using two panels FPGA as main control chip
The cascade configuration of two FPGA, plurality of positions carry out real-time face detection, can be the more complicated image procossing of function, compression, biography
Defeated system provides the acquisition of front-end image data.
In the present invention, it is not directed to part in the device and is the same as those in the prior art or can be realized by using the prior art,
The present invention can carry out acquisition simultaneously to multiple spot and Display on the same screen and switch over all the way to therein.
Detailed description of the invention
Fig. 1 is that the whole structure of the multichannel video decoding Face datection recognition methods proposed by the present invention based on FPGA is shown
It is intended to；
Fig. 2 is that the structure of the part of the multichannel video decoding Face datection recognition methods proposed by the present invention based on FPGA is shown
It is intended to.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that, term " on ", "lower", "front", "rear", "left", "right", "top",
The orientation or positional relationship of the instructions such as "bottom", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, merely to just
In description the present invention and simplify description, rather than the device or element of indication or suggestion meaning must have a particular orientation, with
Specific orientation construction and operation, therefore be not considered as limiting the invention.
Fig. 1-2 is please referred to, the multichannel video decoding Face datection recognition methods based on FPGA, includes FPGA mainboard,
It is characterized in that, the FPGA mainboard access multichannel video decoding chip and all the way clock module, the multichannel video decoding chip
Corresponding multi-path high-definition camera is accessed by communication interface, the output end access CCIR656 video of the FPGA mainboard connects
Mouthful, the CCIR656 video interface accesses video solution code converter, and the video solution code converter accesses FPGA subplate, described
FPGA subplate accesses memory module, video display module, and the FPGA subplate creates face database, the FPGA in memory module
Subplate triggering property is connected with timer, and the timer is to resource manager registration information, and synchronized links have background data base
System.
The FPGA subplate extracts image in memory module, and carries out unitized processing, by face library searching, carries out
Comparative analysis triggers timer to resource manager registration information.
The CCIR656 video interface has 8 data line transmitting data in parallel, transmits the YCbCr video flowing of 4:2:2
Outside, and there is control signal used in row, field synchronization.
The FPGA mainboard accesses UART communication module, sends corresponding control instruction, FPGA master by the serial ports of PC machine
Plate switches respective channel picture after receiving.
The memory module is under the action of corresponding control sequential, successively by display caching, data in memory module according to
Secondary reading is output to video and shows on mould.
The background data base system carries out verification result processing.
Pass through I2C bus under the control of the FPGA mainboard and completes configuration and initial.
The video solution code converter converts the YCrCb 4:2:2 formatted data that video decoding chip exports.
In the present invention, in use, multi-path high-definition camera acquires face face, decoded by multichannel video decoding chip,
Be transferred to FPGA mainboard with data mode, pass through I2C bus under the control of FPGA mainboard and complete configuration and initial, output 8 with
The YCbCr video of CCIR656 compatible 4:2:2 format, video converter carry out format to the YCbCr video of 4:2:2 format and turn
It changes, is input to FPGA subplate, FPGA subplate extracts image in memory module, and carries out unitized processing, searches by face database
Rope compares and analyzes, and triggers timer to resource manager registration information, effect of the memory module in corresponding control sequential
Under, successively by display caching, the data in memory module are sequential read out, and it is output to video and shows on mould, background data base system
Carry out verification result processing.
It although an embodiment of the present invention has been shown and described, for the ordinary skill in the art, can be with
A variety of variations, modification, replacement can be carried out to these embodiments without departing from the principles and spirit of the present invention by understanding
And modification, the scope of the present invention is defined by the appended.
Claims (8)
1. the multichannel video decoding Face datection recognition methods based on FPGA, includes FPGA mainboard, which is characterized in that described
FPGA mainboard accesses multichannel video decoding chip and clock module, the multichannel video decoding chip are connect by communication interface all the way
Enter corresponding multi-path high-definition camera, the output end of the FPGA mainboard accesses CCIR656 video interface, the CCIR656
Video interface accesses video solution code converter, and the video solution code converter accesses FPGA subplate, and the FPGA subplate access is deposited
Module, video display module are stored up, the FPGA subplate creates face database, the FPGA subplate triggering property connection in memory module
There is timer, the timer is to resource manager registration information, and synchronized links have background data base system.
2. the multichannel video decoding Face datection recognition methods according to claim 1 based on FPGA, which is characterized in that institute
It states FPGA subplate and extracts image in memory module, and carry out unitized processing and compared and analyzed by face library searching,
Timer is triggered to resource manager registration information.
3. the multichannel video decoding Face datection recognition methods according to claim 1 based on FPGA, which is characterized in that institute
CCIR656 video interface is stated with 8 data line transmitting data in parallel, is transmitted outside the YCbCr video flowing of 4:2:2, and has row, field
Synchronize control signal used.
4. the multichannel video decoding Face datection recognition methods according to claim 1 based on FPGA, which is characterized in that institute
FPGA mainboard access UART communication module is stated, corresponding control instruction is sent by the serial ports of PC machine, FPGA mainboard is cut after receiving
Change respective channel picture.
5. the multichannel video decoding Face datection recognition methods according to claim 1 based on FPGA, which is characterized in that institute
Memory module is stated under the action of corresponding control sequential, successively by display caching, the data in memory module are sequential read out, and are exported
It is shown on mould to video.
6. the multichannel video decoding Face datection recognition methods according to claim 1 based on FPGA, which is characterized in that institute
It states background data base system and carries out verification result processing.
7. the multichannel video decoding Face datection recognition methods according to claim 1 based on FPGA, which is characterized in that institute
It states and passes through I2C bus under the control of FPGA mainboard and complete configuration and initial.
8. the multichannel video decoding Face datection recognition methods according to claim 1 based on FPGA, which is characterized in that institute
Video solution code converter is stated to convert the YCrCb 4:2:2 formatted data that video decoding chip exports.
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| CN201811240804.3A CN109274941B (en) | 2018-10-23 | 2018-10-23 | Multi-channel video decoding face detection and identification method based on FPGA |
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| CN201811240804.3A CN109274941B (en) | 2018-10-23 | 2018-10-23 | Multi-channel video decoding face detection and identification method based on FPGA |
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| CN109274941A true CN109274941A (en) | 2019-01-25 |
| CN109274941B CN109274941B (en) | 2020-12-18 |
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| CN111507245A (en) * | 2020-04-15 | 2020-08-07 | 海信集团有限公司 | Embedded system and method for face detection |
| CN112788307A (en) * | 2021-02-03 | 2021-05-11 | 安徽创力建设工程有限公司 | Data receiving device for video monitoring |
| GB2622318A (en) * | 2019-06-05 | 2024-03-13 | V Nova Int Ltd | System and method for performing object analysis |
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| CN109274941B (en) | 2020-12-18 |
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