CN109273043A - Nand memory and its bad block labeling method - Google Patents
Nand memory and its bad block labeling method Download PDFInfo
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- CN109273043A CN109273043A CN201811087379.9A CN201811087379A CN109273043A CN 109273043 A CN109273043 A CN 109273043A CN 201811087379 A CN201811087379 A CN 201811087379A CN 109273043 A CN109273043 A CN 109273043A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5606—Error catch memory
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Abstract
The application discloses a kind of nand memory and its bad block labeling method, memory block in the nand memory is divided into the identical sub- memory block of multiple storage sizes, and every sub- memory block is provided with sub- MBA memory block address, therefore, when several wordline existing defects in nand memory, when detecting defect wordline, sub- memory block corresponding to defect wordline can be labeled as bad block, rather than the corresponding memory block monolith of defect wordline is labeled as bad block, to extend the available space of nand memory, take full advantage of the memory space for not occurring the corresponding sub- memory block of defect wordline in memory block, the problem of improving waste of storage space.The bad block labeling method is based on nand memory recited above, and after detecting fault point, marking sub- memory block is bad block, and non-marked memory block is bad block, so that memory space increases, and then expands workable memory space.
Description
Technical field
The present invention relates to memory technology field more particularly to a kind of nand memory and its bad block labeling methods.
Background technique
Due to the limitation of nand memory realization principle, be possible to generate in process of production bad block (bad Block or
Referred to as invalid block, invalid Block).In nand memory in use, MBA memory block address (Block address) is mark
Remember the smallest addressable unit of bad block.Any memory block is marked as bad block, then this memory block (Block) would be unavailable for storing
Valid data.However, the problem of will cause waste of storage space in this way, and in nand memory memory block deposit
The problem of storage space is increasing, waste of storage space will be more serious.
Summary of the invention
In view of this, the present invention provides a kind of nand memory and its bad block labeling method, to solve to deposit in the prior art
The memory space for storing up block is increasing, when entire memory block is marked as bad block, causes the problem that waste of storage space is serious.
To achieve the above object, the invention provides the following technical scheme:
A kind of nand memory, the memory include at least one memory block, and each memory block includes multiple words
Line group and at least one dummy wordlines, dummy；
The memory further include: multiple sub- memory blocks；
Wherein, each memory block is divided into the identical sub- memory block of multiple storage sizes, and each son is deposited
Storage block is provided with sub- MBA memory block address.
Preferably, multiple sub- memory blocks in each memory block are to divide to obtain with the position of the word line group
's.
Preferably, if in the memory including at least one invalid sub- memory block, the institute in the sub- memory block
There is wordline to be set as dummy wordlines, dummy.
The present invention also provides a kind of bad block labeling method of nand memory, the nand memory is any of the above one
The nand memory, the bad block labeling method include:
Wordline in the nand memory is detected；
In the case of detecting that a wordline is faulty word line, according to the corresponding relationship of the wordline and sub- memory block, determine
The corresponding sub- memory block of the wordline；
Sub- memory block where marking the wordline is invalid sub- memory block.
Preferably, the wordline in the nand memory detects, and specifically includes:
According to the direction for being directed toward top selection grid by bottom selection grid in the nand memory, the NAND is stored
Wordline in device is successively detected.
Preferably, further includes: record the address of sub- memory block invalid in the nand memory, and generate sub- memory block
Defect block addresses table.
Preferably, the address for recording sub- memory block invalid in the nand memory, and it is bad to generate sub- memory block
Block address table, specifically includes:
The address of sub- memory block where the wordline of label is saved in preset sub- memory block defect block addresses table；
The sub- memory block defect block addresses table is cured in the storage array of the nand memory.
It can be seen via above technical scheme that the memory block in nand memory provided by the invention is divided into multiple deposit
The identical sub- memory block of space size is stored up, and every sub- memory block is provided with sub- MBA memory block address, therefore, when in nand memory
Several wordline existing defects when, that is, when detecting defect wordline, sub- memory block corresponding to defect wordline can be labeled as
Bad block, rather than the corresponding memory block monolith of defect wordline is labeled as bad block, so as to be deposited corresponding to defect wordline
Other sub- memory blocks in storage block are used to storing data and take full advantage of and deposit to extend the available space of nand memory
Not the problem of not occurring the memory space of the corresponding sub- memory block of defect wordline in storage block, improve waste of storage space.
The present invention also provides a kind of bad block labeling methods, are based on nand memory recited above, are detecting fault point
Afterwards, marking sub- memory block is bad block, and non-marked memory block is bad block, so that memory space increases, and then expanding can
The memory space used.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the schematic diagram of the section structure of a memory block；
Fig. 2 is a kind of nand memory the schematic diagram of the section structure provided by the invention；
Fig. 3 is the bad block labeling method flow diagram of nand memory；
Fig. 4 is a kind of nand memory access method flow diagram provided in an embodiment of the present invention；
Fig. 5 is a kind of featured configuration schematic diagram provided in an embodiment of the present invention；
Fig. 6 is a kind of nand memory access mechanism structural schematic diagram provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Nand memory is made of multiple memory block Block, and each memory block Block is made of multiple pages of Page.Block
It is the minimum unit of erasing operation, Page is the minimum unit of programming.Physically, each memory block Block includes more
Wordline WL.
Referring to Figure 1, Fig. 1 is the schematic diagram of the section structure that word number of lines is 128 corresponding memory blocks；The memory block
Block successively includes bottom selection grid (Bottom selective gate) BSG, a plurality of wordline WL, top selection from bottom to top
Grid (Top selective gate) TSG and be generally arranged at a plurality of wordline WL fringe region, close to top selection grid TSG and
The a plurality of dummy wordlines, dummy Dmy of bottom selection grid BSG；The memory block Block further includes multiple channel hole vertical with wordline WL
(channel hole) CH and array common source (Array common source) ACS, in the embodiment of the present invention memory its
He is not described in detail structure.
Due to manufacture craft, a plurality of dummy wordlines, dummy is additionally provided between a plurality of wordline WL in memory block shown in FIG. 1
Dmy can also be not provided with dummy wordlines, dummy Dmy between a plurality of wordline WL in other embodiments of the invention.
Since memory block Block shown in FIG. 1 includes 128 wordline, if wherein one or more wordline WL existing defects,
When being detected before memory factory, entire memory block Block can be labeled as to bad block, and generated by the address of bad block
Block bad block table, storage in memory, and work as the address that bad block in Block bad block table is read in system use process, thus
It does not store data in bad block.
However, due to including a plurality of wordline in a memory block Block, it can not be normal in addition to several wordline of existing defects
Use, other wordline WL is or normal, the storage unit in the corresponding Page of wordline WL can with normal storage data, because
This, causes the larger waste of memory space in this way, and space loss is larger, also reduces the service life of nand memory.
For example, it is assumed that when the Page2 in Block X in nand memory wrong bit quantity occurs more than threshold value, then
Entire Block is identified as bad block, and all Page are directly abandoned as bad block space on the Block X, and system makes
The Block X is directly skipped in.In addition to Page2 can not be other than normal use on the actually Block X, other Page are just
Normal, it all can be with normal use, this just brings very big space waste.
Moreover, as shown in table 1, with the development of nand memory technology, the wordline number of plies is more and more inside different product,
The memory space of corresponding single memory block is increasing.
The memory space of single block inside 1 different product of table
Wherein, in table 1, existing product A, existing product B and existing product C represent some memory, only illustrate in table 1
Illustrate the wordline number of plies of existing memory and the storage size relationship of memory block, is not limited to some memory product.
Since the memory space of single memory block is increasing, then when there is bad block, caused by waste, get over
Come more serious.
Based on this, a kind of nand memory provided herein, as shown in Fig. 2, Fig. 2 is a kind of NAND provided by the invention
Memory the schematic diagram of the section structure；Memory includes at least one memory block, and each memory block includes multiple word line groups (10
With 20) and at least one dummy wordlines, dummy Dmy；The memory further include: multiple sub- memory block (Sub-Block-0 and Sub-
Block-1), wherein each memory block is divided into the identical sub- memory block of multiple storage sizes, and each son is deposited
Storage block is provided with sub- MBA memory block address.
It is illustrated so that memory block includes 128 wordline as an example, as shown in Fig. 2, each memory block in the present embodiment
In multiple sub- memory blocks be to be divided with the position of the word line group.Memory can generate more in the production process
The continuous wordline of item, therefore according to the location of a plurality of wordline, a plurality of wordline in a memory block is divided into a son and deposits
Block is stored up, while one corresponding sub- MBA memory block address is set to the sub- memory block.
When marking bad block, then using the sub- MBA memory block address as marking unit, with bad block of marking.And in physics knot
On structure, if having been detected in memory and at least one invalid sub- memory block being marked, also as bad block, then by corresponding son
All wordline in memory block are disposed as dummy wordlines, dummy, and as shown in Figure 2, sub- memory block Sub-Block-1 detects a certain word
All wordline in sub- memory block Sub-Block-1 are then disposed as dummy wordlines, dummy by line WL existing defects, functionally with empty word
Line is identical, to be no longer serve as storing data.
It should be noted that due to the definition for increasing sub- memory block, and need to distribute an address for each memory block,
And the memory space of whole memory is constant, provides the address resolution table of sub- memory block therefore, it is necessary to corresponding.
Refer to table 2 and table 3, wherein table 2 is the flash memory address resolution table under default mode, and the default mode is will
Memory block is divided into the mode before sub- memory block；Table 3 is the flash memory address resolution table under sub- memory block mode.The present invention is implemented
With the memory space of memory it is 512Gb in example, there are 1950 memory blocks, includes carrying out for page 2304 in each memory block
Explanation.
Since a memory block is divided into two sub- memory blocks, then the number of page included in every sub- memory block will be
Half originally, therefore, the address of sub- memory block need more increases by one to be indicated, and the page in every sub- memory block
Address reduce one and be indicated, and the global storage space invariance of memory, digit used are constant.
In two address resolution tables, every a line refers to that an address bit, CA are Byte (byte) address bits, and PA is Page (page)
Address bit, BA are Block (memory block) address bit.
Wherein, in table 2, CA0-CA14 indicates memory a total of 215A byte；PA0-PA11 indicates each in memory
The address for the page for including in memory block needs 12 to be characterized namely the quantity of the page in each memory block is greater than 2048；
BA0-BA10, indicate memory in memory block address need 11 characterized namely memory in memory block quantity it is big
In 1024.
In table 3, since a memory block (Block) is divided into two sub- memory blocks (Sub-Block), then sub- memory block
Quantity become original double, the address of sub- memory block then needs 12 to be characterized, and in every sub- memory block page
Number relative to halving originally, therefore it may only be necessary to which 11 are characterized；Therefore, page address position reduces 1, and block address bits increase
1。
From table 2 to table 3 as can be seen that reducing one from default mode page address position (PA), by original PA0-PA11, become
For PA0-PA10；And corresponding block address bits (BA) increase by one, become BA0-BA11 from original BA0-BA10.And entirely
In the resolution table of location, since the memory space of memory does not change, byte address position (CA) quantity is constant.
Flash memory address resolution table under 2 default mode of table
Flash memory address resolution table under the sub- memory block mode of table 3
After using the flash memory address resolution table under sub- memory block mode that address is arranged one by one for sub- memory block, in bad block mark
It clocks, is marked using sub- MBA memory block address, thus using memory block sub- where other normal character lines as normal storage space
Use, expand memory space, it is increasing to improve memory block, caused by waste of storage space the problem of.
It is identical that the memory block in nand memory provided in the embodiment of the present invention is divided into multiple storage sizes
Sub- memory block, and every sub- memory block is provided with sub- MBA memory block address, therefore, when several wordline in nand memory exist
When defect, that is, when detecting defect wordline, sub- memory block corresponding to defect wordline can be labeled as bad block, rather than will lacked
It falls into the corresponding memory block monolith of wordline and is labeled as bad block, so as to deposit other sons in memory block corresponding to defect wordline
Storage block is used to storing data and takes full advantage of to extend the available space of nand memory and do not occur defect in memory block
The memory space of the corresponding sub- memory block of wordline, the problem of improving waste of storage space.
Based on nand memory described in above example, the embodiment of the present invention also provides a kind of bad block labeling method,
As shown in figure 3, Fig. 3 is the bad block labeling method flow diagram of nand memory；The bad block labeling method includes:
S101: the wordline in the nand memory is detected；
S102: in the case of detecting that a wordline is faulty word line, according to the corresponding relationship of the wordline and sub- memory block,
Determine the corresponding sub- memory block of the wordline；
S103: the sub- memory block where marking the wordline is invalid sub- memory block.
Memory block is divided into multiple sub- memory blocks according to word line group by the memory provided in the present embodiment, is being detected
Out before bad block, all normal character lines are regarded as can be with the wordline of normal storage data, by in the nand memory
Wordline successively apply voltage, circuit detection is carried out, when detecting a certain wordline is faulty word line, according to where the wordline
Word line group determine the sub- memory block belonging to it, at this point it is possible to which the sub- memory block where the wordline is labeled as invalid son
Memory block namely bad block.
It should be noted that during detecting wordline, can according in the nand memory by bottom selection grid
BSG is directed toward the direction of top selection grid TSG, successively detects to all wordline in the nand memory.
It is corresponding that the wordline in sub- memory block is carried out accordingly at genuine end after a certain sub- memory block is marked as bad block
Operation, by its function division be dummy wordlines, dummy, without be re-used as normal wordline carry out using.
In addition, recording the address of sub- memory block invalid in the nand memory after marking all bad blocks, and generate
Sub- memory block defect block addresses table.The process for generating sub- memory block defect block addresses table is not limited in the present embodiment, optionally, comprising:
The address of sub- memory block where the wordline of label is saved in preset sub- memory block defect block addresses table；By the son
Memory block defect block addresses table is cured in the storage array of the nand memory.In case follow-up system is read out after powering on,
To be written and read.
It should be noted that due to the sub- memory block provided in the embodiment of the present invention be mainly used for bad block label and it is subsequent
Therefore reading and writing data in the other problems for carrying out other operations to memory or occurring for wordline, does not need sub- storage
When block function, it is also necessary to continue to use original storage block message.Therefore, it whether there is failure, mark in detection wordline in the present embodiment
While remembering sub- memory block, it can also include the steps that marking memory block.Be specifically as follows: when detect a wordline be faulty word
In the case of line, according to the corresponding relationship of the wordline and memory block, the corresponding memory block of the wordline is determined；Mark the wordline
The memory block at place is invalid memory block.
Identical when marking with memory block is the address for recording memory block invalid in the nand memory, and is generated
Memory block defect block addresses table.Specifically: the address of the memory block where the wordline of label is saved in preset memory block
In defect block addresses table；The memory block defect block addresses table is cured in the storage array of the nand memory.When some is deposited
Storage block is marked as invalid memory block, still detects to other wordline in the memory block, in order to complete the memory block
In all memory blocks label.
It should be noted that in genuine detection process, if it is detected that a certain wordline breaks down, it needs to be determined that wordline
The true cause of failure judges whether the reason influences to be located in same memory block rather than son where the faulty word line is deposited
The function of other sub- memory blocks of block is stored up, if influencing, sub- memory blocks all in same memory block are marked as block；If no
It influences, then only marks the sub- memory block where the faulty word line.
The embodiment of the present invention also provides a kind of nand memory access method, and the access method is applied to above example
Described in nand memory, and based on the sub- memory block defect block addresses table being pre-stored in the nand memory storage array.
Fig. 4 is a kind of nand memory access method flow diagram provided in an embodiment of the present invention；As shown in figure 4, in system electrification
Afterwards, the access method includes:
S201: promoter memory block function command is received；
It should be noted that the application is defined as default mode due to not using sub- memory block function under some scenes,
In the case where memory block not being divided into sub- memory block；Another kind is sub- memory block mode, in this mode, to sub- memory block
Carry out relevant operation.
Such mode setting can be designed in the chip design stage of memory, under default mode, bad block management
It is operated according to entire memory block, and under sub- memory block mode, user can be by sending the commands to enter son storage
Block mode, bad block management is operated according to sub- memory block under sub- memory block mode.Namely user can basis
User oneself chooses whether promoter memory block function.
And genuine will prepare two parts of bad block management table (bad before memory chip factory inside memory chip
Block table) portion be default mode bad block table, another is the bad block table of sub- memory block mode.
It should be noted that the particular content of the instruction of the promoter memory block function is not limited in the present embodiment, it can
Selection of land can carry out the switching of mode by set feature command (setting feature instruction).set feature
Command (setting feature instruction) is as shown in table 4.It is as shown in table 4: functional address (Feature address): xxh；Reservation is turned over
It is translated into Reserved.
Table 4 is the instruction catalogue of promoter memory block function
As shown in Figure 5, Fig. 5 is a kind of featured configuration schematic diagram provided in the embodiment of the present invention；Wherein, each in figure
The representative meaning of parameter are as follows:
Cycle Type: input type；CMD: the instruction (command) of input；ADDR: the address (address) of input；
DIN: the data (data in) of input；DQ [7:0]: the pin of the chip with input/output function；R/B_n: monitoring chip
(busy/ready) chip pin of state, low level represent busy (busy) state；EFh: the instruction numerical value (present invention of input
In be not limited to this instruction, can also define other instruction numerical value, be only illustrated as example)；FA: Feature is represented
Address (characteristic address)；TADL:Address cycle to data loading time (it is defeated to be input to data from address
Time interval between entering)；TWB: the time interval dragged down from P4 data to R/B_n；tFEAT:busy time for set
Feature. (rush hour of special envoy's setting)；The specific value of P1/P2/P3/P4 representing characteristic setting.
Switch instances may include: to be switched to sub- memory block mode from default mode and be switched to sub- storage from default mode
Block mode.
Wherein, the operating process for being switched to sub- memory block mode from default mode is as follows:
Receive feature instruction --- set feature command EFh；
The address xxh of input characteristics instruction (specific value of xxh can be defined by genuine)；
After waiting the tADL time, the numerical value 01h of P1 is inputted；
P2 is inputted, P3, P4 numerical value is 00h；
Chip is switched to sub- memory block mode by default mode after operation.
From sub- memory block pattern switching to default mode, operating process is as follows:
Receive feature instruction --- set feature command EFh；
The address xxh of input characteristics (specific value of xxh can be defined by genuine)；
After waiting the tADL time, the numerical value 00h of P1 is inputted；
P2 is inputted, P3, P4 numerical value is 00h；
Chip is by sub- memory block pattern switching to default mode after operation.
Or by allowing storage core on piece electric once again, chip automatically switches to default mode.
It should be noted that the instruction of above-mentioned featured configuration is not limited to EFh, as long as the feature instruction can be realized
The switching of mode.
S202: the sub- memory block defect block addresses table of the sub- memory block is read；
The sub- memory block defect block addresses table that sub- memory block is read in the present embodiment can carry out after the power-up, Huo Zhe
It carries out after receiving promoter memory module function command, is not limited this in the present embodiment.
S203: the operation to the nand memory is received；
Operation described in the present embodiment includes read operation and write operation, can be specifically defined according to the actual situation.
If the operation is write operation, memory further includes the steps that receiving data to be written.
S204: the address of the nand memory neutron memory block for operating and being accessed and the sub- memory block is bad
Block address table is matched；
It is to guarantee to write behaviour that the address for the sub- memory block that operation is accessed, which match with son storage defect block addresses table,
Make or what read operation accessed is all effective sub- memory block.
S205: judge that whether the address of the sub- memory block for operating and being accessed records in the sub- memory block defect block addresses
In table；
S206: if so, skipping the sub- memory block for operating and being accessed；
S207: replacement is described to operate the sub- memory block that is accessed, and returns to S205 and carry out rejudging the operation and visited
Whether the sub- memory block asked is invalid sub- memory block；
S208: if it is not, then carrying out the operation to the sub- memory block accessed that operates.
The operation for write-in data or reads data from the sub- memory block.
It should be noted that in order to guarantee that data are written and read the reliability of data in data procedures do not have between each other
There is interference or interferes smaller, the sequence of nand memory neutron memory block described in operational access described in the present embodiment are as follows: according to
The direction that top selection grid is directed toward by bottom selection grid in the nand memory stores the son in the nand memory
Block carries out the access.That is, write operation and read operation are pushed up according to being directed toward in the nand memory by bottom selection grid
The direction of portion's selection grid operates the sub- memory block in the nand memory.
The nand memory access method provided in corresponding above example, the embodiment of the present invention also provide a kind of NAND and deposit
Reservoir access mechanism is applied to nand memory access method recited above, as shown in fig. 6, Fig. 6 mentions for the embodiment of the present invention
A kind of nand memory access mechanism structural schematic diagram supplied.The access mechanism includes:
Command reception module 601, for receiving promoter memory block function command；
Read module 602, for reading the sub- memory block defect block addresses table of the sub- memory block；
Receiving module 603 is operated, for receiving the operation to the nand memory；
Address matching module 604, the address of the nand memory neutron memory block for being accessed the operation
It is matched with the defect block addresses table of the sub- memory block；
Matching result judgment module 605, the address for judging the sub- memory block for operating and being accessed according to matching result are
It is no to be recorded in the sub- memory block defect block addresses table；
If so, skipping the sub- memory block for operating and being accessed, the sub- memory block for operating and being accessed is replaced, and return
It is back to the address matching module, by the sub- memory block defect block addresses of the address of the sub- memory block after replacement and the sub- memory block
Table is matched；
If it is not, then carrying out the operation to the sub- memory block accessed that operates.
It should be noted that if received instruction is the instruction of default mode or is not received by promoter storage after powering on
The instruction of block, then the access method process that memory executes are the normal read-write operation based on memory block defect block addresses table.
And in erase process, memory block is the smallest erasing unit, is not made an amendment in the embodiment of the present invention to this, when one
When the data in the sub- memory block in part in memory block need to be wiped free of, due to being carried out as unit of memory block in erase process
Erasing, then need not needing to wipe by other, and the data-moving stored in the sub- memory blocks of valid data goes out, then
Entire memory block can be wiped.
It should be noted that nand memory provided in an embodiment of the present invention is after factory, and in user's use process, user
System, as memory install mobile phone or computer, can also the defect block addresses table to memory be updated, including update deposit
Store up block defect block addresses table and sub- memory block defect block addresses table.Only, in memory in the application dispatch from the factory before be arranged memory block
Unlike defect block addresses table and sub- memory block defect block addresses table, system is to memory block defect block addresses table and sub- memory block bad block
The maintenance of location table is in system level, and the memory block defect block addresses table of system level and sub- memory block can be set in its own
Defect block addresses table.
It, can not the only individual son of label one it should be noted that system is during marking bad block and updating bad block
Memory block, therefore, in user's use process, it is bad block that system detection, which goes out a certain sub- memory block, with updating sub- memory block bad block
When the table of location, it is also desirable to mark all sub- memory blocks where the sub- memory block in memory block as block.For example, a storage
Device includes tri- memory blocks of A, B and C, and each memory block is divided into two sub- memory blocks namely memory includes son storage
Block A1, A2, B1, B2, C1, C2；Labeled A1 is bad block before dispatching from the factory, and generates sub- memory block defect block addresses table, i.e. son is deposited
Store up the address in block defect block addresses table including sub- memory block A1.In user's use process, system finds son storage by detection
Block B2 is also bad block, at this point, sub- memory block B1 and sub- memory block B2 is labeled as bad block simultaneously by system, and B1 and B2 is corresponding
Address is recorded in sub- memory block defect block addresses table, is updated to sub- memory block defect block addresses table, updated sub- memory block
It include the address of sub- memory block A1, sub- memory block B1 and sub- memory block B2 in defect block addresses table.Likewise, by memory block B's
Address is updated into memory block defect block addresses table.Updated memory block defect block addresses table includes the ground of memory block A and memory block B
Location.
Accordingly, in access method, in the address and sub- memory block that will operate accessed 3D NAND neutron memory block
Defect block addresses table and the address resolution table of sub- memory block matched, and matching result are as follows: the sub- memory block that operation is accessed
Address when being not recorded in defect block addresses table, further includes:
The sub- memory block that is accessed of operating is detected, judge sub- memory block that the operation is accessed whether be
Invalid sub- memory block；
If so, the sub- memory block defect block addresses table is recorded in the address of the sub- memory block for operating and being accessed
In, and the sub- storage is recorded in the address of other sub- memory blocks in the memory block where the sub- memory block that is accessed of operation
In block defect block addresses table, sub- memory block defect block addresses table is updated；
If it is not, then carrying out the operation to the sub- memory block accessed that operates.
While updating sub- memory block defect block addresses table, memory block defect block addresses table can also be updated.
Although it should be noted that memory block is divided into multiple sub- memory blocks by memory provided by the invention, originally
Apply for that the sub- memory block is not the sub- memory block in complete physical significance, is more like and is provided with separately between page and memory block
Therefore the range of definition of one wordline does not need to increase addressing circuit newly to sub- memory block.In sub- memory block address procedures,
The addressing circuit of addressing circuit or original memory block, there is no increase addressing circuit therefore ensure that memory-size not
In the case where change, free memory is expanded, improves the more serious problem of waste of storage space.
It should be noted that all the embodiments in this specification are described in a progressive manner, each embodiment weight
Point explanation is the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
It should also be noted that, herein, relational terms such as first and second and the like are used merely to one
Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation
There are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that article or equipment including a series of elements not only include those elements, but also
It including other elements that are not explicitly listed, or further include for this article or the intrinsic element of equipment.Do not having
In the case where more limitations, the element that is limited by sentence "including a ...", it is not excluded that in the article including above-mentioned element
Or there is also other identical elements in equipment.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (7)
1. a kind of nand memory, which is characterized in that the memory includes at least one memory block, each memory block packet
Include multiple word line groups and at least one dummy wordlines, dummy；
The memory further include: multiple sub- memory blocks；
Wherein, each memory block is divided into the identical sub- memory block of multiple storage sizes, each sub- memory block
It is provided with sub- MBA memory block address.
2. nand memory according to claim 1, which is characterized in that multiple sons in each memory block are deposited
Storing up block is divided with the position of the word line group.
3. nand memory according to claim 4, which is characterized in that if including that at least one is invalid in the memory
Sub- memory block, then all wordline in the sub- memory block are set as dummy wordlines, dummy.
4. a kind of bad block labeling method of nand memory, which is characterized in that the nand memory is that claim 1-3 is any
Nand memory described in one, the bad block labeling method include:
Wordline in the nand memory is detected；
In the case of detecting that a wordline is faulty word line, according to the corresponding relationship of the wordline and sub- memory block, described in determination
The corresponding sub- memory block of wordline；
Sub- memory block where marking the wordline is invalid sub- memory block.
5. the bad block labeling method of nand memory according to claim 4, which is characterized in that described to be deposited to the NAND
Wordline in reservoir is detected, and is specifically included:
According to the direction for being directed toward top selection grid by bottom selection grid in the nand memory, in the nand memory
Wordline successively detected.
6. the bad block labeling method of nand memory according to claim 4, which is characterized in that further include: described in record
The address of invalid sub- memory block in nand memory, and generate sub- memory block defect block addresses table.
7. the bad block labeling method of nand memory according to claim 6, which is characterized in that described to record the NAND
The address of invalid sub- memory block in memory, and sub- memory block defect block addresses table is generated, it specifically includes:
The address of sub- memory block where the wordline of label is saved in preset sub- memory block defect block addresses table；
The sub- memory block defect block addresses table is cured in the storage array of the nand memory.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111913128A (en) * | 2020-08-05 | 2020-11-10 | 广州东方电科自动化有限公司 | Fault detection system and method for connecting wire of charging gun |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101527162A (en) * | 2008-03-07 | 2009-09-09 | 深圳市朗科科技股份有限公司 | Card slot type flash memory hard disk |
| US20120254680A1 (en) * | 2011-03-28 | 2012-10-04 | Eun Chu Oh | Nonvolatile memory device and bad area managing method thereof |
| CN104461750A (en) * | 2013-09-25 | 2015-03-25 | 北京兆易创新科技股份有限公司 | Method and device for accessing NAND flash |
| CN105719703A (en) * | 2014-12-17 | 2016-06-29 | 爱思开海力士有限公司 | Memory System And Operating Method Thereof |
| US20180046574A1 (en) * | 2010-08-20 | 2018-02-15 | Samsung Electronics Co., Ltd. | Address scheduling methods for non-volatile memory devices with three-dimensional memory cell arrays |
| US20180088823A1 (en) * | 2016-09-29 | 2018-03-29 | Intel Corporation | Managing solid state drive defect redundancies at sub-block granularity |
-
2018
- 2018-09-18 CN CN201811087379.9A patent/CN109273043A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101527162A (en) * | 2008-03-07 | 2009-09-09 | 深圳市朗科科技股份有限公司 | Card slot type flash memory hard disk |
| US20180046574A1 (en) * | 2010-08-20 | 2018-02-15 | Samsung Electronics Co., Ltd. | Address scheduling methods for non-volatile memory devices with three-dimensional memory cell arrays |
| US20120254680A1 (en) * | 2011-03-28 | 2012-10-04 | Eun Chu Oh | Nonvolatile memory device and bad area managing method thereof |
| CN104461750A (en) * | 2013-09-25 | 2015-03-25 | 北京兆易创新科技股份有限公司 | Method and device for accessing NAND flash |
| CN105719703A (en) * | 2014-12-17 | 2016-06-29 | 爱思开海力士有限公司 | Memory System And Operating Method Thereof |
| US20180088823A1 (en) * | 2016-09-29 | 2018-03-29 | Intel Corporation | Managing solid state drive defect redundancies at sub-block granularity |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111913128A (en) * | 2020-08-05 | 2020-11-10 | 广州东方电科自动化有限公司 | Fault detection system and method for connecting wire of charging gun |
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