CN109270742B

CN109270742B - Array substrate and liquid crystal display panel

Info

Publication number: CN109270742B
Application number: CN201811344319.0A
Authority: CN
Inventors: 杨仁光
Original assignee: Chengdu CEC Panda Display Technology Co Ltd
Current assignee: Chengdu CEC Panda Display Technology Co Ltd
Priority date: 2018-11-13
Filing date: 2018-11-13
Publication date: 2021-07-06
Anticipated expiration: 2038-11-13
Also published as: CN109270742A

Abstract

The invention provides an array substrate and a liquid crystal display panel, which comprise an insulating layer and an indium tin oxide semiconductor layer arranged on the insulating layer, wherein the upper side of the indium tin oxide semiconductor layer is in contact with liquid crystal, the array substrate also comprises a plurality of sub-pixel units positioned below the insulating layer, the indium tin oxide semiconductor layer comprises a plurality of first areas with the same number as the sub-pixel units, the size and the size of the first areas are the same as those of the sub-pixel units, the first areas and the sub-pixel units are arranged in a one-to-one correspondence manner, a first groove is arranged in the middle of at least one first area, and the first groove is in a cross shape. The invention can reduce dark stripes in each sub-pixel and improve the light transmittance.

Description

Array substrate and liquid crystal display panel

Technical Field

The invention relates to the technical field of liquid crystal display, in particular to an array substrate and a liquid crystal display panel.

Background

Liquid Crystal Displays (LCDs) have many advantages such as thin body, power saving, and no radiation, and are widely used, such as Liquid Crystal televisions, mobile phones, personal digital assistants, digital cameras, computer screens, or notebook computer screens. As for the TFT-LCD liquid crystal panels currently on the mainstream market, there are three major categories, namely twisted nematic/super twisted nematic (TN/STN) type, in-plane switching (IPS) type and Vertical Alignment (VA) type. In the manufacturing process of the liquid crystal display panel, alignment of the guide film is an important process, and the alignment process is used for realizing the arrangement of liquid crystal molecules according to a specific direction and an angle. The conventional alignment process adopts a Rubbing (Rubbing) method, can align in only one horizontal direction, and is widely adopted by TN-type and IPS-type liquid crystal panels. However, in the VA-type liquid crystal panel, the viewing angle needs to be widened, and the sub-pixel is divided into a plurality of regions, and the alignment direction differs for each region, so that the rubbing method cannot be adopted. And UV induced multi-domain vertical alignment (UV)²A) Is a kind of optical alignment technology of VA type liquid crystal panel. As shown in fig. 1, UV²The a technique utilizes ultraviolet rays to be obliquely incident on the alignment film (PI)10 at a certain angle, so as to form the alignment microstructure 20 with a certain inclination angle on the surface of the alignment film 10, thereby enabling the first liquid crystal molecules 30 to have a pre-tilt angle on the surface of the alignment film 10. By UV²After alignment, the alignment microstructure 20 formed on the surface of the alignment film 10 is consistent with the inclination angle of the ultraviolet ray, and the alignment precision is higher. UV (ultraviolet) light²The A technology can be realized by an alignment filmSince the liquid crystal molecules are inclined in the design direction, the liquid crystal molecules are tilted in the same direction when an electric field is applied, and the response speed is increased to 2 times that of the original liquid crystal molecules to 4ms or less. Since the panel can be divided into a plurality of regions without using the projections and the slits, the aperture ratio is improved by 20% or more as compared with the conventional panel divided into a plurality of regions by the projections. The brightness of the backlight lamp is very low, the same brightness as the original brightness can be obtained, the power consumption is reduced, the number of backlight lamp light sources is reduced, the energy saving and the cost saving are facilitated, and the high-precision and 3D display and the like are easy to realize. In addition, light from the backlight was scattered in the projection and slit portions and leaked in the front, and thus blackened; and UV²The technology A does not leak light at the protrusion and slit part, so the static contrast ratio reaches 5000: 1, 1.6 times of the original. And the process of designing the protrusion and the slit can be omitted, and the production capacity is improved.

With the development of liquid crystal display technology, high-resolution liquid crystal panels become current hot spot products, but the aperture ratio of the high-resolution liquid crystal panels is low, so that the percentage (T%) of transmitted light in the incident light intensity and the light transmittance are low. In consideration of the viewing angle problem of the VA-type liquid crystal panel, the existing UV²The pixel structure a generally divides the red sub-pixel, the green sub-pixel, and the blue sub-pixel in each pixel unit into four alignment sub-regions with the same size, and the alignment directions between two adjacent alignment sub-regions in the same sub-pixel are perpendicular to each other.

However, using such UV²In the liquid crystal panel with the a-technology alignment, the pixel structure forms a cross-shaped dark fringe 40 as shown in fig. 2 at the boundary between the four alignment sub-regions of each sub-pixel, i.e., the middle of the sub-pixel, which affects the light transmittance.

Disclosure of Invention

The invention provides an array substrate and a liquid crystal display panel, which can reduce dark stripes in each sub-pixel and improve light transmittance.

In a first aspect, the present invention provides an array substrate, including an insulating layer and an indium tin oxide semiconductor layer disposed on the insulating layer, where an upper side of the indium tin oxide semiconductor layer contacts a liquid crystal, the array substrate further includes a plurality of sub-pixel units located below the insulating layer, the indium tin oxide semiconductor layer includes a plurality of first regions having the same number as the number of the sub-pixel units, where the first regions have the same size as the sub-pixel units, and are disposed in one-to-one correspondence with the sub-pixel units, a first groove is disposed in a middle of at least one of the first regions, and the first groove is cross-shaped in a direction along a normal to the array substrate.

In a second aspect, the present invention provides a liquid crystal display panel, which includes the array substrate as described above, a counter substrate disposed opposite to the array substrate, and a liquid crystal molecular layer sandwiched between the array substrate and the counter substrate.

The array substrate comprises an insulating layer and an indium tin oxide semiconductor layer arranged on the insulating layer, wherein the upper side of the indium tin oxide semiconductor layer is in contact with liquid crystal, the array substrate further comprises a plurality of sub-pixel units positioned below the insulating layer, the indium tin oxide semiconductor layer comprises a plurality of first areas with the same number as the sub-pixel units, the size and the size of the first areas are the same as those of the sub-pixel units, the first areas and the sub-pixel units are arranged in a one-to-one correspondence mode, a first groove is arranged in the middle of at least one first area, and the first grooves are in a cross shape in the normal direction of the array substrate. Due to the adoption of UV²When the liquid crystal display panel of the technology A is used for displaying after the liquid crystal display panel is aligned with the box, cross dark stripes can appear when the pixel is in a white state, namely, the liquid crystal molecules above the first area can generate the cross dark stripes at the position corresponding to the middle part of the first area due to the toppling, the first groove is arranged at the middle part of the first area, the first groove is in a cross shape in the normal direction along the array substrate, namely, the first groove is arranged at the position corresponding to the toppling of the toppling liquid crystal molecules, the toppling liquid crystal molecules are contacted with the first groove, and the toppling angle is formed along the inner surface of the groove, namely the inner wall due to the influence of the boundary effect, so that the dark stripes are lightened.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 shows UV in the prior art²A schematic diagram of an alignment method;

FIG. 2 is a schematic diagram of a dark fringe generated inside a sub-pixel unit in the prior art;

fig. 3 is a schematic top view of a portion of an array substrate corresponding to a first region according to an embodiment of the present invention;

fig. 4 is a cross-sectional view of a portion of an array substrate corresponding to a first region according to an embodiment of the present invention;

fig. 5 is a schematic top view illustrating another structure of an array substrate according to an embodiment of the invention;

fig. 6 is a cross-sectional view of a portion of the array substrate corresponding to the first region according to the second embodiment of the present invention;

fig. 7 is a cross-sectional view of a portion of an array substrate corresponding to a first region according to a third embodiment of the present invention;

fig. 8 is a schematic structural diagram of a liquid crystal display panel according to a fourth embodiment of the present invention.

Description of reference numerals:

1-an array substrate;

2-an insulating layer;

3-indium tin oxide semiconductor layer;

4-liquid crystal;

5-a sub-pixel unit;

6 — a first region;

7-opposite substrate;

8-a layer of liquid crystal molecules;

9-a first groove;

10-an alignment film;

20-alignment microstructure;

30-first liquid crystal molecules;

40-dark lines;

41-liquid crystal molecules;

92-a second recess;

93 — a third groove;

95-dark end-line.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms "sidewall", "above", and the like, are used in an orientation or positional relationship indicated based on those shown in the drawings, only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention.

In the description of the present invention, "a plurality" means a plurality, e.g., two, four, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "above" the second feature may comprise the first and second features being in direct contact, or the first and second features being in contact, not directly, but via another feature therebetween.

In the present invention, unless otherwise expressly stated or limited, the terms "connected" and the like are to be construed broadly, e.g., as meaning fixedly attached, detachably attached, or integrally formed; can be mechanically connected, electrically connected or can communicate with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

With the development of large display panels, better visual performance is higher and higher, and UV²A is one of the most popular display technologies at present, and has a wider viewing angle and a faster response speed.

UV²The key technology of A is that UV light can effectively and accurately perform different direction alignment on pixels, and the invention provides UV based on the technology²A is matched with special materials and graphic design, the width of dark lines of pixels can be effectively reduced, the transmittance is improved, the cost is effectively reduced, and the specification of a final product can be effectively improved.

Example one

Fig. 3 is a schematic top view of a portion of the array substrate corresponding to the first region according to an embodiment of the invention. Fig. 4 is a cross-sectional view of a portion of the array substrate corresponding to the first region according to a first embodiment of the invention. For convenience of explaining how to reduce the generation of dark stripes, fig. 3 and 4 only show schematic diagrams of portions corresponding to two first regions 6 (sub-pixel units) in the array substrate.

As shown in fig. 3 and 4, the array substrate 1 of the present embodiment includes an insulating layer 2 and an ito semiconductor layer 3 disposed on the insulating layer 2, an upper side of the ito semiconductor layer 3 contacts a liquid crystal 4, the array substrate 1 further includes a plurality of sub-pixel units 5 disposed under the insulating layer 2, the ito semiconductor layer 3 includes a plurality of first regions 6 having the same number as the sub-pixel units 5, wherein the first regions 6 have the same size as the sub-pixel units 5, the first regions 6 are disposed in one-to-one correspondence with the sub-pixel units 5, a first groove 9 is disposed in a middle portion of at least one of the first regions 6, and the first groove 9 is cross-shaped when viewed along a normal direction of the array substrate 1. The term "the size and the dimension of the first region 6 are the same as those of the sub-pixel unit 5" means that the shape and the dimension of the first region 6 are the same as those of the sub-pixel unit 5. The normal direction of the array substrate 1 is a direction perpendicular to the array substrate 1, and is viewed along the normal direction of the array substrate 1, specifically, viewed from above or from below the array substrate 1.

In the array substrate 1, an insulating layer 2 is formed to protect the array substrate and to flatten a surface on which the pixel electrode is formed. Due to the adoption of UV²In the technology a, when the liquid crystal display panel is aligned to the cell and displays, cross dark fringes appear when the pixel is in a white state, that is, dark fringes occur at a position corresponding to the middle of the first region 6 due to the liquid crystal molecules above the first region 6 falling. In this embodiment, since the first regions 6 are disposed in one-to-one correspondence with the sub-pixel units 5, the first grooves 9 are disposed in the middle of the first regions 6 corresponding to the positions where the dark stripes are generated, and the first grooves 9 are cross-shaped in the direction along the normal of the array substrate, so that the first grooves 9 can be disposed in the positions corresponding to the positions where the tilted liquid crystal molecules are generated. As shown in fig. 4, the first groove 9 is recessed from the surface of the ito layer 3 in a direction away from the liquid crystal 4, but does not penetrate the ito layer 3. Since the liquid crystal molecules 41 contact the first groove 9, an inward-inclining angle is formed along the inner surface of the first groove 9 due to the influence of the boundary effect, so that the alignment of the liquid crystal molecules is changed, and the dark fringes are reduced. Here, the insulating layer 2 may be an organic insulating layer or an inorganic insulating layer.

Optionally, the dielectric constant of the indium tin oxide semiconductor layer 3 is greater than the dielectric constant of the liquid crystal 4. The inventors have found that when the dielectric constant of the material of the indium tin oxide semiconductor layer 3 in direct contact with the liquid crystal 4 is larger than that of the liquid crystal 4, the dark stripes are thinned to some extent.

Further alternatively, as shown in fig. 4, the cross section of the first groove 9 in the groove depth direction may be triangular. When the cross section is in the shape of an inverted triangle as shown in fig. 4, since the sidewall of the first groove 9 forms an acute angle with respect to the horizontal plane, the liquid crystal molecules are substantially perpendicular to the sidewall, and the liquid crystal molecules tilt to the inner side of the groove at an acute angle with respect to the vertical direction, and the shading effect is better and more preferable. In addition, the cross section may be in other shapes, such as square, dovetail, semi-circular, etc., and at this time, since the boundary effect is more obvious, the liquid crystal molecules are more inclined, and the shading effect is slightly inferior to that of the case where the cross section is triangular. The examples given here are merely illustrative, and the present invention is not limited to this, and may be any other cross-sectional shape that can realize the tilt of liquid crystal molecules.

In addition, since the groove is directly formed on the surface of the ito semiconductor layer 3, the width of the groove cannot be too large, so as to affect the normal display of the sub-pixel unit, and reduce the display effect of the liquid crystal panel. Generally the groove width of the first grooves 9 is less than or equal to 1/10 of the width of the first areas 6. The width of the groove may be 3-15 μm, that is, when the width of the groove is less than 3 μm, the shading effect is not good, but when the width of the groove is greater than 15 μm, the normal display of the sub-pixel unit is affected. Meanwhile, the depth of the first groove 9 can be within the range of 10-100 μm to ensure better effect of reducing dark lines.

In addition, in the dark stripe diagram of fig. 2, it can be seen that the dark stripe is substantially cross-shaped, but an end dark stripe 95 is further formed at the end of the cross, i.e., the entire dark stripe substantially forms a swastika shape. Fig. 5 is a schematic top view of another structure of an array substrate according to an embodiment of the present invention, as shown in fig. 5, as an alternative embodiment, a third groove 93 communicated with the first groove 9 of the cross may be further optionally disposed along an outer edge portion of the first region 6, and the third groove 93 and the first groove are communicated and added together to form a swastika shape in a top view.

In this embodiment, the array substrate includes an insulating layer and an indium tin oxide semiconductor layer disposed on the insulating layer, an upper side of the indium tin oxide semiconductor layer is in contact with the liquid crystal, the array substrate further includes a plurality of sub-pixel units located under the insulating layer, the indium tin oxide semiconductor layer includes a plurality of first regions having the same number as the sub-pixel units, wherein the first regions have the same size as the sub-pixel units, the first regions are disposed in one-to-one correspondence with the sub-pixel units, a first groove is disposed in a middle portion of at least one of the first regions,the first groove is cross-shaped along the normal direction of the array substrate. Due to the adoption of UV²When the liquid crystal display panel of the technology A is used for displaying after box alignment, cross dark fringes can appear in the pixels in a white state, namely, the liquid crystal molecules above the first area can generate the cross dark fringes at the position corresponding to the middle part of the first area due to toppling, the first groove is arranged at the middle part of the first area, the first groove is in a cross shape in the normal direction along the array substrate, namely the first groove is arranged at the position corresponding to the toppling of the toppling liquid crystal molecules, the toppling liquid crystal molecules are in contact with the first groove, and an inward toppling angle is formed along the inner surface of the groove due to the influence of a boundary effect, so that the dark fringes are reduced.

Example two

On the basis of the first embodiment, the present embodiment improves the arrangement manner of the first groove in the first embodiment. The rest of the process is the same as the first embodiment and is not described herein again.

Fig. 6 is a cross-sectional view of a portion of the array substrate corresponding to the first region according to the second embodiment of the present invention. As shown in fig. 6, the first groove 9 penetrates the ito layer 3. This method is applied to the case where the ito semiconductor layer 3 is thin, and in order to ensure that a sufficient edge effect is generated on the liquid crystal molecules, the ito semiconductor layer 3 and the portion corresponding to the first groove 9 need to be formed in a hollow cross shape.

In addition, compared with the case that the first groove 9 does not penetrate through the ito semiconductor layer 3, the surface of the ito semiconductor layer 3 needs to be etched after the ito semiconductor layer 3 is formed, so as to form the first groove 9 with a certain depth, and since the depth of the groove is limited, the etching process has a high requirement for precision, which results in a high cost. In the present embodiment, the first groove 9 penetrates the ito layer 3, so that the formation process is simplified. Since the first groove 9 on the ito semiconductor layer 3 is formed as a through groove and thus the liquid crystal is directly in contact with the insulating layer 2 exposed to the surface through the first groove 9, the dielectric constant of the insulating layer can be selected to be larger than that of the liquid crystal, so as to achieve the effect of making the dark lines thin.

In the array substrate of this embodiment, the first groove is disposed through the ito layer. When the thickness of the ITO semiconductor layer is thin, the sufficient edge effect on the liquid crystal molecules can be ensured, and the effect of making the dark stripes thin is better.

EXAMPLE III

On the basis of the second embodiment, the present embodiment further improves the groove portion in the second embodiment. The rest is the same as the embodiment and is not described herein.

Fig. 7 is a cross-sectional view of a portion of the array substrate corresponding to the first region according to the third embodiment of the present invention. As shown in fig. 7, in the second embodiment, after the first groove 9 penetrates through the ito layer 3, a plurality of second grooves 92 are formed on the surface of the insulating layer 2 contacting the ito layer 3, and the projections of the plurality of second grooves 92 in the normal direction of the array substrate 1 coincide with the plurality of first grooves 9. This method is applied to the case where the ito semiconductor layer 3 has a small thickness, and in order to ensure that a sufficient fringe effect is generated on the liquid crystal molecules, the ito semiconductor layer 3 corresponding to the first groove 9 needs to be formed in a hollowed cross shape, and the second groove 92 needs to be formed in the insulating layer 2 corresponding to the first groove 9. Here, the first groove 9 and the second groove 92 cooperate with each other to tilt the liquid crystal molecules in the first groove 9, thereby reducing dark streaks.

In addition, as in the second embodiment, since the first groove 9 on the ito semiconductor layer 3 is formed as a through groove and thus the liquid crystal is directly in contact with the insulating layer 2 exposed to the surface through the first groove 9, the dielectric constant of the insulating layer can be selected to be larger than that of the liquid crystal, so as to achieve the effect of making the dark line fine.

In addition, similarly to the first embodiment, the cross section of the second groove 92 in the depth direction of the second groove 92 is also triangular.

In this way, since the sidewall of the second groove 92 forms an acute angle with respect to the horizontal plane, the liquid crystal molecules in the first groove 9 are substantially perpendicular to the sidewall of the second groove 92, and the shading effect is better and more preferable. In addition, the cross section may be in other shapes, such as square, dovetail, semi-circular, etc., and at this time, since the boundary effect is more obvious, the liquid crystal molecules are more inclined, and the shading effect is slightly inferior to that of the case where the cross section is triangular. The examples given here are merely illustrative, and the present invention is not limited to this, and may be any other interface shape that can realize the tilt of liquid crystal molecules.

In addition, since the surface of the ito semiconductor layer 3 and the surface of the insulating layer 2 are directly provided with the grooves, the width and the depth of the grooves cannot be too large, so as to affect the normal display of the sub-pixel units, and reduce the display effect of the liquid crystal panel. In general, the width of the groove portion of the second groove 92, similar to the first groove 9, is smaller than 1/10 of the width of the first region 6, and may be in the range of 3 to 15 μm. The sum of the depths of the first groove 9 and the second groove 92 can be in the range of 10-100 μm to ensure better effect of reducing dark lines. In addition, similarly to the embodiment, as an alternative implementation manner, when a third groove 93 communicated with the first groove 9 of the cross is provided along the outer edge portion of the first area 6, a fourth groove having the same shape and size as the third groove is correspondingly formed in the second groove, and the fourth groove and the second groove are communicated and added together to form a swastika shape in plan view.

In the array substrate of this embodiment, the first groove is disposed through the ito layer, and a plurality of second grooves are formed on a surface of the insulating layer in contact with the ito layer, and projections of the plurality of second grooves in a normal direction of the array substrate completely overlap with the plurality of first grooves. When the thickness of the ITO semiconductor layer is thin, the first groove and the second groove are matched with each other to ensure that enough edge effect is generated on liquid crystal molecules, so that the effect of making dark stripes thin is better.

Example four

Fig. 8 is a schematic structural diagram of a liquid crystal display panel according to a fourth embodiment of the present invention. As shown in fig. 8, the present embodiment provides a liquid crystal display panel, which includes the array substrate 1 according to any one of the first to third embodiments, the opposite substrate 7 disposed opposite to the array substrate 1, and the liquid crystal molecule layer 8 sandwiched between the array substrate 1 and the opposite substrate 7. The specific structure of the array substrate 1 has been described in detail in the first to third embodiments, and is not described herein again.

Optionally, the opposite substrate may be a color filter substrate.

The display device of the embodiment includes the array substrate as described in any one of the first to third embodiments, and therefore, the groove can be disposed at the position corresponding to the region where the dark fringe is to be generated, so that the liquid crystal molecules at the position are inclined due to the edge effect, thereby reducing the dark fringe in the liquid crystal display panel. Meanwhile, the pattern design of the special pixel indium tin oxide semiconductor layer is used on the array substrate side, and the selection of different dielectric coefficients of the insulating layer material, the indium tin oxide semiconductor layer and the liquid crystal can enable the pixel dark lines to achieve the effect of fine lines.

EXAMPLE five

The embodiment provides a manufacturing method of an array substrate. The manufacturing method of the array substrate of the present embodiment is used for manufacturing the array substrate described in the third embodiment. The specific structure of the array substrate has been described in detail in the third embodiment, and is not described herein again.

The manufacturing method of the array substrate of the embodiment includes the following steps:

s1, an insulating layer is formed on the substrate on which the sub-pixel cells are formed.

The insulating layer is formed to protect the array substrate and to flatten a surface on which the pixel electrode is formed.

And S2, forming a plurality of second grooves in a plurality of areas corresponding to the sub-pixel units on the insulating layer by an etching method, wherein the second grooves are in a cross shape along the normal direction of the array substrate, the width of each second groove is 3-15 μm, and the depth of each second groove is 10-100 μm.

S3, an indium tin oxide semiconductor layer is formed on the insulating layer.

S4, forming a plurality of first grooves penetrating the indium tin oxide semiconductor layer on the indium tin oxide semiconductor layer at the positions corresponding to the plurality of second grooves of the insulating layer by an etching method, wherein the width of the first grooves is 3-15 μm, and the projection of the plurality of second grooves on the normal direction of the array substrate completely coincides with the plurality of first grooves.

When the above embodiment is further modified, step S2 may further include:

s21, forming fourth grooves at the cross ends of the second grooves on the insulating layer, wherein the fourth grooves are communicated with the end parts of the second grooves, and the fourth grooves are communicated with the second grooves and added together to form a swastika shape in plan view.

Correspondingly, step S4 may further include:

s41, forming third grooves at the cross ends of the first grooves, wherein the third grooves are communicated with the ends of the first grooves, and the third grooves are communicated with the first grooves and added together to form a swastika shape in plan view.

In this way, recesses are formed on the insulating layer and the ITO semiconductor layer, which are overlapped to form a recess for generating an edge effect on liquid crystal molecules.

In the manufacturing method of the array substrate of this embodiment, first, a plurality of second grooves are formed on the insulating layer, then, a first groove that completely corresponds to and coincides with the plurality of second grooves is formed on the ito semiconductor layer, and a depression for generating an edge effect on liquid crystal molecules is formed by adding the first groove and the second groove together, so that the liquid crystal molecules at the depression are tilted, thereby reducing dark streaks.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.

In addition, in the present invention, unless otherwise explicitly specified or limited, the terms "connected," "fixed," "mounted," and the like are to be construed broadly, e.g., as mechanical or electrical connections; the terms may be directly connected or indirectly connected through an intermediate, and may be used for communicating between two elements or for interacting between two elements, unless otherwise specifically limited, and the specific meaning of the terms in the present invention will be understood by those skilled in the art according to specific situations.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An array substrate is characterized by comprising an insulating layer and an indium tin oxide semiconductor layer arranged on the insulating layer, wherein the upper side of the indium tin oxide semiconductor layer is in contact with liquid crystal, the array substrate further comprises a plurality of sub-pixel units positioned below the insulating layer, the indium tin oxide semiconductor layer comprises a plurality of first areas, the number of the first areas is the same as that of the sub-pixel units, the first areas are the same as that of the sub-pixel units, the first areas and the sub-pixel units are arranged in a one-to-one correspondence mode, a first groove is arranged in the middle of at least one first area, and the first groove is in a cross shape;

follow the outer edge part of first region be equipped with the third recess of first recess intercommunication, the third recess with first recess is "swastika".

2. The array substrate of claim 1, wherein the indium tin oxide semiconductor layer has a dielectric constant greater than that of the liquid crystal.

3. The array substrate of claim 2, wherein the cross section of the first groove along the depth direction of the groove is triangular.

4. The array substrate of claim 2, wherein the first groove penetrates through the indium tin oxide semiconductor layer.

5. The array substrate of claim 4, wherein a plurality of second grooves are formed on the surface of the insulating layer contacting the ITO semiconductor layer, and projections of the plurality of second grooves in a normal direction of the array substrate coincide with the plurality of first grooves.

6. The array substrate of claim 5, wherein the dielectric constant of the insulating layer is greater than the dielectric constant of the liquid crystal.

7. The array substrate of claim 5, wherein the cross section of the second groove along the depth direction of the second groove is triangular.

8. The array substrate of claim 1, wherein the groove width of the first groove is less than or equal to 1/10 of the width of the first region.

9. A liquid crystal display panel comprising the array substrate according to any one of claims 1 to 8, a counter substrate disposed opposite to the array substrate, and a layer of liquid crystal molecules sandwiched between the array substrate and the counter substrate.