CN109244077A - The production method of three-dimensional storage - Google Patents
The production method of three-dimensional storage Download PDFInfo
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- CN109244077A CN109244077A CN201811031283.0A CN201811031283A CN109244077A CN 109244077 A CN109244077 A CN 109244077A CN 201811031283 A CN201811031283 A CN 201811031283A CN 109244077 A CN109244077 A CN 109244077A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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Abstract
The present invention provides a kind of production method of three-dimensional storage, the following steps are included: providing semiconductor structure, the semiconductor structure includes virtual hierarchic structure and stacked structure, the virtual hierarchic structure includes multi-stage stairs, every grade of step has different height, the stacked structure is conformally formed in the virtual hierarchic structure, and the stacked structure includes the multiple first material layers and multiple second material layers being alternately stacked；It removes at least partly stacked structure and forms exposed contact surface in the multiple first material layer；It is formed respectively through multiple conductive contacts of the contact the multiple first material layer of face contact；Insulating layer is covered on the stacked structure；It is formed on the insulating layer the multiple contact portions extended through to the multiple conductive contact；Wherein, the stacked structure is located at the lamination quantity difference on the lamination quantity and the N+1 grades of steps on the N grades of steps, and N is the integer more than or equal to 1.
Description
Technical field
The invention mainly relates to field of semiconductor manufacture more particularly to a kind of production methods of three-dimensional storage.
Background technique
In order to overcome the limitation of two-dimensional storage device, industry has been developed that the memory device with three-dimensional (3D) structure,
Integration density is improved by the way that memory cell is three-dimensionally disposed in substrate.
In the three-dimensional storage part of such as 3D nand flash memory, storage array may include the core area (core) and stepped region.
Stepped region is used to draw contact portion for the grid layer in each layer of storage array.Wordline of these grid layers as storage array, holds
The operation such as row programming, erasable, reading.
In the manufacturing process of 3D nand flash memory, etching forms contact hole in the hierarchic structures at different levels of stepped region, then
Filling contact hole, to draw the electric signal of grid layer.In the actual production process, since the 3D-NAND flash memory ladder number of plies is more,
In contact hole etching step, in order to guarantee that lower layer's ladder can smoothly be drawn, upper layer ladder is easy by over etching (Over
Etch), there is etching break-through (Punch Through), lead to not meet technique requirement, reduce product yield.
To solve the above-mentioned problems, it generally requires to carry out multiple illumination and etching, thus depth when reducing etching every time
Difference.
Summary of the invention
The technical problem to be solved by the present invention is to a kind of methods for making three-dimensional storage, can overcome wordline bonding pad
The problems such as etching defect, and multiple illumination and etching need not be carried out.
In order to solve the above technical problems, the present invention provides a kind of production methods of three-dimensional storage, comprising the following steps:
Semiconductor structure is provided, the semiconductor structure includes virtual hierarchic structure and stacked structure, and the virtual hierarchic structure includes
Multi-stage stairs, every grade of step have different height, and the stacked structure is conformally formed in the virtual hierarchic structure
On, the stacked structure includes the multiple first material layers and multiple second material layers being alternately stacked；Removal at least partly stacks
Structure and exposed contact surface is formed in the multiple first material layer；Wherein, after removal at least partly stacked structure, institute
Lamination quantity difference of the stacked structure on the lamination quantity and the N+1 grades of steps on the N grades of steps is stated, N is
Integer more than or equal to 1；It is formed respectively through multiple conductive contacts of the contact the multiple first material layer of face contact；?
Insulating layer is covered on the stacked structure；It is formed on the insulating layer to extend through to the multiple of the multiple conductive contact and connect
Contact portion.
In one embodiment of this invention, the first material layer is dummy gate layer or dummy gate layer, second material
Layer is dielectric layer.
In one embodiment of this invention, the conductive contact is identical as the material of the grid layer.
In one embodiment of this invention, the contact surface is the upper surface of the first material layer, the conductive contact
The thickness with a thickness of second material layer described in single layer.
In one embodiment of this invention, the contact surface is that the first material layer is removed at least part thickness shape
At medial surface, the thickness of the conductive contact is greater than the thickness of second material layer described in single layer.
In one embodiment of this invention, the method for forming the virtual hierarchic structure is to cut down etching method.
In one embodiment of this invention, it removes at least partly stacked structure and is formed in the multiple first material layer
The step of exposed contact surface includes: the part table of removal at least partly stacked structure and the multiple second material layer of exposure
Face；And it removes at least partly second material layer at the part of the surface and exposes the contact surface in the first material layer.
In one embodiment of this invention, the portion of at least partly stacked structure and the multiple second material layer of exposure is removed
The method for dividing surface is to cut down etching method, center position of the direction for cutting down etching towards the semiconductor structure.
In one embodiment of this invention, remove at least partly second material layer at the part of the surface and exposure described in
Contact surface step in first material layer includes: photoresist to be covered on the dielectric layer being exposed and to the photoetching
Glue carries out dry etching.
In one embodiment of this invention, the dry etching can be single layer dry etching.
In one embodiment of this invention, it is formed respectively through the more of the contact the multiple first material layer of face contact
The step of a conductive contact includes: to be covered in conductive contact and the removal second material layer in the first material layer
Conductive contact.
In one embodiment of this invention, it is formed on the insulating layer after the contact portion for being through to the conductive contact
Further include: it removes the dummy gate layer and forms gap between the dielectric layer and form grid layer in the gap.
It in one embodiment of this invention, further include forming peripheral components below the virtual hierarchic structure.
The invention has the following advantages that the present invention provides a kind of production method of three-dimensional storage, the semiconductor that provides
Structure includes virtual hierarchic structure and stacked structure, has preformed conductive contact on stacked structure, can increase stacking
The thickness of grid layer in structure, since the thickness of grid layer increases, it is not easy to be worn by erosion, therefore the risk that etching break-through occurs is big
To reduce.
Detailed description of the invention
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates, in which:
Figure 1A -1F is a kind of flow chart of the production method of three-dimensional storage.
Fig. 2A -2B is a kind of structural schematic diagram of three-dimensional storage.
Fig. 3 is a kind of flow chart of the production method of three-dimensional storage of one embodiment of the invention.
Fig. 4 A-4F is that a kind of section of the example process of the production method of three-dimensional storage of one embodiment of the invention shows
It is intended to.
Fig. 5 A-5L is the section signal that exposed contact surface is formed in multiple first material layers of one embodiment of the invention
Figure.
Fig. 6 is a kind of structural schematic diagram of three-dimensional storage of one embodiment of the invention.
Specific embodiment
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, therefore the present invention is by the limit of following public specific embodiment
System.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus
The step of may also including other or element.
When describing the embodiments of the present invention, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion work
Partial enlargement, and the schematic diagram is example, should not limit the scope of protection of the invention herein.In addition, in practical system
It should include the three-dimensional space of length, width and depth in work.
For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper"
Etc. spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will reason
Solve, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing
Other directions.For example, being described as be in other elements or feature " below " or " under " if overturning the device in attached drawing
Or the direction of the element of " following " will be changed to " top " in the other elements or feature.Thus, illustrative word " under
Side " and " following " can include upper and lower both direction.Device may also have other directions (to be rotated by 90 ° or in its other party
To), therefore spatial relation description word used herein should be interpreted accordingly.In addition, it will also be understood that being referred to as when one layer at two layers
" between " when, it can be only layer between described two layers, or there may also be one or more intervenient layers.
If background technique is introduced, in the three-dimensional storage part of such as 3D nand flash memory, storage array may include core
(core) area and stepped region.Stepped region is used to draw contact portion for the grid layer in each layer of storage array.These grid layer conducts
The wordline of storage array executes the operation such as programming, erasable, reading.
In the manufacturing process of 3D nand flash memory, etching forms contact hole in the hierarchic structures at different levels of stepped region, then
Filling contact hole, to draw the electric signal of grid layer.In the actual production process, since the 3D-NAND flash memory ladder number of plies is more,
In contact hole etching step, in order to guarantee that lower layer's ladder can smoothly be drawn, upper layer ladder is easy by over etching (Over
Etch), there is etching break-through (Punch Through), lead to not meet technique requirement, reduce product yield.
Figure 1A -1F is a kind of flow chart of the production method of three-dimensional storage.The production method is mainly in ladders at different levels
Upper etching forms contact hole.The process for forming contact hole includes that formation as shown in Figure 1A has the dummy gate layer being alternately stacked
101 and dielectric layer 102 stacked structure 110, the edge in stacked structure 110 as shown in Figure 1B forms hierarchic structure, such as schemes
Shown in 1C on stacked structure 110 cover insulating layer 103, and as shown in figure iD dummy gate layer 101 is replaced with into grid
Layer 104 forms contact hole 106 by etching mask 105, the formation of filling contact hole 106 connects finally respectively as shown in Fig. 1 E and 1F
Contact portion 107.
As shown in figure iD, stepped region grid layer 104 is relatively thin in this method, is easy by over etching.As shown in Figure 2 A, contact hole
Since depth difference is larger when 106 etching, when in bosom, contact hole is just etched in place, most shallow place's contact hole can occur etching and wear
It is logical to cause short circuit.In order to avoid most shallowly by over etching, usually segmentation etching different zones Metal gate layer is corresponding hangs down place's contact hole
Clear opening, as shown in Figure 2 B, this method need to carry out multiple tracks photoetching, etch step, and cost is higher with time cost, seriously affects
Volume production rate, and the number of plies of stacked memory cell is more, the photoetching that need to be carried out, etching technics are more.
Fig. 3 is a kind of flow chart of the production method of three-dimensional storage of one embodiment of the invention.Fig. 4 A-4F is the present invention
A kind of diagrammatic cross-section of the example process of the production method of three-dimensional storage of one embodiment.Below with reference to shown in Fig. 3-4F
The production method for describing a kind of three-dimensional storage of the present embodiment.
In step 302, semiconductor structure is provided.
This semiconductor structure is at least one for being used for structure of the follow-up process to ultimately form three-dimensional storage part
Point.Semiconductor structure may include array area (array), array area may include core space (core) and stepped region (stair step,
SS).Core space is the region for including storage unit, and stepped region is the region for including wordline connection circuit.In terms of vertical direction, battle array
Column area can have substrate and stack layer, channel hole array is formed on the stacked structure of core space, the stacking knot in stepped region
Virtual channel hole array can be formed on structure, stacked structure includes the first material layer and second material layer being alternately stacked.First
Material layer can be dummy gate layer or grid layer.Second material layer can be dielectric layer.To simplify the explanation, hereafter with the first material
The bed of material is dummy gate layer, and second material layer is illustrated for dielectric layer.
In the sectional view of semiconductor structure 400a exemplified by Fig. 4 A, semiconductor structure 400a may include virtual ladder knot
Structure 410 and stacked structure 420.For simplicity, other regions of semiconductor structure in the horizontal direction, such as core are not shown
Area.And other layers of hierarchic structure in vertical direction, such as substrate are also not shown.Virtual hierarchic structure 410 includes multistage
Step 410a, 410b, 410c and 410d.Multi-stage stairs 410a, 410b, 410c and 410d have different height, i.e. every grade of platform
The top surface of rank is located at different height.The height of the top surface of step is higher, and the series of step is bigger.Virtual hierarchic structure
410 height can increase along the center position far from semiconductor structure 400a, can also be along separate semiconductor structure 400a's
Center position reduces.The center position of semiconductor structure refers to the direction in semiconductor structure where core space.Preferably, such as
Shown in Fig. 4 A, the height of virtual hierarchic structure 410 increases along the center position far from semiconductor structure 400a.Semiconductor in Fig. 4 A
For the core space of structure 400a in left side, the center position far from semiconductor structure 400a is from left to right.Form virtual ladder knot
The method of structure 410 can be reduction etching (trim/etch).Reduction quarter is carried out along the center position far from semiconductor structure 400a
Erosion can form height along the increased virtual hierarchic structure 410 of center position far from semiconductor structure 400a.It is appreciated that edge
Cut down close to the center position of semiconductor structure 400a etching and can form height along far from along semiconductor structure 400a
The virtual hierarchic structure 410 that heart direction reduces.Stacked structure 420 is conformally formed in virtual hierarchic structure 410.Stacked structure
420 include the multiple dummy gate layer 420a and multiple dielectric layer 420b being alternately stacked.Multiple dummy gate layers in stacked structure 420
The number of plies of 420a and multiple dielectric layer 420b depend on the number of plies (such as 32 layers or 64 layers) of made three-dimensional storage part.Fig. 4 A
Stacked structure 420 is shown with 6 layers of dummy gate layer 420a and 6 layers of dielectric layer 420b, however this does not represent actual dummy grid
The number of plies of layer 420a and dielectric layer 420b.The method that stacked structure 420 is formed in virtual hierarchic structure 420 can be alternately heavy
Product dummy gate layer 420a and dielectric layer 420b.The method of deposition dummy gate layer 420a and dielectric layer 420b can be atomic layer deposition
Method (Atomic Layer Deposition, ALD).Deposition every layer of dummy gate layer 420a and dielectric layer 420b shape with
The shape of virtual hierarchic structure 420 is identical.
In an embodiment of the present invention, the material of dummy gate layer 420a can be silicon nitride.The material example of dielectric layer 420b
Silica in this way.
Although there is described herein the exemplary composition of initial semiconductor structure, it is to be understood that, one or more features
It can be omitted, substitute or increase to from this semiconductor structure in this semiconductor structure.In addition, each layer illustrated
Material be only exemplary, such as dummy gate layer 420a and dielectric layer 420b can also select charge storage type (CTF) three
Tie up available other materials in nand memory.Such as dummy gate layer 420a and dielectric layer 420b can also be silica with (not
Doping) polysilicon or combination, silicon oxide or silicon nitride and the combination of amorphous carbon of amorphous silicon etc..
In step 304, removes at least partly stacked structure and form exposed contact surface in multiple first material layers.
Here, removal at least partly stacked structure, forms exposed contact surface in multiple first material layers.Removal is at least
After the stacked structure of part, stacked structure is located at the lamination quantity on the lamination quantity and N+1 grades of steps on N grades of steps not
Together, N is the integer more than or equal to 1.Lamination quantity on step refers to the number of complete lamination.Removal at least partly stacks
Structure and the step of forming exposed contact surface in multiple first material layers may include removal at least partly stacked structure and
The part of the surface of the multiple second material layers of exposure and at least partly second material layer and exposure first at removal part of the surface
Contact surface in material layer.The method of removal at least partly stacked structure and the part of the surface of the multiple second material layers of exposure can be with
To cut down etching method.It removes at least partly second material layer at part of the surface and exposes the contact surface step in first material layer
It may include covering photoresist in the second material layer being exposed and dry etching being carried out to photoresist.Dry etching can
To be single layer dry etching.The step of contact surface formed in exposure first material layer, will be described in detail later.Contact surface can be
The upper surface of first material is also possible to the medial surface that first material layer is removed the formation of at least part thickness.
In the sectional view of semiconductor structure 400b exemplified by Fig. 4 B, stacking stack structure in the middle part of semiconductor structure 400a
420 are removed, and multiple dummy gate layer 420a form exposed contact surface 420c.Removal at least partly stacked structure 420 and more
The step of exposed contact surface 420c is formed on a dummy gate layer 420a may include removal at least partly stacked structure 420 and it is sudden and violent
Reveal at least partly dielectric layer 420b at the part of the surface and removal part of the surface of multiple dielectric layer 420b and exposes dummy grid
Contact surface 420c on layer 420a.The method of removal at least partly stacked structure and the part of the surface of the multiple dielectric layer 420b of exposure
The direction of etching can be cut down towards the center position of semiconductor structure to cut down etching method.The center position of semiconductor structure
Refer to the direction in semiconductor structure where core space.The core space of semiconductor structure 400b is in left side in Fig. 4 B, towards half
The center position of conductor structure 400b is to turn left from the right side.It removes at least partly dielectric layer 420b at part of the surface and exposes pseudo- grid
Contact surface step on the layer 420a of pole may include photoresist being covered on the dielectric layer 420b being exposed and to photoresist
Carry out dry etching.Dry etching can be single layer dry etching.Contact surface 420c is the whole of dummy gate layer 420a in Fig. 4 B
Thickness is removed and the medial surface that is formed.It is appreciated that contact surface 420c is also possible to upper surface or the puppet of dummy gate layer 420a
Grid layer 420a is removed the medial surface that a part of thickness is formed.The position of contact surface 420c can be controlled by the depth of etching
System.For example, the depth when etching is the thickness of single-layer medium layer 420b, contact surface 420c is the upper surface of dummy gate layer 420a.
When the depth of etching is the thickness more than single-layer medium layer 420b and is less than single-layer medium layer 420b plus single layer dummy gate layer
When the thickness of 420a, contact surface 420c is the medial surface of dummy gate layer 420a.After removal at least partly stacked structure 420, heap
Stack structure 420 is located at the lamination quantity difference on the lamination quantity and N+1 grades of steps on N grades of steps, and N is more than or equal to 1
Integer.Lamination quantity on step refers to the number of complete lamination.For example, as shown in Figure 4 B, removal at least partly heap
After stack structure 420, layer number on step 410a is 8 (4 layers of grid layer 420a, 4 layers of dielectric layer 420b), on step 410b
Layer number be 6 (3 layers of grid layer 420a, 3 layers of dielectric layer 420b), the layer number on step 410c is 4 (2 layers of grid layer
420a, 2 layers of dielectric layer 420b), the layer number on step 410d is 0.It can be seen in fig. 4b stacked structure 420 is located at N
Lamination quantity in grade step (such as step 410a, 410b, 410c) and N+1 grades of steps (such as step 410b, 410c,
Lamination quantity on 410d) is different.Further, in Fig. 4 B, the height of virtual hierarchic structure 410 is along far from semiconductor structure 410b
Center position increase, stacked structure 420 is located at the lamination number on greater than N+1 grades steps of the lamination quantity on N grade steps
Amount.It is appreciated that accordingly, if the height of virtual hierarchic structure 410 is reduced along the center position far from semiconductor structure 410b,
Stacked structure 420 is located at the lamination quantity that the lamination quantity on N grades of steps is greater than on N+1 grades of steps.
In step 306, formed respectively through multiple conductive contacts of the contact multiple first material layers of face contact.
In this step, it is formed respectively through multiple conductive contacts of the contact multiple first material layers of face contact.It is formed and is divided
It not may include that conductive layer is covered in first material layer by the multiple conductive contacts for contacting the multiple first material layers of face contact
And the conductive layer in removal second material layer.The method that conductive layer is covered in first material layer can be atomic layer deposition
Method.The thickness of conductive contact can be slightly larger than the distance between contact surface to second material layer corresponding with the contact surface.It is conductive
The material of contact can be identical as the material of grid layer, such as is all tungsten.The then conductive layer in removal second material layer,
So that mutually insulated between each conductive contact.The method of conductive layer in removal second material layer can be wet etching.It is wet
The etching agent of method etching can be phosphoric acid.So far, contact has conductive contact in each first material layer.
In the sectional view of semiconductor structure 400c exemplified by Fig. 4 C, conduction is covered on the surface semiconductor structure 400c
Layer 430, conductive layer 430 can fill dummy gate layer 420a and be etched the groove to be formed, formed contacted by contact surface 420c it is multiple
Multiple conductive contact 430a of dummy gate layer 420a.The method for forming conductive layer 430 can be atomic layer deposition method.Conductive contact
The thickness of 430a is slightly larger than the distance between contact surface 420c to dielectric layer 420b corresponding with contact surface 420c.Conductive contact
The material of 430a can be identical as the material of grid layer, such as is all tungsten.
In the sectional view of semiconductor structure 400d exemplified by Fig. 4 D, the conductive layer 430 on dielectric layer 420b is removed.
The method of conductive layer 430 on removal dielectric layer 420b can be wet etching.The etching agent of wet etching can be phosphoric acid.It is situated between
After conductive layer 430 on matter layer 420b is removed, the thickness of conductive contact 430a is substantially equal to contact surface 420c and connects to this
The distance between corresponding dielectric layer 420b of contacting surface 420c.So far, contact has conductive contact on each dummy gate layer 420a
430a。
In step 308, insulating layer is covered on stacked structure.
In this step, insulating layer is covered on stacked structure.The method that insulating layer is covered on stacked structure can wrap
Include deposition.Can from known various depositing operations, such as low-pressure chemical vapor deposition (Low Pressure CVD, LPCVD),
Plasma enhanced chemical vapor deposition (Plasma Enhanced CVD, PECVD), high-density plasma chemical gas phase are heavy
Long-pending (High density Plasma CVD, HDPCVD), Metalorganic chemical vapor deposition (Metal-Organic CVD,
MOCVD) MOCVD, molecular beam epitaxy (Molecular Beam Epitaxial, MBE), choose suitable work in atomic layer deposition
Skill.It can also include being planarized to the surface of insulating layer in the step of covering insulating layer on stacked structure.To insulating layer
The technique that surface is planarized can be chemical machinery and polish (Chemical Mechanical Polishing, CMP).Absolutely
The material of edge layer may, for example, be silica.
In the sectional view of semiconductor structure 400d exemplified by Fig. 4 D, insulating layer 440 is covered on stacked structure 420.
The surface of insulating layer 440 is flat.The technique for forming the surface of flat insulating layer 440 can be chemical machinery and polish.Absolutely
The material of edge layer 440 may, for example, be silica.
In step 310, the multiple contact portions extended through to multiple conductive contacts are formed on the insulating layer.
In this step, the multiple contact portions extended through to multiple conductive contacts are formed on the insulating layer.It can be according to
Usual manner etches to form the contact hole for extending vertically through stacked structure.Contact hole can pass perpendicularly through insulating materials from upper surface, arrive
Up to each conductive contact.
The mode for forming contact hole e.g. etches or other known mode, it is not limited here.Form contact hole
Later, with conductive material filling contact hole to form contact portion.It is formed after contact portion, when first material layer is dummy gate layer
When, it can also include removal dummy gate layer and form gap between dielectric layer, and in gap the step of formation grid layer.
When first material layer is grid layer, this step just can be omitted.
In the sectional view of semiconductor structure 400f exemplified by Fig. 4 F, covering insulating material 440 in each hierarchic structure, and
It is respectively formed the contact hole (not shown) that each conductive contact 430a is reached across insulating materials 440.Later, can pass through to
Contact hole fills contact portion 450, provides conductive path for the core space of storage array.The material of contact portion 470 is, for example, metal,
Such as tungsten (W).It then removes dummy gate layer 420a and forms gap between dielectric layer 420b, and form grid in gap
Layer.
Flow chart has been used to be used to illustrate operation performed by method according to an embodiment of the present application herein.It should be understood that
, the operation of front not necessarily accurately carries out in sequence.On the contrary, various steps can be handled according to inverted order or simultaneously
Suddenly.Meanwhile or during other operations are added to these, or from these processes remove a certain step or number step operation.For example, also
It may include forming virtual channel hole in the semiconductor structure, to provide support for semiconductor structure.It is appreciated that virtual channel
There is no separate dummy gate layer or grid layer completely in hole.Virtual channel hole is only to run through dummy gate layer or gate layer portions cross
The cavernous structure of sectional area, control signal still can be transmitted to core space by grid layer.In another example void can also be included in
Peripheral components are formed below quasi- ladder.
Above-described embodiment is formed by semiconductor structure, and using subsequent conventional steps, three-dimensional storage can be obtained
Part.Semiconductor structure, which is formed by, with reference to the present embodiment herein describes three-dimensional storage according to an embodiment of the invention.
Fig. 5 A-5L is the section signal that exposed contact surface is formed in multiple first material layers of one embodiment of the invention
Figure.For ease of description, indicate the basic stacked structure of stacked structure 520 with ON layers, every layer ON layers include second material layer and
First material layer below second material layer.Fig. 5 A-5L show stacked structure 520 include 6 layers ON layers (from top to bottom according to
It is secondary be 520a, 520b, 520c, 520d, 520e, 520f), however this and represent the actual number of plies.
It removes at least partly stacked structure and can wrap the step of forming exposed contact surface in multiple first material layers
It includes removal at least partly stacked structure and exposes at the part of the surface and removal part of the surface of multiple second material layers at least
Part second material layer and expose the contact surface in first material layer.Fig. 5 A-5I show removal at least partly stacked structure and
The process of the part of the surface of the multiple second material layers of exposure.Fig. 5 J-5L shows at least partly second at removal part of the surface
Material layer and the process for exposing the contact surface in first material layer.
As shown in Fig. 5 A-5I, the side of removal at least partly stacked structure and the part of the surface of the multiple second material layers of exposure
Method can be reduction etching method.The direction of etching is cut down towards the center position (center of semiconductor in Fig. 5 A of semiconductor structure
In left side, the center position towards semiconductor structure is from right to left).In Fig. 5 A, photoresist is covered on stacked structure 520
530.The surface of photoresist 530 is flat.Forming flat photoresist 530 can be spin coating (Spin-on).In Fig. 5 B, beat
Part photoresist 530 is opened, so that ON layers of 520a are exposed.It is exposed in Fig. 5 C, ON layers of 520b, ON layers of 520a are partially carved
Erosion.In Fig. 5 C, part photoresist 530 is removed, ON layers of 520c are exposed, and ON layers of 520a and ON layers of 520b are partially etched.So
Afterwards as shown in Fig. 5 D-5I, reduction etching successively is carried out towards the center position of semiconductor structure.In Fig. 5 I, each ON layers (i.e.
520a, 520b, 520c, 520d, 520e, 520f) the part of the surface of second material layer be exposed.
As shown in Fig. 5 J-5L, removes at least partly second material layer at part of the surface and expose in first material layer
Contact surface step may include covering photoresist in the second material layer being exposed and carrying out dry etching to photoresist.
Dry etching can be single layer dry etching.In Fig. 5 J, photoresist 530 is covered on stacked structure.The surface of photoresist 530 is
Flat.Forming flat photoresist 530 can be spin coating (Spin-on).In Fig. 5 K, using photomask to photoresist 530 into
Row etching forms the hole 540 for reaching multiple second material layers.The part of the surface of each ON layers of second material layer is correspondingly formed
There is hole 540.In Fig. 5 L, through hole 540 performs etching the second material layer being exposed.The etching can be single layer etching.
By the illustrative step as shown in Fig. 5 A-5L, the contact of exposure can be formed in multiple first material layers
Face 550.
Fig. 6 shows a kind of partial structurtes of three-dimensional storage 600 according to an embodiment of the invention.As shown in fig. 6, three
Tieing up memory includes semiconductor structure 600.Semiconductor structure 600 includes virtual hierarchic structure 610 and stacked structure 620.Virtually
Hierarchic structure 610 includes multi-stage stairs.Multi-stage stairs have different height, i.e., the top surface of every grade step is located at different height
Degree.The height of step top surface is higher, and the series of step is bigger.The height of virtual hierarchic structure 610 can be along far from semiconductor
The center position of structure 400a increases, and can also reduce along the center position far from semiconductor structure 400a.Semiconductor structure
Center position refers to the direction in semiconductor structure where core space.Preferably, as shown in fig. 6, virtual hierarchic structure 610
Height increases along the center position far from semiconductor structure 600.Stacked structure 620 is conformally formed in virtual hierarchic structure 610
On.Stacked structure 620 includes the grid layer 620a and dielectric layer 620b being alternately stacked.At least partially formation of grid layer 620a
There is conductive contact 630.Contact portion 640 has been correspondingly formed on conductive contact 630.Stacked structure 620 is located at folded on N grades of steps
Layer number is different with the lamination quantity on N+1 grades of steps, and N is the integer more than or equal to 1.Lamination quantity on step refers to
The number of complete lamination.In Fig. 6, the height of virtual hierarchic structure 610 increases along the center position far from semiconductor structure 600
Add, stacked structure 620 is located at the lamination quantity that the lamination quantity on N grades of steps is greater than on N+1 grades of steps.It is appreciated that
Accordingly, if the height of virtual hierarchic structure 610 is reduced along the center position far from semiconductor structure 600, stacked structure 420
It is greater than the lamination quantity on N+1 grades of steps in the lamination quantity on N grades of steps.
In some embodiments of the invention, conductive contact 630 can be identical with the material of grid layer 620a, such as is all
Tungsten.In some embodiments of the invention, the thickness with a thickness of single-layer medium layer 620b of conductive contact 630.Of the invention
In some embodiments, the thickness of conductive contact 630 is greater than the thickness of single-layer medium layer 620b.In some embodiments of the present invention
In, peripheral components 650 are formed with below virtual hierarchic structure 610.In some embodiments of the invention, semiconductor structure 600
It further include extending upward through the virtual channel hole 660 of virtual hierarchic structure 610 and stacked structure 620 in diagram Vertical Square, for half
Conductor structure 600 provides support.It is appreciated that there is no separate grid layer 620a completely in virtual channel hole 660.Virtual channel
Hole 660 is only the cavernous structure through grid layer 620a portion cross-sectional area, and control signal can still pass through grid layer
620a is transmitted to core space.
The other details of the present embodiment can refer to production method above, not reinflated herein.
The present invention provides a kind of production method of three-dimensional storage, the semiconductor structure provided includes virtual hierarchic structure
And stacked structure, there is on stacked structure preformed conductive contact, the thickness of grid layer in stacked structure can be increased, by
Increase in the thickness of grid layer, it is not easy to be worn by erosion, therefore the risk that etching break-through occurs is greatly lowered.
Although the present invention is described with reference to current specific embodiment, those of ordinary skill in the art
It should be appreciated that above embodiment is intended merely to illustrate the present invention, can also make in the case where no disengaging spirit of that invention
Various equivalent change or replacement out, therefore, as long as to the variation of above-described embodiment, change in spirit of the invention
Type will all be fallen in the range of following claims.
Claims (14)
1. a kind of production method of three-dimensional storage, comprising the following steps:
Semiconductor structure is provided, the semiconductor structure includes virtual hierarchic structure and stacked structure, the virtual hierarchic structure
Including multi-stage stairs, every grade of step has different height, and the stacked structure is conformally formed in the virtual ladder
In structure, the stacked structure includes the multiple first material layers and multiple second material layers being alternately stacked；
It removes at least partly stacked structure and forms exposed contact surface in the multiple first material layer；Wherein, it removes extremely
After small part stacked structure, the stacked structure is located at lamination quantity and the N+1 grades of steps on the N grades of steps
On lamination quantity it is different, N is the integer more than or equal to 1；
It is formed respectively through multiple conductive contacts of the contact the multiple first material layer of face contact；
Insulating layer is covered on the stacked structure；
It is formed on the insulating layer the multiple contact portions extended through to the multiple conductive contact.
2. the method according to claim 1, wherein the height of the virtual hierarchic structure is partly led along far from described
The center position of body structure increases, and the stacked structure is located at the lamination quantity on the N grades of steps and is greater than N+1 grades of institutes
State the lamination quantity on step.
3. the method according to claim 1, wherein the first material layer be dummy gate layer or dummy gate layer,
The second material layer is dielectric layer.
4. the method according to claim 1, wherein the conductive contact is identical as the material of the grid layer.
5. the method according to claim 1, wherein the contact surface be the first material layer upper surface,
The thickness with a thickness of second material layer described in single layer of the conductive contact.
6. the method according to claim 1, wherein the contact surface is that the first material layer is removed at least
The medial surface that a part of thickness is formed, the thickness of the conductive contact are greater than the thickness of second material layer described in single layer.
7. the method according to claim 1, wherein the method for forming the virtual hierarchic structure is to cut down etching
Method.
8. the method according to claim 1, wherein removal at least partly stacked structure and the multiple first
The step of exposed contact surface is formed in material layer include:
The part of the surface of removal at least partly stacked structure and the multiple second material layer of exposure；And
It removes at least partly second material layer at the part of the surface and exposes the contact surface in the first material layer.
9. according to the method described in claim 8, it is characterized in that, removal at least partly stacked structure and exposure the multiple the
The method of the part of the surface of two material layers is to cut down etching method, and the direction for cutting down etching is towards in the semiconductor structure
Heart direction.
10. according to the method described in claim 8, it is characterized in that, removing at least partly the second material at the part of the surface
The bed of material and the contact surface step in the exposure first material layer includes: to cover photoresist on the dielectric layer being exposed
And dry etching is carried out to the photoresist.
11. according to the method described in claim 10, it is characterized in that, the dry etching can be single layer dry etching.
12. the method according to claim 1, wherein being formed the multiple by the contact face contact respectively
The step of multiple conductive contacts of first material layer includes: to be covered described in conductive contact and removal in the first material layer
Conductive contact in second material layer.
13. being through to the conductive touching the method according to claim 1, wherein being formed on the insulating layer
After the contact portion of point further include: remove the dummy gate layer and form gap between the dielectric layer and in the gap
Middle formation grid layer.
14. the method according to claim 1, wherein further including outside being formed below the virtual hierarchic structure
Peripheral device.
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| US20160172296A1 (en) * | 2014-12-10 | 2016-06-16 | Tae-Wan Lim | Semiconductor device and method for manufacturing the same |
| CN108461503A (en) * | 2018-04-25 | 2018-08-28 | 长江存储科技有限责任公司 | The manufacturing method of three-dimensional storage and the method for forming crystal silicon layer |
| CN108493192A (en) * | 2018-06-04 | 2018-09-04 | 长江存储科技有限责任公司 | Three-dimensional storage and its manufacturing method |
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| US20160172296A1 (en) * | 2014-12-10 | 2016-06-16 | Tae-Wan Lim | Semiconductor device and method for manufacturing the same |
| CN108461503A (en) * | 2018-04-25 | 2018-08-28 | 长江存储科技有限责任公司 | The manufacturing method of three-dimensional storage and the method for forming crystal silicon layer |
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