CN109215590B - Power control system and display - Google Patents
Power control system and display Download PDFInfo
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- CN109215590B CN109215590B CN201811038429.4A CN201811038429A CN109215590B CN 109215590 B CN109215590 B CN 109215590B CN 201811038429 A CN201811038429 A CN 201811038429A CN 109215590 B CN109215590 B CN 109215590B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
Abstract
The application provides a power control system, includes: the system comprises a power management module, a code memory, a logic board and an I2C bus, wherein the code memory is connected with the logic board, and the power management module is connected with the logic board through the I2C bus; the power management integrated circuit comprises a power management unit and a monitoring unit, wherein the power management unit and the monitoring unit are arranged in the power management integrated circuit, the monitoring unit is used for acquiring cyclic redundancy check data in the power management unit to detect whether the power management unit is in an abnormal state or not, and the logic board downloads configuration information of the power management unit from the code memory and uploads the configuration information to the power management unit through an I2C bus; when the power management unit has abnormal state, the debugged configuration information is obtained from the logic board through the I2C bus. The monitoring unit is arranged inside the power management module, so that the I2C bus is almost in the idle state of the logic board in the working phase of the whole system, and the control right of the I2C bus can be effectively released by the logic board.
Description
Technical Field
The application relates to the field of liquid crystal display, in particular to a power supply control system and a display.
Background
With the technical development and progress of the lcd tv panel and the more intense market competition, the integration level of the driving circuit is higher and higher to achieve further cost optimization. The power management chip is applied to a power management chip of a non-GOA framework and a power management chip of a programmable gamma buffer unit, and the power management chip is applied to a power management chip of a GOA framework, a power management chip of a programmable gamma buffer unit and a power management chip of a level conversion three-in-one framework, and in order to achieve effective utilization of a nonvolatile storage device, the power management chip is not integrated with the nonvolatile storage device any more, configuration information of the power management chip is stored in a code memory outside a logic board, the configuration information of the power management chip is downloaded through the logic board after power-on, and is uploaded to the power management chip through an I2C bus, so that the power management chip enters a normal working state. However, based on the consideration of the safety and stability of the configuration information of the power management chip, the power management chip calculates and updates the redundancy check data of the internal configuration information in real time, and the logic board reads back the redundancy check data in real time through the I2C bus to compare the data to determine whether the operating state of the power management chip is normal. The I2C bus is only used to control the power management chip, and if the external chip needs to perform debugging operations such as reading and writing operations on the logic board or the power management chip, the external chip needs to notify the logic board to release the I2C bus control right through an additional GPI pin (e.g., low- > high).
Therefore, the prior art has defects and needs to be improved urgently.
Disclosure of Invention
The purpose of the application is to provide a power control system and a display, which can facilitate other control chips to debug the power management module or send instructions to a logic board through an I2C bus, so as to realize specific functions.
An embodiment of the present application provides a power control system, including: the power management module comprises a power management module, a code memory, a logic board and an I2C bus, wherein the code memory is connected with the logic board, and the power management module is connected with the logic board through the I2C bus;
the power management module comprises a power management unit and a monitoring unit, wherein the power management unit and the monitoring unit are arranged in the power management module, the monitoring unit is used for acquiring cyclic redundancy check data in the power management unit to detect whether the power management unit is in an abnormal state, and the logic board downloads configuration information of the power management unit from the code memory and uploads the configuration information to the power management unit through the I2C bus; when the power management unit is abnormal, the debugged configuration information is acquired from the logic board through the I2C bus.
In the power control system of the present application, the power management module further includes a programmable gamma buffer unit, and the programmable gamma buffer unit is connected to the power management unit.
In the power control system of the present application, the power management module further includes a level conversion unit, and the level conversion unit is connected to the power management unit.
In the power control system of the present application, during a power-on phase, the I2C bus is in a logic board occupied state, and the power management unit obtains the configuration information from the logic board through the I2C bus; in the working phase, the I2C bus is in a logic board idle state.
In this application power control system in, work as in the working phase the monitor cell monitors when power management unit configuration information is unusual, I2C bus switches into the logic board occupation state from logic board idle state to last first predetermined duration T1, just first predetermined duration includes the second duration T2 that the logic board effectively occupies and the not effective safe redundant duration T3 that occupies of logic board.
In this application power control system in, the power management unit has a state pin GPO, works as the monitor cell is monitored when the power management unit is unusual, state pin GPO is the high level, works as the monitor cell is monitored when the power management unit does not have the abnormality, state pin GPO is the low level.
In the power control system of the present application, the status pin GPO is connected to the logic board unit; when the logic board unit detects that the status pin GPO is at a high level, the status of the I2C bus is switched from a logic board idle status to a logic board occupied status, and the configuration information is uploaded again through the I2C bus.
In the power control system described in the present application, the code memory is a read only memory.
In the power control system described herein, the code memory is a non-volatile memory.
The embodiment of the application also provides a display which comprises the power supply control system.
According to the method, the monitoring unit is arranged in the power management module, so that the I2C bus is almost in an idle state of the logic board in the working stage of the whole system, and the control right of the I2C bus can be effectively released by the logic board; the other control chips are further convenient to debug the power management module or send instructions to the logic board through the I2C bus so as to realize specific functions.
Drawings
Fig. 1 is a schematic structural diagram of a power supply control system in an embodiment of the present application.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative and are only for the purpose of explaining the present application and are not to be construed as limiting the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a power control system in an embodiment of the present application. The power control system includes: the power management module comprises a power management module 10, a code memory 30, a logic board 20 and an I2C bus 40, wherein the code memory 30 is connected with the logic board 20, and the power management module 10 is connected with the logic board 20 through the I2C bus 40.
The power management module 10 includes a power management unit 11 and a monitoring unit 12 disposed therein, where the monitoring unit 12 is configured to obtain cyclic redundancy check data in the power management unit 11 to detect whether the power management unit 12 is in an abnormal state, and the logic board 20 downloads configuration information of the power management unit 11 from the code memory 30 and uploads the configuration information to the power management unit 11 through the I2C bus 40; when the power management unit 11 has an abnormal status, the debugged configuration information is acquired from the logic board 20 through the I2C bus 40.
Specifically, the power management module 10 is an integrated circuit, which employs a power management chip of a two-in-one architecture of power management and programmable gamma buffer in the prior art, and a monitoring unit is further provided to monitor a state of the power management chip. The power management module 10 specifically includes: programmable gamma buffer unit 14, power management unit 11, and monitoring unit 12. In some embodiments, the Power management module 10 of Power + P-Gamma + Level Shifter for GOA architecture is an integrated circuit that employs PMIC for Power management, programmable Gamma buffering, and Level shifting for GOA architecture. The power management module 10 specifically includes: programmable gamma buffer unit 14, level conversion unit 13, power management unit 11, and monitoring unit 12. The programmable gamma buffer unit 14 is connected to the power management unit 11. The level conversion unit 13 is connected to the power management unit 11.
In actual operation, when the power control system is in a power-on stage, the I2C bus 40 is in an occupied state on the logic board 20, and the power management unit obtains the configuration information from the logic board 20 through the I2C bus 40; in the operational phase, the I2C bus 40 is in the logic board 20 idle state.
Of course, in the working phase, when the monitoring unit monitors that the configuration information of the power management unit is abnormal, the I2C bus 40 is switched from the idle state of the logic board 20 to the occupied state of the logic board 20 and lasts for a first preset duration T1, and the first preset duration includes a second duration T2 that the logic board 20 is effectively occupied and a safety redundancy duration T3 that the logic board 20 is not effectively occupied.
Specifically, the power management unit 11 has a status pin GPO, and when the monitoring unit 12 monitors that the power management unit 11 is abnormal, the status pin GPO is at a high level, and when the monitoring unit 12 monitors that the power management unit 11 is not abnormal, the status pin GPO is at a low level.
The status pin GPO is connected to the logic board 20 unit; when the logic board 20 unit detects that the status pin GPO is at a high level, the state of the I2C bus 40 is switched from the idle state of the logic board 20 to the occupied state of the logic board 20, and the configuration information is uploaded again through the I2C bus 40.
The code memory 30 is a read only memory ROM or a nonvolatile memory.
In the working phase of the whole system, the I2C bus 40 is almost in a logic board idle state, so that the logic board can effectively release the I2C bus control right; it is further convenient for other control chips to debug the power management module or send instructions to the logic board through the I2C bus to implement specific functions.
The present application also provides a display including the power control system in any of the above embodiments.
In the description herein, references to the description of the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In summary, although the present application has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, so that the scope of the present application shall be determined by the appended claims.
Claims (10)
1. A power control system, comprising: the power management module comprises a power management module, a code memory, a logic board and an I2C bus, wherein the code memory is connected with the logic board, and the power management module is connected with the logic board through the I2C bus;
the power management module comprises a power management unit and a monitoring unit, wherein the power management unit and the monitoring unit are arranged in the power management module, the monitoring unit is used for acquiring cyclic redundancy check data in the power management unit to detect whether the power management unit is in an abnormal state, and the logic board downloads configuration information of the power management unit from the code memory and uploads the configuration information to the power management unit through the I2C bus; when the power management unit is abnormal, the debugged configuration information is acquired from the logic board through the I2C bus.
2. The power control system of claim 1, wherein the power management module further comprises a programmable gamma buffer unit, the programmable gamma buffer unit being coupled to the power management unit.
3. The power control system of claim 1, wherein the power management module further comprises a level shifting unit, the level shifting unit being connected to the power management unit.
4. The power control system of claim 1, wherein during power-up phase, the I2C bus is in a logic board occupied state, and the power management unit obtains the configuration information from the logic board via the I2C bus; in the working phase, the I2C bus is in a logic board idle state.
5. The power control system according to claim 4, wherein in the working phase, when the monitoring unit monitors that the configuration information of the power management unit is abnormal, the I2C bus is switched from the logic board idle state to the logic board occupied state for a first preset duration T1, and the first preset duration comprises a second duration T2 when the logic board is effectively occupied and a safety redundancy duration T3 when the logic board is not effectively occupied.
6. The power control system of claim 5, wherein the power management unit has a status pin GPO, and wherein the status pin GPO is high when the monitoring unit detects the power management unit is abnormal, and the status pin GPO is low when the monitoring unit detects the power management unit is not abnormal.
7. The power control system of claim 6, wherein the status pin GPO is connected to the logic board; when the logic board detects that the status pin GPO is at a high level, the status of the I2C bus is switched from a logic board idle status to a logic board occupied status, and the configuration information is re-uploaded through the I2C bus.
8. The power control system of claim 1, wherein the code memory is a read-only memory.
9. The power control system of claim 1, wherein the code memory is a non-volatile memory.
10. A display comprising the power control system of any one of claims 1-9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811038429.4A CN109215590B (en) | 2018-09-06 | 2018-09-06 | Power control system and display |
| PCT/CN2018/113285 WO2020047980A1 (en) | 2018-09-06 | 2018-11-01 | Power supply control system, and display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201811038429.4A CN109215590B (en) | 2018-09-06 | 2018-09-06 | Power control system and display |
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| CN109215590A CN109215590A (en) | 2019-01-15 |
| CN109215590B true CN109215590B (en) | 2020-09-01 |
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| CN201811038429.4A Active CN109215590B (en) | 2018-09-06 | 2018-09-06 | Power control system and display |
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| WO (1) | WO2020047980A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110767188B (en) * | 2019-10-12 | 2022-05-31 | Tcl华星光电技术有限公司 | Display panel driving system |
| CN111443888B (en) * | 2020-03-27 | 2024-03-22 | Tcl华星光电技术有限公司 | Display control method, display control device, electronic equipment and storage medium |
| CN115396255A (en) * | 2022-08-31 | 2022-11-25 | 哲库科技(北京)有限公司 | Power supply control method, control chip, power supply management chip and electronic equipment |
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| CN104409059A (en) * | 2014-11-21 | 2015-03-11 | 中航华东光电有限公司 | Driving circuit, display and driving method thereof |
| CN105185324A (en) * | 2015-07-24 | 2015-12-23 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and device |
| CN107544018A (en) * | 2017-07-21 | 2018-01-05 | 芯海科技（深圳）股份有限公司 | A kind of more site semaphores detections and fail-ure criterion system and method |
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| US7392411B2 (en) * | 2003-04-25 | 2008-06-24 | Ati Technologies, Inc. | Systems and methods for dynamic voltage scaling of communication bus to provide bandwidth based on whether an application is active |
| US8433936B2 (en) * | 2008-04-04 | 2013-04-30 | Advanced Micro Devices, Inc. | USB power conservation method and apparatus |
| CN105045366B (en) * | 2015-07-01 | 2019-01-15 | 湖南汽车工程职业学院 | A kind of more device for managing and controlling electrical source of processor, system and method |
| CN105468123A (en) * | 2015-11-18 | 2016-04-06 | 浪潮电子信息产业股份有限公司 | Rack management controller, power management program update system and method |
| KR102562645B1 (en) * | 2016-05-20 | 2023-08-02 | 삼성전자주식회사 | Operating Method for display corresponding to luminance, driving circuit, and electronic device supporting the same |
| CN106384580A (en) * | 2016-09-14 | 2017-02-08 | 深圳市视显光电技术有限公司 | Gamma automatic correction device and method for LCD logic board |
| CN108198536B (en) * | 2017-12-29 | 2020-06-09 | 深圳市华星光电技术有限公司 | Voltage calibration method and system based on time schedule controller |
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- 2018-11-01 WO PCT/CN2018/113285 patent/WO2020047980A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104409059A (en) * | 2014-11-21 | 2015-03-11 | 中航华东光电有限公司 | Driving circuit, display and driving method thereof |
| CN105185324A (en) * | 2015-07-24 | 2015-12-23 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and device |
| CN107544018A (en) * | 2017-07-21 | 2018-01-05 | 芯海科技（深圳）股份有限公司 | A kind of more site semaphores detections and fail-ure criterion system and method |
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| CN109215590A (en) | 2019-01-15 |
| WO2020047980A1 (en) | 2020-03-12 |
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