CN1091952C

CN1091952C - Semiconductor device and production method therefor

Info

Publication number: CN1091952C
Application number: CN95197819A
Authority: CN
Inventors: 平田宏治; 田上知纪; 增田宏; 内山博幸; 望月和浩
Original assignee: Hitachi Super - Ireland - Love Ace Engineering Ltd By Share Ltd; Hitachi Ltd
Current assignee: Hitachi Super - Ireland - Love Ace Engineering Ltd By Share Ltd; Hitachi Ltd
Priority date: 1995-03-17
Filing date: 1995-03-17
Publication date: 2002-10-02
Anticipated expiration: 2015-03-17
Also published as: CN1181844A

Abstract

The present invention relates to a contact structure. The contact structure not only is suitable for heterojunction bipolar transistors or heterogeneity insulated gate field effect transistors, but also is suitable for common semiconductor devices. A contact through hole is formed in a polycrystal or non-crystal semiconductor layer which is not doped with compounds of the III family to the V family or alloy thereof, and at least part of the contact through hole is allowed to be exposed out of a first conducting layer and an insulating Si alloy layer around the first conducting layer. A second conducting layer is formed in the through hole, and is in contact with the first conducting layer. The semiconductor layer is corroded by a selective drying method correspondingly to the insulating Si alloy layer. When the through hole is formed in the semiconductor layer, the insulating Si alloy layer can not be corroded, so that the electrical short between the second conducting layer and the single crystal semiconductor layer under the insulating Si alloy layer can be avoided.

Description

Semiconductor device and manufacture method thereof

The present invention relates generally to comprise the semiconductor device and the manufacture method thereof of bipolar transistor and field-effect transistor.

Use the common heterojunction bipolar transistor of III-V compound semiconductor to have description, for example, at National Technical Report Vol.39 No.6 (Dec.1993), among the pp.729-735 (first prior art).Its cross-section structure is illustrated among Fig. 2 (a).On GaAs substrate 1, form the auxiliary collector layer 2 of heavily doped n-type GaAs, n-type GaAs collector layer 3, heavily doped p-type GaAs base layer 4, n-type AlGaAs emitter layer 5, be used to form the heavy doping n-type InGaAs cover layer 6 of ohmic contact, and heavy doping n-type InGaAs layer 7.Form emitter electrode 8, base electrode 10 and collector electrode 16 respectively at exposed emitter region, base and auxiliary collecting region.The high resistance area that identification number 38 expressions adopt protonation to form.According to this device architecture, the emitter electrode area greater than 39 that form by the SiN layer, be used for the emitter region contact hole area that links to each other with the metal 20 that goes between.

At IEEE Electron Device Letters EDL-8 (1987), another example (second prior art) that uses the heterojunction bipolar transistor of III-V compound semiconductor has been described among the pp.246-248.Its cross-section structure is shown in Fig. 2 (b).The heavy doping n-type GaAs cover layer 6 that on GaAs substrate 1, forms the auxiliary collector layer 2 of heavily doped n-type GaAs, n-type GaAs collector layer 3, heavily doped p-type GaAs base layer 4, unadulterated GaAs base stage wall 4, n-type AlGaAs emitter layer 5 and be used to form ohmic contact.Form emitter electrode 8, base electrode 10 and collector electrode 16 respectively at exposed emitter region, base and auxiliary collecting region.Identification number 9 expression SiO ₂Side wall, the high resistance area that identification number 38 expressions become with protonation, identification number 40 expression SiO ₂Film.In this device, the neighboring of base 4 and collecting region 3 mesa region is identical with the neighboring structure of base electrode 10.

In addition, for example, in the open No.283433/93 of Japan Patent, introduced conventional heterogeneous-isolated-gate field effect transistor (IGFET) (the 3rd prior art).Heterogeneous-isolated-gate field effect transistor (IGFET) shows a kind of grid field effect transistor structure that accompanies its bandwidth of one deck greater than channel layer between raceway groove and schottky gate electrode.Its cross-section structure is shown in Fig. 9.In this drawing, identification number 26 expression monocrystalline semiconductor substrates, identification number 31 expression heavy doping n-type GaAs, identification number 28 expressions contain n-type GaAs, not the doped with Al GaAs layer and the channel layer of Doped GaAs layer not, and identification number 24 expression SiO ₂Insulating barrier between the layer.In this device, that low metal 37 is stacking on the gate electrode 29 that is formed by WSi, to reduce gate resistance.

In order to obtain the high speed heterojunction bipolar transistor, will reduce base resistance emitter region-base electric capacity and base-collecting region electric capacity effectively.Every kind of electric capacity increases with junction area with being directly proportional.For reducing electric capacity, it is effectively reducing size of each figure such as emitter region itself and the spacing between the shortening adjacent pattern.

Yet, in above-mentioned first prior art, do forr a short time than the area of emitter electrode contact hole if find the area of emitter electrode 8, base electrode 10 can expose because of corrosion when forming the emitter contact hole, and can cause short circuit between emitter and the base stage by lead-in wire metal 20.So device size reduces emitter region-base and base-collecting region parasitic capacitance is restricted by reducing.

In above-mentioned second prior art, do hour if find the neighboring of base 4 and collecting region 3 mesa region, then the base electrode area also require to do little, so cause the increase of base electrode resistance.

In the 3rd prior art on relevant, find corroding SiO for exposing gate electrode 29 ₂During insulating barrier 24 between the layer, the corroding excessively and arrive the source region and the drain region of insulating barrier 24, thereby when formation low resistance metal layer 37 on gate electrode 29, source or drain region and gate electrode 29 are by short circuit.

First target of the present invention is the short circuit problem that solves general semiconductor device under the above-mentioned condition, and is not limited to contain the semiconductor device of heterojunction bipolar transistor and heterogeneous-isolated-gate field effect transistor (IGFET).More particularly, first target of the present invention provides the semiconductor device that a kind of its structure comprises first conductive layer and second conductive layer, in single-crystal semiconductor layer, form first conductive layer, each side at first conductive layer forms first insulating barrier, and second conductive layer that forms and contact with it on the first insulation Si alloy-layer around first conductive layer.Attempt to avoid the electrical short between second conductive layer and the single-crystal semiconductor layer therefrom.

Second target of the present invention is to reduce the area of base mesa region in the heterojunction bipolar transistor semiconductor device and do not increase base electrode resistance.

Above-mentioned first target can be by forming polycrystalline or the unadulterated III-V compound semiconductor of amorphous or its alloy, opening through hole a to small part and expose first conductive layer and be positioned at first insulating barrier around first conductive layer, form second conductive layer at through hole then and realize on first insulating barrier.

First target also can realize by a kind of method, semi-conductor device manufacturing method, is included in and forms first conductive layer on the single-crystal semiconductor layer; Form first insulating barrier and the upper surface of first conductive layer is exposed in each side of first conductive layer; On first insulating barrier and first conductive layer, form polycrystalline or amorphous not doped with II I-V compound semiconductor or its alloy first semiconductor layer and form second insulating barrier successively; In second insulating barrier, form first through hole of through first semiconductor layer according to the selection type dry corrosion method of relative first semiconductor layer with reacting gas; Make etch mask with reacting gas and with second insulating barrier with first through hole, selection type dry corrosion method according to relative first conductive layer and first insulating barrier forms second through hole in first semiconductor layer, this through hole reaches part first conductive layer and first insulating barrier around first conductive layer at least; And in the through hole that constitutes by first and second through holes, form second conductive layer, make it to contact with first conductive layer.

Aforementioned second target of the present invention can realize with a kind of semiconductor device with bipolar transistor structure, wherein auxiliary collecting region, collecting region and emitter region stack gradually, collecting region and base are less than auxiliary collecting region, the emitter region is less than collecting region and base, also have at auxiliary collecting region, form and have the insulating barrier of through hole on collecting region and the base in the base, the base lead-out wire semiconductor layer that conduction type is identical with the base (formation of this base lead-out wire semiconductor layer will contact with the base in the insulating barrier through hole), and form the base electrode contact and extend to insulating barrier with base lead-out wire semiconductor layer.

Polycrystalline or amorphous not first semiconductor layer (it is introduced for realizing aforementioned first target) of doped with II I-V compound semiconductor or its alloy may stand once selectivity dry etching between it and first insulating barrier, therefore, when forming through hole in first semiconductor layer, first insulating barrier can not be corroded.So, might avoid the electrical short between second conductive layer and the single-crystal semiconductor layer.

By introducing second insulating barrier, may lead capacitance be reduced from structure, and the viewpoint from making can make the shoulder height on the device surface reduce, thereby form lead-in wire easily.

First semiconductor layer becomes polycrystalline or amorphous layer or its alloy-layer, depends on this layer formation temperature.Formation temperature amorphous, mixed crystal and polycrystal occur from low to high successively.Also may form first semiconductor layer in zubzero temperature.Layer formation temperature is low more, and the resistivity of first semiconductor layer is high more.From this viewpoint, it is desirable that layer at low temperatures forms.Yet in low temperature formed, it is big that the water content of film becomes, thereby when considering film quality, this has just determined the lower limit of layer formation temperature.As for the upper limit of layer formation temperature, consider the deterioration of device property, wish about 400 ℃.

In addition, utilize the corrosion selectivity between polycrystalline or amorphous layer or IIII-V compound semiconductor or its alloy-layer and the insulation Si alloy-layer, may realize a kind of structure that on insulation Si alloy-layer, forms semiconductor layer with very high controllability with through hole.

Have under base electrode the area that the structure (it is introduced for realizing second target) that forms insulating barrier allows to reduce the base table top and do not increase base electrode resistance,, and do not require and reduce the base electrode area even because do hour when the base table top.In addition, also might reduce base-collecting region electric capacity.

Fig. 1 is the heterojunction bipolar transistor section of structure of example 1 of the present invention;

Fig. 2 (a) and 2 (b) are common heterojunction bipolar transistor section of structures;

Fig. 3 is the process drawing of the heterojunction bipolar transistor of example 1;

Fig. 4 is the heterojunction bipolar transistor process drawing of example 2 of the present invention;

Fig. 5 is the heterojunction bipolar transistor process drawing of example 3 of the present invention;

Fig. 6 is the heterojunction bipolar transistor process drawing of example 4 of the present invention;

Fig. 7 is example 5 differentiating amplifier circuit diagrams of the present invention;

Fig. 8 is the circuit arrangement map of example 5 differentiating amplifiers;

Fig. 9 is common heterojunction isolated-gate field effect transistor (IGFET) section of structure;

Figure 10 is the heterojunction isolated-gate field effect transistor (IGFET) process drawing of example 6 of the present invention;

Figure 11 is the circuit diagram of the static ram cell of example 7 of the present invention;

Figure 12 is the circuit diagram of the dynamic random memory cell of example 8 of the present invention.

Making example below by it goes through the present invention.Example 1

Below with reference to Fig. 1 and Fig. 3 AlGaAs/GaAs heterojunction bipolar transistor in the example 1 of the present invention is described.In this example, form the unadulterated GaAs layer 15 of amorphous state in the insulating interlayer zone.

At first, on GaAs (100) substrate 1 the secondary collector layer 2 of epitaxial growth heavy doping n type GaAs (concentration is 5 * 10 ¹⁸/ cm ³Si, thick 500nm), (concentration is 5 * 10 to n type GaAs collector layer 3 ¹⁶/ cm ³Silicon, thick 150nm), (concentration is 4 * 10 to heavy doping p type GaAs base layer 4 ¹⁹/ cm ³Carbon, thick 50nm), (AlAs Mo Er ratio is 0.3 to n type AlGaAs emitter layer 5, and concentration is 1 * 10 ¹⁸/ cm ³Silicon, thick 50nm), (concentration is 5 * 10 to be used to form the heavy doping n type GaAs cover layer 6 of emitter region ohmic contact ¹⁸/ cm ³Silicon, thick 150nm) and heavy doping n type InGaAs cover layer 7 (concentration is 5 * 10 ¹⁸/ cm ³Silicon, thick 50nm).Subsequently, the tungsten W of deposit 600nm, and form the wide tungsten emitter electrode 8 of 0.3 μ m by phase-shift mask photoetching and fluoro-gas ECR dry etching.Then, be mask with emitter electrode 8, (gas compares Cl to adopt the ECR method ₂/ CH ₄=7/3sccm, corrosion pressure 36mPa, microwave power 700W, radio-frequency power 50W, 25 ℃ of underlayer temperatures) InGaAs overcoat 7, GaAs overcoat 6 and emitter layer 5 are carried out isotropic etch, so that base 4 is come out.(Fig. 3 (a))

Then, by deposit SiO ₂Form SiO with dry etching ₂Side wall 9 (the long 0.1 μ m of side wall).Then, adopt and directly to evaporate successively deposit Pt, Ti, Mo, Ti, Pt and Au as the material 300nm of base electrode 10, deposit SiO again ₂ Film 11, resist coating 12a and complanation.(Fig. 3 (b))

After this, to photoresist 12a and SiO ₂Film 11 corrodes to expose the material film of the base electrode 10 that forms on emitter electrode 8.(Fig. 3 (c))

Next, (comprise and be deposited on SiO by the material film of ion etching the base electrode 10 that is exposed ₂Subregion on side wall 9 sides) erodes.(Fig. 3 (d))

Then, by deposit SiO ₂Form SiO with the dry etching that adopts mask lithography glue ₂Film pattern 13.Again with SiO ₂ Film pattern 13 is made mask, and base electrode 10, base 4 and collecting region 3 are carried out ion etching and expose auxiliary collecting region 2.(Fig. 3 (e))

Then, by deposit SiO ₂Form the SiO that covers the base electrode 10 that exposes with dry etching ₂Side wall 14.Then, in molecular beam epitaxy system, the thick not Doped GaAs of deposit 50nm under 120 ℃ substrate heating temperature.The crystal structure of this generation layer 15 is amorphous states.(Fig. 3 (f))

Next, auxiliary collecting region 2 is carried out dry etching, so that isolate mutually between device.Then, form AuGe collector electrode 16 by the lift-off method.

After this, deposit SiO in succession ₂Film 17,18 and 19 is to form insulating interlayer zone, wherein SiO ₂Film 18 is used for attenuate shoulder height and form with coating process.SiO ₂

Film

17,19 is used for preventing that aqueous vapor from entering SiO ₂Film 18.Then, make in order to form the photoresist mask 12b of emitter electrode contact hole.(Fig. 3 (g))

Then, adopt HF and H ₂O hybrid corrosion liquid is to SiO ₂Film 19 carries out isotropic etch.Then, by adopting C ₂F ₂And CHE ₃The RIE method of gas is to SiO ₂The SiO of film 19, coating ₂Film 18 and SiO ₂Film 17 carries out optionally isotropism dry etching, reaches unadulterated GaAs layer 15.(Fig. 3 (h))

Below, by adopting SiCl ₄The RIE method of gas is carried out optionally isotropism dry etching to unadulterated GaAs layer 15, reaches SiO ₂ Film 14 and emitter electrode 8 are to expose the upper surface of emitter electrode 8.Fig. 3 (i))

Equally, behind the formation contact hole, also deposit lead-in wire metal 20 on base electrode 10 and collector electrode 16 then, forms lead-in wire by etching and is made into heterojunction bipolar transistor.(Fig. 1)

According to this example, may produce emitter region wide with high rate of finished products be the heterojunction bipolar transistor of 0.3 μ m.Therefore, with the emitter region live width is that the device of 1 μ m is compared, emitter-base stage parasitic capacitance can be reduced to about 1/3rd, and that base stage-collector parasitic capacitance can be reduced to is about 2/3rds, so that and might produce the ultrahigh speed heterojunction bipolar transistor that maximum frequency of oscillation is 1.2 times of conventional devices.Example 2

Referring now to Fig. 4 AlGaAs/GaAs heterojunction bipolar transistor in the example 2 of the present invention is described.In this example, form amorphous state undoped layer 15 in the dielectric interlayer district.Between base layer and base electrode, form the increase that heavy doping P type GaAs layer 23 is used for suppressing the electrode contact resistance, form SiO in the additional collection district in collecting region ₂Layer 22 is used for reducing base stage-collector electric capacity.

At first, (concentration is 5 * 10 at the secondary collector layer 2 of GaAs (100) substrate 1 epitaxial growth heavy doping n type GaAs ¹⁸/ cm ³Si, thick 500nm), (concentration is 5 * 10 to n type GaAs collector layer 3 ¹⁶/ cm ³Silicon, thick 150nm), (concentration is 4 * 10 to heavy doping p type GaAs base layer 4 ¹⁹/ cm ³Carbon, thick 50nm), (AlAs Mo Er ratio is 0.3 to n type AlGaAs emitter layer 5, and concentration is 1 * 10 ¹⁸/ cm ³Silicon, thick 50nm), (concentration is 5 * 10 to be used to form the n type GaAs overcoat 6 of emitter region ohmic contact ¹⁸/ cm ³Silicon, thick 150nm) and heavy doping n type InGaAs layer 7 (concentration is 5 * 10 ¹⁸/ cm ³Silicon, thick 50nm).Subsequently, the tungsten of deposit 600nm, and form the tungsten emitter electrode 8 of wide 0.3 μ m by phase-shift mask photoetching and fluoro-gas ECR dry etching.Then, be mask with emitter electrode 8, (gas compares Cl to adopt the ECR method ₂/ CH ₄=7/3sccm, corrosion pressure 36mPa, microwave power 700W, radio-frequency power 50W, 25 ℃ of underlayer temperatures) InGaAs overcoat 7, GaAs overcoat 6 and emitter layer 5 are carried out isotropic etch, to expose base 4.(Fig. 4 (a))

Then, form SiN side wall 21 (the long 0.5 μ m of side wall) by deposit SiN and dry etching.Then, making mask with emitter electrode 8 and side wall 21 isotropically carries out the ECR dry etching and exposes auxiliary collecting region 2 base region 4 and collecting region 3.After this, deposit forms SiO ₂ Film 22 then applies photoresist 12c and complanation.(Fig. 4 (b))

After this, to photoresist 12c and SiO ₂Film 22 corrodes, up to SiO ₂ Film 22 thickness are 300nm.This moment, base layer 4 did not expose.(Fig. 4 (c))

Then, by the plasma etching system and adopt fluoro-gas corrosion SiN side wall 21 and expose base layer 4.After this, by deposit SiO ₂With dry etching in the

emitter region

5,6,7,8 and SiO ₂The side of film 22 forms SiO ₂Side wall 9.SiO ₂Side wall 9 length are 0.1 μ m, fully expose base layer 4.(Fig. 4 (d))

Then, substrate is incorporated in the metal-organic chemical vapor deposition system, (C concentration is 4 * 10 to the heavy doping P-GaAs layer 23 that makes it optionally to grow ²⁰/ cm ³, thickness 150nm).Then, by direct evaporation successively with Pt, Ti, Mo, Ti, Pt and Au deposition of materials 300nm, deposit SiO then as base electrode 10 ₂ Film 11, coating photoresist 12a and complanation.

After this, to photoresist 12a and SiO ₂Film 11 corrodes, to expose the material film that forms, be used as base electrode 10 on emitter electrode 8.Fig. 4 (e))

Then, (comprise and be deposited on SiO by the material film of ion etching the base electrode 10 of exposure ₂The part of the side of side wall 9) erodes.(Fig. 4 (f))

Then, by deposit SiO ₂With make the mask dry etching with photoresist and form SiO ₂Film pattern 13.Again with SiO ₂ Film pattern 13 is made mask, and base electrode 10 is carried out ion etching.(Fig. 4 (g))

After this, by deposit SiO ₂Form the SiO that covers exposure base electrode 10 with dry etching ₂Side wall 14.Then, substrate is incorporated in the molecular beam epitaxy system the thick not Doped GaAs of deposit 50nm under the room temperature that substrate does not heat.The crystal structure that generates layer 15 is an amorphous state.(Fig. 4 (h))

Next, auxiliary collecting region 2 is carried out dry etching to realize the isolation between the device, form AuGe collector electrode 16 with the lift-off method then.Follow deposit SiO ₂Film is to form the insulating interlayer zone.This SiO ₂Be used for the attenuate shoulder height, and form by coating process.This SiO ₂

Film

17 and 19 has been to prevent that aqueous vapor from entering SiO ₂The effect of film.Then, be constructed for forming the photoresist mask 12b of emitter electrode contact hole.(Fig. 4 (i))

Then, adopt HF and H ₂O hybrid corrosion liquid is to SiO ₂Film 19 carries out isotropic etch.Then, by adopting C ₂F ₂And CHE ₃The RIE method of gas is to SiO ₂Film 19, coating SiO ₂Film 18 and SiO ₂Film 17 carries out selectivity isotropism dry etching, reaches unadulterated GaAs layer 15.(Fig. 4 (j))

By adopting SiCl ₄The RCR method of gas is carried out selectivity isotropism dry etching to unadulterated GaAs layer 15, reaches SiO ₂ Film 14 and emitter electrode 8.(Fig. 4 (k))

Equally, form contact hole after, deposit lead-in wire metal 20 and be etched into lead-in wire and be made into heterojunction bipolar transistor on base electrode 10 and collector electrode 16.(Fig. 4 (l))

According to this example, forming C concentration at the base lead end is 4 * 10 ²⁰/ cm ³GaAs layer 23 to suppress the increase of base electrode contact resistance, in the additional collection district, form the SiO lower than inductance capacitance ₂Film 22 is to reduce base stage-collection junction area.Therefore, might produce the ultrahigh speed heterojunction bipolar transistor, compare with the structure of example 1, it is about 1/3rd that base stage-collector parasitic capacitance is reduced to, and the maximum frequency of oscillation ratio is brought up to about 1.7 times.And the amorphous state that forms in the insulating interlayer district not Doped GaAs floor 15 makes that this heterojunction bipolar transistor can be with high rate of finished products production, and the problem that emitter-base stage short circuit and metal lead wire puncture can not occur.Example 3

To 4 (k) and Fig. 5 AlGaAs/GaAs heterojunction bipolar transistor in the example 3 of the present invention is described referring now to Fig. 4 (a), 4 (e).In this example, in the additional collection district, form than inductance capacitance than the SiO that adopts in the example 2 ₂The polyimide resin film 25 that film 22 is lower.

The method of the manufacture method of this example and example 2 basic identical (Fig. 4), its difference are that Fig. 4 (b) is replaced to 5 (c) by Fig. 5 (a) to 4 (d).

At first, deposit SiO on the whole surface of structure shown in Fig. 4 (a) ₂, and form SiO with dry etching ₂Side wall 24 (the long 0.5 μ m of side wall).Then, use SiO ₂Side wall 24 and emitter electrode 8 are made mask, adopt the ECR method that base layer 4 and collector layer 3 are carried out the anisotropic dry corrosion to expose auxiliary collecting region 2.Then, polyimide resin is coated to whole surface flattens, obtain polyimide resin film 25 until the surface.(Fig. 5 (a.))

Then, it is thick polyimide resin film 25 to be eroded to 300nm.This moment, base layer 4 did not expose.(Fig. 5 (b))

Then, with HF and H ₂O hybrid corrosion liquid is with SiO ₂Side wall 24 erodes to expose base layer 4.After this, by deposit SiO ₂With dry etching in the

emitter region

5,6,7,8 and the side of polyimide resin film 25 form SiO ₂Side wall 9.SiO ₂Side wall 9 is that 0.1 μ m is long, and base 4 fully exposes.(Fig. 5 (c))

Then, by producing heterojunction bipolar transistor as the same step among Fig. 4 (e)-4 (k), its situation of finishing is shown in Fig. 5 (d).

According to this example, since in the additional collection district, form than inductance capacitance than SiO ₂The polyimide resin film 25 that film 22 is lower might produce the ultrahigh speed heterojunction bipolar transistor, with the structure of example 2 relatively, it is about 7/9ths that base stage-collector parasitic capacitance is reduced to, maximum frequency of oscillation is brought up to about 1.1 times.And the amorphous state that forms in the insulating interlayer district not Doped GaAs floor 15 makes that this heterojunction bipolar transistor can be with high rate of finished products production, and the problem that emitter-base stage short circuit and metal lead wire puncture can not occur.Example 4

Referring now to Fig. 4 (a), 4 (e) to 4 (k), 5 (a) to 5 (c) and 6 (a), 6 (b) the AlGaAs/GaAs heterojunction bipolar transistor in the example 4 of the present invention is described.

The feature of this example is: before the applying step of the polyimide resin film 25 shown in Fig. 5 (a) relevant with example 3, introduce from base electrode 10 and form the step that additional collection layers 2 are removed in the zone.More particularly, this embodiment is characterised in that the same procedure by example 3, forms SiO on the structure of Fig. 4 (a) ₂Side wall 24 (SiO ₂The long 0.5 μ m of side wall), base layer 4 and collector layer 3, partly form mask 12d against corrosion then and remove additional collection utmost point layer 2, allow substrate 1 expose.

Finish AlGaAs/GaAs heterojunction bipolar transistor shown in Fig. 6 (b) to the same step of 5 (c) and Fig. 4 (e) to the follow-up same step of 4 (k) by Fig. 5 (a).

Yet in this example, mutual isolation step is unnecessary between the device of Fig. 4 (i), because the removal of additional collection utmost point layer 2 has also played the internal components isolation step.

According to this example since than inductance capacitance than SiO ₂Film 22 lower polyimide resin films 25 not only form in the additional collection district, and in auxiliary collecting region, form, might produce the ultrahigh speed heterojunction bipolar transistor, compare with the structure of example 3, it is about 5/7ths that its base stage-collector parasitic capacitance reduces to, and maximum frequency of oscillation is brought up to about 1.2 times.And the amorphous state that forms in the insulating interlayer district not Doped GaAs floor 15 makes that this heterojunction bipolar transistor can be with high rate of finished products production, and emitter-base stage short circuit and metal lead wire breakdown problem can not occur.

Though Doped GaAs layer 15 is not in the formation of insulating interlayer zone for amorphous state in routine 1-example 4, it is amorphous state that same layer does not always require, and can be the mixture of polycrystalline or amorphous and polycrystalline material.And the layer of being discussed can be the polycrystalline or the amorphous compound semiconductor of other materials, as AlGaAs.

Although related in the example 4 in example 1 is manufacture method about the heterojunction bipolar transistor of AlGaAs/GaAs system, also can adopt other III-V compound semiconductors, for example GaAs/InGaAs and InP/InGaAs.In this case, the base structure can be utilized two-dimensional electron gas.As base impurity, C can replace with Be.The Mo Er of the AlAs of emitter region is than selecting arbitrarily in 0 to 1 scope.Though emitter region and collecting region are to make the n type, and the p type is made in the base, also the p type can be made in emitter region and collecting region, and the n type is made in the base.Though collecting region forms in substrate side, the emitter region forms above substrate, also can form the emitter region in substrate side, and form collecting region above substrate.Though that use in the additional collection district is SiO ₂Film and polyimide resin film, but also can adopt other insulation films, for example Si ₃N ₄Film.And, though adopt GaAs (100) face to make substrate, also can adopt any other material and crystal orientation certainly.Example 5

Describe with reference to Fig. 7 to 8 below and make the differential amplifier circuit of use-case 1 to any AlGaAs/GaAs heterojunction bipolar transistor described in the example 4.Fig. 7 is a circuit diagram, and Fig. 8 is a circuit layout.

In these figure, Q ₁To Q ₇The expression heterojunction bipolar transistor, E, B and C represent emitter, base stage and collector, R respectively ₁To R ₅Expression resistance, V _iThe expression input voltage, V ₀₁And V ₀₂The expression output voltage, V _CCThe expression supply voltage, V _EEThe expression earth potential, V _RThe expression reference voltage, V _CcbThe expression constant voltage.

According to this example, may realize to carry out the differential amplifier circuit of ultrahigh speed running with height integrated level very.And, might adopt such differentiating amplifier circuit to realize electronic circuit system as elementary cell.

Though this routine differentiating amplifier circuit uses the heterojunction bipolar transistor of AlGaAs/GaAs system, also can use the heterojunction bipolar transistor of other III-V compound semiconductors, for example InAlAs/InGaAs and InP/InGaAs system.Example 6

Below, with reference to Figure 10 heterogeneous-isolated-gate field effect transistor (IGFET) in the embodiment of the invention 6 is described.

At first, (Be concentration is 3 * 10 to adopt epitaxial growth to form p type GaAs layer 27 successively on GaAs (100) substrate 26 ¹⁶/ cm ³, thick 300nm), (Si concentration is 4 * 10 to heavy doping n type GaAs channel layer 28 ¹⁹/ cm ³, thick 20nm), not doping type AlGaAs layer 28 (AlAs Mo Er ratio is 0.3, thick 50nm) and doping type GaAs layer 28 (thick 5nm) not.Subsequently, expose substrate 26, so that device is isolated mutually by photoetching and corrosion.Then, forming thickness is the WSi gate electrode 29 of 700nm.(Figure 10 (a))

Below, deposit SiO on whole surface ₂, and, allow part to keep resulting SiO by photoetching and dry etching ₂Film comprises side wall 30 (the long 0.3 μ m of side wall).With these SiO ₂The district is as mask, with epitaxial crystal surface corrosion 90nm to expose the side of channel layer 28.Subsequently, (Si concentration is 4 * 10 to adopt selective metal-organic-matter chemical vapor deposition method to form heavily doped n type GaAs layer 31 in this corrosion area selectivity ¹⁸/ cm ³, thick 250nm), be used for forming the source and the drain region of low-resistance.This heavily doped n type GaAs layer 31 links to each other with the side of channel layer 28.Then, form AuGe source electrode 32S and AuGe drain electrode 32D in these zones.(Figure 10 (b))

Then, deposit SiO on whole surface ₂, and be that gate electrode 29 forms SiO by dry etching ₂Side wall 33.(Figure 10 (c))

Then, in molecular beam epitaxy system,, obtain polycrystal layer 34 at 350 ℃ of thick unadulterated GaAs of following deposit 50nm of substrate heating temperature.(Figure 10 (d))

Then, deposit SiO on whole surface ₂Film 35 forms the anticorrosion mask 36 that is used for making contact hole with photoetching process.(Figure 10 (e))

Then, adopt C ₂F ₆And CHE ₃The RIE method of gas is to SiO ₂Film 35 carries out the dry etching of selective anisotropic, obtains not Doped GaAs layer 34 of polycrystalline.(Figure 10 (f))

Then, adopt SiCl ₄The ECR method of gas to polycrystalline not Doped GaAs layer 34 carry out the dry etching of selective anisotropic, obtain gate electrode 29 and SiO ₂Side wall 30,33 exposes gate electrode 29.Simultaneously, form the contact hole of source and drain electrode in the same way.(Figure 10 (g))

Then, the lead-in wire metal level 37 of deposit low resistance metal and carry out ion etching and form lead-in wire and obtain heterogeneous-isolated-gate field effect transistor (IGFET).(Figure 10 (h))

According to this example, may produce heterogeneous-isolated-gate field effect transistor (IGFET) with high finished product rate, even be 0.3 μ m and the spacing of gate electrode and source-drain area is under the small size device structure situation of 0.3 μ m, can not produce grid-source and grid-leakage problem of short-circuit at gate electrode,

In this example, though adopt not Doped GaAs layer 34 of polycrystalline in the insulating interlayer zone, this one deck does not require always uses polycrystal.It can be the mixture of amorphous state or amorphous and polycrystalline material.And the layer of being discussed can be the polycrystal or the amorphous compound semiconductor of other materials, as AlGaAs.Though what relate in this example is heterogeneous-isolated-gate field effect transistor (IGFET), the present invention also is applicable to other field-effect transistors, as HEMT (high electron mobility field-effect transistor), MESFET (metal Schottky-based field-effect transistor), and MIS (metal-insulator layer-semiconductor) structure field-effect transistor.And, as backing material, can adopt various other materials, comprise compound semiconductor and single element semiconductor, as the Si semiconductor.Example 7

Figure 11 with reference to expression storage unit circuit figure describes the static ram cell that adopts example 6 heterogeneous-isolated-gate field effect transistor (IGFET)s below.

T1 represents heterogeneous-isolated-gate field effect transistor (IGFET) to T6, Vcc represents power supply potential, and Vss represents earth potential, and W represents word line, and B1 and B2 represent bit line.The voltage of B1 is opposite with the polarity of voltage of B2.

According to this example, might make a kind of highly reliable storage unit circuit with high integration, also may adopt this storage unit circuit to make Circuits System as elementary cell.Example 8

Figure 12 with reference to expression storage unit circuit figure describes the dynamic random memory cell that adopts example 6 heterogeneous-isolated-gate field effect transistor (IGFET)s below.

T1 represents heterogeneous-isolated-gate field effect transistor (IGFET), C1 represents storage capacitance, and Vss represents earth potential, and W represents word line, and B represents bit line.

According to this example, might make a kind of highly reliable storage unit circuit with high integration, also may adopt this storage unit circuit to make Circuits System as elementary cell.

Though each has just described the storage unit circuit that uses heterogeneous-isolated-gate field effect transistor (IGFET) in example 7 and example 8, can certainly use the field-effect transistor of any other type.

The present invention also is applicable to other semiconductor device, and for example light emitting devices and light receiving element rather than the described device of above-mentioned example also are applicable to the integrated circuit and the electronic circuit that utilize this semiconductor device in addition.

Claims

1. semiconductor device comprises:

One single-crystal semiconductor layer;

First conductive layer that on described single-crystal semiconductor layer, forms;

First insulating barrier that forms on each limit of described first conductive layer;

First semiconductor layer of the polycrystalline attitude that on first insulating barrier, forms or the unadulterated III-V compound semiconductor of amorphous state or its alloy, and have the through hole that described first conductive layer and described first insulating barrier are partly exposed; And

Second conductive layer that in described through hole, contacts with described first conductive layer.

2. according to the semiconductor device of claim 1, wherein said III-V compound semiconductor is GaAs.

3. according to the semiconductor device of claim 1, wherein said single-crystal semiconductor layer comprises collecting region, base, the emitter region of bipolar transistor, described first conductive layer is collector electrode or emitter electrode, described semiconductor device also is included in second insulating barrier that forms on described first semiconductor layer, described second insulating barrier has a through hole, and the shape of through holes that forms on the boundary shape of this through hole and described first semiconductor layer is basic identical.

4. according to the semiconductor device of claim 3, wherein said III-V compound semiconductor is GaAs.

5. according to the semiconductor device of claim 3, wherein said first conductive layer is an emitter electrode, described single-crystal semiconductor layer also is included in the auxiliary collecting region that a side relative with described base on the described collecting region forms, this collecting region and base are less than auxiliary collecting region, described emitter region is less than collecting region and base, described semiconductor device also comprises and described auxiliary collecting region, collecting region contacts the insulating barrier that forms and a through hole is arranged on described base with the base, the base lead-out wire semiconductor layer that has identical conduction light type with described base, base in the through hole of described base lead-out wire semiconductor layer and described insulating barrier contacts, and contacts with described base lead-out wire semiconductor layer and extend to described insulating barrier and the base electrode that forms.

6. according to the semiconductor device of claim 5, wherein said III-V compound semiconductor is GaAs.

7. according to the semiconductor device of claim 5, wherein said bipolar transistor is a kind of heterojunction bipolar transistor that is made of compound semiconductor, and its EB junction is a heterojunction, and described base lead-out wire semiconductor layer is made of compound semiconductor.

8. according to the semiconductor device of claim 7, wherein said III-V compound semiconductor is GaAs.

9. according to any semiconductor device of claim 1-8, wherein said first insulating barrier is an insulation Si compound layer.

10. according to the semiconductor device of claim 1, wherein said single-crystal semiconductor layer comprises the channel region of a field-effect transistor, described first conductive layer is a gate electrode, described semiconductor device also is included in second insulating barrier that forms on first semiconductor layer, described second insulating barrier has a through hole, and its inner circumference shape is identical with the shape of through holes that forms on described first semiconductor layer.

11. according to the semiconductor device of claim 10, wherein said III-V compound semiconductor is GaAs.

12. according to the semiconductor device of claim 10, wherein said field-effect transistor is made of compound semiconductor.

13. according to the semiconductor device of claim 12, wherein said III-V compound semiconductor is GaAs.

14. according to any semiconductor device of claim 10-13, wherein said first insulating barrier and second insulating barrier all are insulation Si compound layers.

15. a method that is used for making semiconductor device comprises the steps:

On single-crystal semiconductor layer, form first conductive layer;

Each side at described first conductive layer forms first insulating barrier, and the upper surface of first conductive layer is exposed;

On described first insulating barrier and described first conductive layer, form not first semiconductor layer of doped with II I-V compound semiconductor or its alloy of polycrystalline or amorphous;

On described first semiconductor layer, form second insulating barrier;

Adopt reacting gas in described second insulating barrier, to form first through hole, make it to reach first semiconductor layer according to the selectivity dry corrosion method of relative first semiconductor layer;

Adopt reacting gas and apparatus to have described second insulating barrier of described first through hole to make etch mask, selectivity dry corrosion method according to relative first conductive layer and first insulating barrier, in described first semiconductor layer, form second through hole, make it to reach described first conductive layer and described first insulating barrier around first conductive layer to small part;

Form second conductive layer, make it in the through hole that constitutes by first and second through holes, to contact with described first conductive layer.

16. according to the method for claim 15, wherein GaAs is as described III-V compound semiconductor.

17. method according to claim 15, wherein said first semiconductor layer is to be no more than under 400 ℃ the temperature the substrate heating, to form according to the film formation method of selecting from molecular beam epitaxy, metal-organic chemical vapor deposition process, metal-organic chemical molecular beam epitaxy and sputtering method.

18. according to the method for claim 16, wherein GaAs is as described III-V compound semiconductor.

19. according to the method for claim 15, wherein said single-crystal semiconductor layer comprises the semiconductor layer of the compound semiconductor that contains In, also is included in the Cl that pressure is no more than 40mPa ₂And CH ₄The step of according to the microwave etching method described semiconductor layer being corroded in the mixed atmosphere.

20. according to any described method of claim 15-19, wherein said first insulating barrier and second insulating barrier all are insulation Si compound layers.