CN109192714A - Frame substrate for electroplating shielding and manufacturing method thereof - Google Patents
Frame substrate for electroplating shielding and manufacturing method thereof Download PDFInfo
- Publication number
- CN109192714A CN109192714A CN201810816550.9A CN201810816550A CN109192714A CN 109192714 A CN109192714 A CN 109192714A CN 201810816550 A CN201810816550 A CN 201810816550A CN 109192714 A CN109192714 A CN 109192714A
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- CN
- China
- Prior art keywords
- layer
- plating
- exposed
- frame base
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 title abstract description 7
- 238000009713 electroplating Methods 0.000 title abstract description 3
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000004381 surface treatment Methods 0.000 claims abstract description 12
- 239000003989 dielectric material Substances 0.000 claims abstract description 11
- 238000007747 plating Methods 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000005507 spraying Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 abstract description 5
- 230000002860 competitive effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract 6
- 239000002335 surface treatment layer Substances 0.000 abstract 2
- 230000007547 defect Effects 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
The invention relates to a frame substrate for electroplating shielding and a manufacturing method thereof, wherein the frame substrate comprises a first characteristic layer (1) and a second characteristic layer (2), the peripheries of the first characteristic layer (1) and the second characteristic layer (2) are coated with dielectric materials (5), the first characteristic layer (1) comprises a grounding exposed pin (6) and an independent unexposed pin (7), a first surface treatment layer (3) is arranged on the surface of the second characteristic layer (2), and second surface treatment layers (4) are arranged on the surfaces of the grounding exposed pin (6) and the independent unexposed pin (7). The invention can solve the defect that the surface treatment of the independent pin can not be realized by the traditional process, and can meet different designs and different packaging requirements of customers, thereby greatly improving the competitive advantage of the product in the market.
Description
Technical field
The present invention relates to a kind of frame bases and its manufacturing method for plating shield, belong to semiconductor packaging neck
Domain.
Background technique
With the development of science and technology and the needs of life, in daily life, it is not merely sound, information that we, which require mobile phone,
Transmitting, becomes closer to original information with greater need for these obtained information, this requires electronic products to go back to various signals
Former validity is higher, and the interference requirement between signal is accomplished smaller and smaller.Due between this electronics module there are electromagnetic interference,
So the increase for needing electromagnetism (EMI) to shield.
There is the processing method being much electromagnetically shielded in industry, for example covers metallic shield, spraying, sputtering, covering metal
Etc..
Traditional mobile phone EMI shielding is using metallic shield, and shielding case will horizontally occupy valuable PCB surface product,
Also the solid space inside equipment is occupied on longitudinal direction, be a big obstacle of device miniaturization.New shield technology --- it is conformal
It shields (Conformal shielding), shielded layer and encapsulation is fused together completely, mould group itself just has shielding function
Can, after chip attachment is on PCB, it is no longer necessary to which additional shielding case is not take up the additional device space, to solve this hardly possible
Topic.
Accomplish that shielded layer combines together completely with encapsulation, then needs packaging frame and partially connect after the completion of encapsulating cutting
Ground exposed metal is connected by the metal on exposed metal and packaging body, is formed the structure of all closure conductings, is realized screen
The effect of covering layer.
The design of exposed metal after encapsulation may be implemented in traditional packaging frame, but for client because of functional requirement
Independent pin design can not depend on other any pins, but realize that this is just needed for functions such as routing, upside-down mountings again
The processing such as gold-plated, silver-plated is also carried out on independent pin, frame-generic is then unable to reach requirement.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of frame for plating shield for the above-mentioned prior art
Substrate and its manufacturing method, it is able to solve the shortcomings that traditional handicraft cannot achieve the surface treatment of independent pin, can satisfy visitor
The different design in family, different encapsulation requirement, to substantially increase product competitive advantage in the market.
The present invention solves the above problems used technical solution are as follows: a kind of frame base for plating shield, it is wrapped
Including fisrt feature layer and second feature layer, the fisrt feature layer and second feature layer periphery are coated with dielectric material, and described
One characteristic layer includes being grounded exposed pin and independent not exposed pin, and the second feature layer surface is provided with first surface processing
Layer, the exposed pin of ground connection and independent not exposed pin surface are provided with second surface process layer.
Preferably, the first surface process layer and the second surface process layer are all made of NiPdAu layer.
A kind of manufacturing method of the frame base for plating shield, the described method comprises the following steps:
Step 1: taking a metal plate as bottom plate；
Step 2: covering photoresist layer on bottom plate, exposes and be developed in bottom plate front and formed needed for fisrt feature layer and scheme
The negativity characteristic pattern of shape；
Step 3: plating is to make fisrt feature layer；
Step 4: continuing to second layer photoresist layer, exposing and being developed in needed for bottom plate front formation second feature layer
The negativity characteristic pattern of figure；
Step 5: plating is to make second feature layer；
Step 6: removal photoresist layer；
Step 7: coating all characteristic layers with dielectric material；
Step 8: grinding dielectric material face is to expose outermost layer feature layer pattern；
Step 9: two sides covers photoresist layer, the pattern that the bottom plate back side forms the required figure that opens a window, erosion are exposed and are developed in
Windowing is carved to expose the figure of fisrt feature layer；
Step 10: removal photoresist layer；
Step 11: conducting processing is carried out to product surface, so that entire product surface covers metal layer；
Step 12: two sides covers photoresist layer, exposes and be developed in required for product is showed out and be surface-treated
Pattern guarantees that the exposed figure of fisrt feature layer has part to be connected with figure is not exposed；
Step 13: the conducting metal layer of exposed portion is removed；
Step 14: being surface-treated to the windowed regions of removal conducting metal layer；
Step 15: removal photoresist layer；
Step 16: removing remaining conducting metal layer.
Preferably, the metal layer in step 11 uses copper.
Preferably, conducting is handled by the way of changing plating, sputtering, spraying or attaching in step 11.
Preferably, surface treatment uses nickel gold, NiPdAu or silver-plated process in step 14.
Preferably, step 12 to step 15 is repeated as many times, and realizes a variety of tables by exposing different positions every time
Surface treatment mode is on a product.
Preferably, the surface treatment mode of step 14 is led to using directly plating, or using in outermost layer feature layer surface
It crosses microetch and forms groove, recess region carries out plating again and forms recessed or raised surface-treated layer.
Compared with the prior art, the advantages of the present invention are as follows:
1, the present invention can effectively cooperate packaging process, realize newest conformal shielding；
2, the present invention, which solves available frame, cannot achieve the graphic designs of independent pin, solve common substrate long flow path,
Encapsulation thickness, problem at high cost；
3, the present invention makes substrate using pre-packaged method, optimizes in original technique, realizes original technique
The drawbacks of doing electroplating surface processing on the independent pin that cannot achieve；
4, for the present invention from the point of view of product structure, it does not need to increase extra coating or metal layer in finished product, ensure that
Good binding force between each layer of product, to guarantee higher product reliability；
5, the present invention is with the superior design face diversity of its bring, the advantage of high reliability and low cost,
Superior competitiveness is brought in the market.
Detailed description of the invention
Fig. 1 is that the 3D of conventional package frame schemes.
Fig. 2 is the sectional view of Fig. 1.
Fig. 3 is that the 3D of traditional pre-packaged substrate schemes.
Fig. 4 is the sectional view of Fig. 3.
Fig. 5 is a kind of 3D figure of frame base for plating shield of the present invention.
Fig. 6 is the sectional view of Fig. 5.
Fig. 7~Figure 25 is a kind of each process flow chart of the frame base manufacturing method for plating shield of the present invention.
Wherein:
Fisrt feature layer 1
Second feature layer 2
First surface process layer 3
Second surface process layer 4
Dielectric material 5
It is grounded exposed pin 6
Independent not exposed pin 7.
Specific embodiment
The present invention will be described in further detail below with reference to the embodiments of the drawings.
As shown in Figure 5, Figure 6, one of the present embodiment is used for the frame base of plating shield, it includes fisrt feature layer
1 and second feature layer 2, the fisrt feature layer 1 and 2 periphery of second feature layer be coated with dielectric material 5, the fisrt feature layer
1 includes being grounded exposed pin 6 and independent not exposed pin 7, and 2 surface of second feature layer is provided with first surface process layer 3,
The exposed pin 6 of ground connection and independent not exposed 7 surface of pin are provided with second surface process layer 4；
The first surface process layer 3 uses NiPdAu layer；
The second surface process layer 4 uses NiPdAu layer.
Its manufacturing method the following steps are included:
Step 1: taking a metal plate as bottom plate referring to Fig. 7；
Step 2: participating in Fig. 8, photoresist layer is covered on bottom plate, exposes and is developed in bottom plate front formation fisrt feature
The negativity characteristic pattern of figure needed for layer；
Step 3: being electroplated referring to Fig. 9 to make fisrt feature layer；
Step 4: continuing to second layer photoresist layer referring to Figure 10, exposing and being developed in bottom plate front formation second and is special
The negativity characteristic pattern of figure needed for levying layer；
Step 5: being electroplated referring to Figure 11 to make second feature layer；
Step 6: removing photoresist layer referring to Figure 12；
Step 7: coating all characteristic layers with dielectric material referring to Figure 13；
Step 8: grinding dielectric material face referring to Figure 14 to expose outermost layer feature layer pattern；
Step 9: two sides covers photoresist layer referring to Figure 15, Figure 16, exposes and be developed in bottom plate back side formation windowing institute
The pattern of figure is needed, etching opens a window to expose the figure of fisrt feature layer；
Step 10: removing photoresist layer referring to Figure 17；
Step 11: conducting processing is carried out to product surface referring to Figure 18, so that entire product surface covers metal layer,
Metal layer herein includes all electrically conductive metals, such as copper.The mode of processing includes: changing plating, sputtering, spraying, attaches
Etc. a variety of；
Step 12: two sides covers photoresist layer referring to Figure 19, exposes and be developed in carry out table required for product is showed out
The pattern of surface treatment guarantees that the exposed figure of fisrt feature layer has part to be connected with figure is not exposed；
Step 13: referring to fig. 20, the conducting metal layer of exposed portion is removed；
Step 14: referring to fig. 21, the windowed regions of removal conducting metal layer are surface-treated, including nickel gold, nickel
The processing such as porpezite, silver-plated；
Step 15: referring to fig. 22, remove photoresist layer；
Step 16: referring to fig. 23, remove remaining conducting metal layer.
The step 12 can be repeated constantly, be realized by exposing different positions every time a variety of to step 15
Surface treatment mode is on a product；
The surface treatment mode of the step 14 can directly be electroplated, and can also pass through in outermost layer feature layer surface micro-
Etching forms groove, and recess region carries out plating again and forms recessed or raised surface-treated layer, and referring to fig. 24, Figure 25.
In addition to the implementation, all to use equivalent transformation or equivalent replacement the invention also includes there is an other embodiments
The technical solution that mode is formed should all be fallen within the scope of the hereto appended claims.
Claims (9)
1. a kind of frame base for plating shield, it is characterised in that: it includes fisrt feature layer (1) and second feature layer
(2), the fisrt feature layer (1) and second feature layer (2) periphery are coated with dielectric material (5), fisrt feature layer (1) packet
The exposed pin (6) of ground connection and independent not exposed pin (7) are included, second feature layer (2) surface is provided with first surface processing
Layer (3), the exposed pin (6) of ground connection and independent not exposed pin (7) surface are provided with second surface process layer (4).
2. a kind of frame base for plating shield according to claim 1, it is characterised in that: at the first surface
Reason layer (3) and the second surface process layer (4) are all made of NiPdAu layer.
3. a kind of manufacturing method of the frame base for plating shield, it is characterised in that the described method comprises the following steps:
Step 1: taking a metal plate as bottom plate；
Step 2: covering photoresist layer on bottom plate, exposing and being developed in figure needed for bottom plate front forms fisrt feature layer
Negativity characteristic pattern；
Step 3: plating is to make fisrt feature layer；
Step 4: continuing to second layer photoresist layer, exposing and being developed in figure needed for bottom plate front forms second feature layer
Negativity characteristic pattern；
Step 5: plating is to make second feature layer；
Step 6: removal photoresist layer；
Step 7: coating all characteristic layers with dielectric material；
Step 8: grinding dielectric material face is to expose outermost layer feature layer pattern；
Step 9: two sides covers photoresist layer, the pattern that the bottom plate back side forms the required figure that opens a window is exposed and be developed in, is etched open
Window is to expose the figure of fisrt feature layer；
Step 10: removal photoresist layer；
Step 11: conducting processing is carried out to product surface, so that entire product surface covers metal layer；
Step 12: two sides covers photoresist layer, the pattern being surface-treated required for product is showed out is exposed and is developed in,
Guarantee that the exposed figure of fisrt feature layer has part to be connected with figure is not exposed；
Step 13: the conducting metal layer of exposed portion is removed；
Step 14: being surface-treated to the windowed regions of removal conducting metal layer；
Step 15: removal photoresist layer；
Step 16: removing remaining conducting metal layer.
4. a kind of manufacturing method of frame base for plating shield according to claim 3, it is characterised in that: step
Metal layer in 11 uses copper.
5. a kind of manufacturing method of frame base for plating shield according to claim 3, it is characterised in that: step
Conducting is handled by the way of changing plating, sputtering, spraying or attaching in 11.
6. a kind of manufacturing method of frame base for plating shield according to claim 3, it is characterised in that: step
Surface treatment is using nickel gold, NiPdAu or silver-plated process in 14.
7. a kind of manufacturing method of frame base for plating shield according to claim 3, it is characterised in that: step
12 are repeated as many times to step 15, realize a variety of surface treatment modes with a production by exposing different positions every time
On product.
8. a kind of manufacturing method of frame base for plating shield according to claim 3, it is characterised in that: step
14 surface treatment mode is using directly plating.
9. a kind of manufacturing method of frame base for plating shield according to claim 3, it is characterised in that: step
14 surface treatment mode, which is used, forms groove by microetch in outermost layer feature layer surface, and recess region is electroplated again
Form recessed or raised surface-treated layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810816550.9A CN109192714B (en) | 2018-07-24 | 2018-07-24 | Frame substrate for electroplating shielding and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810816550.9A CN109192714B (en) | 2018-07-24 | 2018-07-24 | Frame substrate for electroplating shielding and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109192714A true CN109192714A (en) | 2019-01-11 |
| CN109192714B CN109192714B (en) | 2020-07-14 |
Family
ID=64936578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810816550.9A Active CN109192714B (en) | 2018-07-24 | 2018-07-24 | Frame substrate for electroplating shielding and manufacturing method thereof |
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| Country | Link |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116170954A (en) * | 2023-04-23 | 2023-05-26 | 四川富乐华半导体科技有限公司 | Surface metallization method for alumina DPC product with three-dimensional pin structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6396129B1 (en) * | 2001-03-05 | 2002-05-28 | Siliconware Precision Industries Co., Ltd. | Leadframe with dot array of silver-plated regions on die pad for use in exposed-pad semiconductor package |
| CN1650425A (en) * | 2002-04-30 | 2005-08-03 | 株式会社瑞萨科技 | Semiconductor device and electronic device |
| CN106024750A (en) * | 2016-07-14 | 2016-10-12 | 江阴芯智联电子科技有限公司 | Metal lead frame structure with low test cost and manufacturing method thereof |
| CN106783794A (en) * | 2017-03-16 | 2017-05-31 | 江阴芯智联电子科技有限公司 | It is pre-packaged without wire electrodepositable lead-frame packages structure and its manufacture method |
-
2018
- 2018-07-24 CN CN201810816550.9A patent/CN109192714B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6396129B1 (en) * | 2001-03-05 | 2002-05-28 | Siliconware Precision Industries Co., Ltd. | Leadframe with dot array of silver-plated regions on die pad for use in exposed-pad semiconductor package |
| CN1650425A (en) * | 2002-04-30 | 2005-08-03 | 株式会社瑞萨科技 | Semiconductor device and electronic device |
| CN106024750A (en) * | 2016-07-14 | 2016-10-12 | 江阴芯智联电子科技有限公司 | Metal lead frame structure with low test cost and manufacturing method thereof |
| CN106783794A (en) * | 2017-03-16 | 2017-05-31 | 江阴芯智联电子科技有限公司 | It is pre-packaged without wire electrodepositable lead-frame packages structure and its manufacture method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116170954A (en) * | 2023-04-23 | 2023-05-26 | 四川富乐华半导体科技有限公司 | Surface metallization method for alumina DPC product with three-dimensional pin structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109192714B (en) | 2020-07-14 |
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