CN109192699A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN109192699A CN109192699A CN201811040236.2A CN201811040236A CN109192699A CN 109192699 A CN109192699 A CN 109192699A CN 201811040236 A CN201811040236 A CN 201811040236A CN 109192699 A CN109192699 A CN 109192699A
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- groove
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- sacrificial layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Abstract
This disclosure relates to a kind of method for manufacturing semiconductor device comprising: dielectric layer is formed in substrate, wherein the substrate includes first area and second area；Sacrificial layer is formed on the dielectric layer；The dielectric layer and the sacrificial layer are carried out being patterned so as to be formed opening；Operation is performed etching to the substrate by the opening, to form first groove in the first region, and forms second groove in the second area, wherein the depth of first groove in the substrate is less than the depth of second groove in the substrate；Remove the sacrificial layer.
Description
Technical field
This disclosure relates to semiconductor field, it particularly relates to the manufacturing method of semiconductor device.
Background technique
The design of some semiconductor devices needs that there are the shallow trench isolation of different depth (STI).And the STI of different depth
Formation process after, formed different depth STI region between there may be differences in height, and this difference in height be easy
Defect is caused in subsequent fabrication processing (such as etching forms gate pattern).These defects may influence the yield of wafer.
Therefore there is the demand for new technology.
Summary of the invention
One purpose of the disclosure is to provide a kind of novel manufacturing method for semiconductor device, particularly, be related to avoiding by
In being formed simultaneously defect caused by different depth groove.
According to the disclosure in a first aspect, providing a kind of method for manufacturing semiconductor device comprising: in substrate
On form dielectric layer, wherein the substrate includes first area and second area；It is formed on the dielectric layer sacrificial
Domestic animal layer；The dielectric layer and the sacrificial layer are carried out being patterned so as to be formed opening；By the opening come to the lining
Bottom performs etching operation, to form first groove in the first region, and forms second groove in the second area, wherein
The depth of first groove in the substrate is less than the depth of second groove in the substrate；Remove the sacrificial layer.
By referring to the drawings to the detailed description of exemplary embodiment of the present invention, other feature of the invention and its
Advantage will become more apparent from.
Detailed description of the invention
The attached drawing for constituting part of specification describes embodiment of the disclosure, and together with the description for solving
Release the principle of the disclosure.
The disclosure can be more clearly understood according to following detailed description referring to attached drawing, in which:
Fig. 1 schematically shows the sectional view of the semiconductor device of the prior art.
Fig. 2 shows the flow charts according to the manufacturing method of the semiconductor device of the disclosure one exemplary embodiment.
Fig. 3 A-3H is respectively illustrated in a side for manufacturing semiconductor device according to one exemplary embodiment of the disclosure
Device schematic cross-section at the exemplary each step of method.
Note that same appended drawing reference is used in conjunction between different attached drawings sometimes in embodiments described below
It indicates same section or part with the same function, and omits its repeated explanation.In the present specification, using similar mark
Number and letter indicate similar terms, therefore, once being defined in a certain Xiang Yi attached drawing, then do not needed in subsequent attached drawing pair
It is further discussed.
In order to make it easy to understand, position, size and range of each structure shown in attached drawing etc. etc. do not indicate practical sometimes
Position, size and range etc..Therefore, disclosed invention is not limited to position, size and range disclosed in attached drawing etc. etc..
Specific embodiment
It is described in detail the various exemplary embodiments of the disclosure below with reference to accompanying drawings.It should also be noted that unless in addition having
Body explanation, the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
Scope of disclosure.
Be to the description only actually of at least one exemplary embodiment below it is illustrative, never as to the disclosure
And its application or any restrictions used.That is, semiconductor device and its manufacturing method herein is with illustrative
Mode is shown, to illustrate the different embodiments of the structures and methods in the disclosure.It will be understood by those skilled in the art, however, that
They, which are merely illustrative, can be used to the exemplary approach of the invention implemented, rather than mode exhausted.In addition, attached drawing need not be by
Ratio is drawn, and some features may be amplified to show the details of specific component.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of, the technology, method and apparatus should be considered as authorizing part of specification.
It is shown here and discuss all examples in, any occurrence should be construed as merely illustratively, without
It is as limitation.Therefore, the other examples of exemplary embodiment can have different values.
The inventors of the present application found that being easy when being formed simultaneously the groove of different depth in a semiconductor device
Formed different depth groove region between there are differences in height, consequently, it is possible to subsequent fabrication processing (such as etching formed
Gate pattern) in cause defect, influence the yield of wafer.Partly leading for the prior art is specifically described below with reference to the example of Fig. 1
Body device difference in height that may be present.
Fig. 1 shows two regions of semiconductor device, i.e. first area and second area, and wherein dotted line indicates the two
The boundary in region.Multiple grooves 103 in first area are less than multiple grooves in second area in the depth in substrate 101
104 depth in substrate 101.For example, the depth of groove 103 can be less than or equal to the half of the depth of groove 104.It is logical
Often, groove 103 and 104 is formed by etched substrate 101, is blocked in etching process with hard mask 102 and is not etched
Part.To which hard mask 102 may also be etched away a part in the etching process.Due to the etching of groove 103 and 104
Depth is different, and it is also different to typically result in the thickness that the hard mask 102 in first area and second area is correspondingly etched away, because
After this etching, hard mask 102 is different from the thickness in second area in first area, i.e., first area and second area it
Between boundary (shown in dotted line) at there are differences in height, that is to say, that there are steps as shown in Figure 1.In such as subsequent etching shape
During at gate electrode (usually polysilicon) pattern, which is easy to cause the etching polysilicon of first area not
It is complete, and the polysilicon over etching of second area, influence the yield of wafer.
In this regard, present inventor wishes the manufacturing method by improveing this semiconductor device to avoid such lack
It falls into.
By further investigation, present inventor proposes a kind of manufacturing method of novel semiconductor device, sets
Sacrificial layer is set to serve as at least part of hard mask so that due to different depth groove etching caused by difference in height it is basic
It falls on sacrificial layer.The difference in height is eliminated substantially and removing sacrificial layer after etching forms groove, so as to avoid it
To the adverse effect of the subsequent manufacturing processes of semiconductor device.Therefore, the yield of wafer can be improved using the technology of the disclosure.
In order to more comprehensively, the present invention is expressly understood, the novel skill according to the disclosure is illustrated below in conjunction with attached drawing
Art.
Fig. 2 shows the flow charts according to the manufacturing method for semiconductor device 200 of the disclosure one exemplary embodiment.
Specifically, form dielectric layer in substrate as shown in Fig. 2, at step 210, wherein substrate includes the
One region and second area.
In some embodiments, substrate can be semiconductor substrate, by any semiconductor for being suitable for semiconductor device
Material (Si, SiC, SiGe etc.) is made.In other embodiments, substrate may be silicon-on-insulator (SOI), absolutely
The various compound substrates such as germanium silicon on edge body.Those skilled in the art understand that substrate is not any way limited, but can basis
Practical application is selected.Could be formed with other semiconductor device components in substrate, for example, trap and/or early stage handle
The other components formed in step.Before forming dielectric layer, other layers or component can also be already formed on substrate.
In some embodiments, dielectric layer may include pad oxide layer and the nitrogen in pad oxide layer
SiClx layer.The pad oxide can be silica etc..
At step 220, sacrificial layer is formed on dielectric layer.
In some embodiments, sacrificial layer can be made of amorphous carbon.Substrate is selected relative to the etching of amorphous carbon
Select relatively high, therefore the thickness of sacrificial layer that amorphous carbon is constituted can be made thinner.
In some embodiments, the step of forming the sacrificial layer of the amorphous carbon may include: to utilize hydrocarbon
One layer of amorphous carbon is deposited as reaction gas and using chemical vapor deposition process using as the sacrificial layer.The sacrificial layer
Thickness can be in the range of 50~100 nanometers.
At step 230, dielectric layer and sacrificial layer are carried out being patterned so as to be formed opening.
In some embodiments, it is patterned by dry etching dielectric layer and sacrificial layer.Described
Opening exposes following substrate, so that etched substrate in subsequent processing is to form groove.
At step 240, operation is performed etching to substrate by being open, to form the first ditch in the first region
Slot, and second groove is formed in the second area, wherein the depth of first groove in the substrate is less than second groove in substrate
In depth.
In some embodiments, which may include: to carry out the first etching processing to substrate by being open
So that first groove and second groove reach the predetermined depth of first groove；And first area is at least blocked, to substrate
Second area carries out the second etching processing, so that second groove reaches the predetermined depth of second groove.
Above-mentioned predetermined depth, that is, projected depth, that is to say, that the depth reached it is expected in the design of the semiconductor device.When
The right predetermined depth is there may be the factors bring deviation such as manufacturing process, this is similarly within the scope of the present invention.Separately
Outside, it can use photoresist to be blocked.
The etching operation is not limited to said circumstances.For example, method of the invention, which can also separate etching, forms the first ditch
Slot and second groove block second area in first time etching processing, form first groove, and in second of etching processing
When block first area, form second groove.
In some embodiments, thickness of the sacrificial layer after etching operation on first area is greater than in second area
On thickness.In some embodiments, after the etching operation, on the first area of the substrate and second area
There are the sacrificial layers.
In some embodiments, big to the etching selection ratio of the substrate and the sacrificial layer in the etching operation
In or equal to 6:1.In the feelings that above-mentioned dielectric layer includes pad oxide layer and the silicon nitride layer in pad oxide layer
Under condition, 10 are greater than or equal to the etching selection ratio of the pad oxide layer and the sacrificial layer in the etching operation:
1,4:1 is greater than or equal to the etching selection ratio of the silicon nitride layer and the sacrificial layer.The substrate can be monocrystalline substrate.
Those skilled in the art understand that etching selection ratio refers to the ratio to the etch rate of different materials.
Then, at step 250, sacrificial layer is removed.
In some embodiments, it can use cineration technics removal sacrificial layer.
Further optionally, in some embodiments, after removal of the sacrificial layer, first groove and second groove are filled
And chemical mechanical polish process (CMP) is carried out, to be respectively formed first groove structure member and second groove structure member.
It can be by chemical vapor deposition (CVD) technique come deposition materials, to fill each groove.The property of the packing material depends on
The function etc. of the groove structure component.
In some embodiments, it fills first groove and the step of second groove may include: in first groove and the
Liner layer is formed on the wall of two grooves；Deposition of insulative material is to fill up first groove and second groove；And it is exhausted to what is deposited
Edge material carries out steam annealing processing.
In addition, in some embodiments, optionally, after carrying out chemical mechanical polish process, to the material of filling
Carve, to adjust the height of first groove structure member and second groove structure member.
In many semiconductor devices, the groove structure component of above-mentioned formation is shallow trench isolation portion.That is, above-mentioned
First groove structure member be the first shallow trench isolation portion, second groove structure member be the second shallow trench isolation portion.Certainly,
The present disclosure is not limited thereto, as long as the groove structure component is formed by filling groove.
In addition, the technology of the disclosure is especially suitable for imaging sensor, such as back side illumination image sensor.Imaging sensor
Usually there are two regions, i.e. pixel region and logic region.Requirement due to pixel region and logic region to performance is different
(for example, pixel region compares logic region to factors such as silicon substrate damages to the plasma in metal ion and etching process
More sensitive, the image quality of image can be seriously affected), this makes during prepared by technique, need in pixel region and
Logic region prepares the shallow trench isolation (STI) of different depth, and wherein the depth of the STI of pixel region is less than logic region
The depth of STI.Therefore, in the case where semiconductor device is imaging sensor, first area is the picture for being formed with pixel array
Plain region, second area are the logic region for being formed with the processing circuit for pixel array.Above-mentioned groove structure component is shallow
Trench isolations portion.Certainly, those skilled in the art can understand that the semiconductor device of the disclosure is not limited to imaging sensor, ditch
Slot structure component is not limited to shallow trench isolation portion.
Although only describing the groove to form two kinds of different depths above, those skilled in the art can understand, this
It invents without being limited thereto, but can be adapted for the groove to form three or more different depths.Moreover, substrate is also not necessarily limited to just
It, can also be comprising not forming the region of groove or forming the region etc. of other depth grooves comprising two regions.
By above-mentioned method shown in Fig. 2, the difference in height as caused by different depth groove can be substantially eliminated, to keep away
Exempt to impact subsequent manufacturing processes.Therefore it avoids due to existing simultaneously different depth groove and bring adversely affects,
Improve yield.
In order to understand the present invention more complete and comprehensively, will be described in detail by taking Fig. 3 A-3H as an example according to the disclosure one below
One specific example of the manufacturing method for semiconductor device of a exemplary embodiment.It note that this example is not intended to constitute
Limitation of the present invention.For example, the present invention is not limited in the specific structure of semiconductor device shown by Fig. 3 A-3H, but
All semiconductor devices for having same requirements or design consideration are all suitable for.It can also be fitted above in conjunction with content described in Fig. 2
For corresponding feature.
Fig. 3 A-3H respectively illustrates the device schematic cross-section at the exemplary each step of this method.
At Fig. 3 A, dielectric layer 302 and sacrificial layer 303 are formed on substrate 301.
As previously mentioned, substrate 301 is not any way limited, but can be selected according to practical application.In addition, substrate
Among and/or on be likely present other components, and in order to avoid obscuring the main points of the disclosure, attached drawing is not shown and herein
Also it does not go that other components are discussed.
In some embodiments, dielectric layer 302 can be constituted by two layers, respectively included pad oxide layer and be located at
Silicon nitride layer in pad oxide layer.The pad oxide can be silica, can carry out shape for example, by thermal oxidation
At.Silicon nitride layer can be formed by the methods of CVD.
Although the first area of substrate 301 and second area are drawn as two adjacent regions, this field in Fig. 3 A
Technical staff can understand that the invention is not limited thereto.Moreover, those skilled in the art can understand that substrate 301 is also not necessarily limited to just
Comprising the two regions, this figure, which is intended merely to facilitate, shows main points of the invention.
In some embodiments, sacrificial layer 303 can be made of amorphous carbon.The step of forming the sacrificial layer can wrap
It includes: using hydrocarbon (for example, acetylene) as reaction gas and utilizing chemical vapor deposition process (for example, PECVD)
To deposit one layer of amorphous carbon using as the sacrificial layer.The thickness of the amorphous carbon layer can be in 50~100 nanometers of range
It is interior, but those skilled in the art understand, the thickness is without being limited thereto, but can be according to actual process conditions and each layer material
Material attribute is selected.
At Fig. 3 B, dielectric layer 302 and sacrificial layer 303 are carried out to be patterned so as to be formed multiple openings 304.This is multiple
Opening 304 corresponds respectively to the first groove structure member (left side two as shown in Fig. 3 B to be formed in the first region
It is a) and the second groove structure member (as shown in Fig. 3 B the right two) to be formed in the second area.Certainly here only
It is two groove components shown for the sake of simple and convenient in each region, and there can actually be any number of grooves
Component.
Dielectric layer 302 and sacrificial layer 303 can be patterned by dry etching.Expose at opening 304
Following substrate 301 performs etching substrate 301 so as to subsequent to form groove (as shown in Figure 3 C).
At Fig. 3 C, the first etching processing is carried out to the substrate portions by 304 exposure of opening, to be respectively formed first
First groove 305 (two, the left side as shown in Fig. 3 C) in region and the second groove 306 in second area are (in such as Fig. 3 C
Two, the right shown).All grooves depth having the same at this time, the i.e. projected depth of first groove 305.
Then, at Fig. 3 D, the first area on the left side is blocked with photoresist 307, only to the second area of substrate into
The second etching processing of row, so that second groove 306 reaches its projected depth.Therefore, the depth of second groove 306 is greater than the first ditch
The depth of slot 305.Due to the etching processing also can etch away sections sacrificial layer 303, the sacrificial layer 303 after etching operation exists
Thickness on second area is less than the thickness on first area.Certainly, those skilled in the art can understand the present invention
It is without being limited thereto, but can according to need to design the thickness of sacrificial layer 303, so that sacrificial on second area after etching operation
Domestic animal layer 303 has just etched or slightly a bit, this also will not influence the height of following dielectric layer 302 to over etching substantially.
Then, at Fig. 3 E, shelter, i.e. photoresist 307 is removed, all grooves are exposed.
Then, at Fig. 3 F, sacrificial layer 303 is removed.
For example, can use the sacrificial layer that cineration technics removal amorphous carbon is constituted.By cineration technics, can it is simple,
Sacrificial layer is rapidly removed, and the influence to lower layer is smaller.
Then, at Fig. 3 G, groove is filled for example, by HARP technique, and CMP processing is carried out to the material of filling,
To be respectively formed first groove structure member 310 and second groove structure member 311.
In some embodiments, the process for filling groove may include:
Firstly, for example, by the oxidation of ISSG (in-site steam generation) technique in first groove 305 and the
It is formed on the wall of two grooves 306 than relatively thin oxide as liner layer 308, the temperature of the ISSG technique can be such as 1050
Degree Celsius；
Secondly, for example, by SACVD (sub-atmospheric chemical vapor deposition) process deposits
Insulating materials 309 is to fill up first groove 305 and second groove 306；
Finally, such as 600 degrees Celsius at a temperature of steam annealing processing is carried out to the insulating materials 309 that is deposited
(steam anneal)。
Then, at Fig. 3 H, to the material after CMP carry out back carve (etch back) (for example, can by wet etching come
Carve), to adjust the height of first groove structure member 310 and second groove structure member 311.As a result it obtains such as figure
Semiconductor device shown in 3H.It can carry out necessary subsequent fabrication processing according to the actual situation below.
It will be understood by those skilled in the art that the disclosure further includes shape other than the process and structure as shown in Fig. 3 A-3H
At other any process and structures necessary to semiconductor device.
Pass through method example shown by above-mentioned Fig. 3 A-3H, it can be seen that due to the groove of different depth etching and lead
The difference in height of cause is fallen on sacrificial layer substantially, eliminates the height substantially and removing sacrificial layer after etching forms groove
Difference, so as to avoid its adverse effect to the subsequent manufacturing processes of semiconductor device.
Manufacturing method above in conjunction with Fig. 3 A-3H description is first while to etch all grooves to the design depth compared with shallow trench
Then degree continues etching while at least blocking compared with shallow trench and forms deeper slot, be conducive to save deeper slot in this way
Etch period.However, those skilled in the art understand, the invention is not limited thereto.Method of the invention is not intended to limit groove
Etching process, as long as can be formed compared with shallow trench and deeper slot the two.It is etched for example, method of the invention can also separate
It is formed compared with shallow trench and deeper slot, i.e., blocks deeper slot region when being formed compared with shallow trench, and when forming deeper slot
It blocks compared with shallow trench area.
In the word "front", "rear" in specification and claim, "top", "bottom", " on ", " under " etc., if deposited
If, it is not necessarily used to describe constant relative position for descriptive purposes.It should be appreciated that the word used in this way
Language be in appropriate circumstances it is interchangeable so that embodiment of the disclosure described herein, for example, can in this institute
It is operated in those of description show or other other different orientations of orientation.
As used in this, word " illustrative " means " be used as example, example or explanation ", not as will be by
" model " accurately replicated.It is not necessarily to be interpreted than other implementations in any implementation of this exemplary description
It is preferred or advantageous.Moreover, the disclosure is not by above-mentioned technical field, background technique, summary of the invention or specific embodiment
Given in go out theory that is any stated or being implied limited.
As used in this, word " substantially " means comprising the appearance by the defect, device or the element that design or manufacture
Any small variation caused by difference, environment influence and/or other factors.Word " substantially " also allows by ghost effect, makes an uproar
Caused by sound and the other practical Considerations being likely to be present in actual implementation with perfect or ideal situation
Between difference.
In addition, the description of front may be referred to and be " connected " or " coupling " element together or node or feature.Such as
It is used herein, unless explicitly stated otherwise, " connection " mean an element/node/feature and another element/node/
Feature is being directly connected (or direct communication) electrically, mechanically, in logic or in other ways.Similarly, unless separately
It clearly states outside, " coupling " means that an element/node/feature can be with another element/node/feature with direct or indirect
Mode link mechanically, electrically, in logic or in other ways to allow to interact, even if the two features may
It is not directly connected to be also such.That is, " coupling " is intended to encompass the direct connection and indirectly of element or other feature
Connection, including the use of the connection of one or more intermediary elements.
In addition, just to the purpose of reference, can with the similar terms such as " first " used herein, " second ", and
And it thus is not intended to limit.For example, unless clearly indicated by the context, be otherwise related to structure or element word " first ", "
Two " do not imply order or sequence with other such digital words.
It should also be understood that one word of "comprises/comprising" as used herein, illustrates that there are pointed feature, entirety, steps
Suddenly, operation, unit and/or component, but it is not excluded that in the presence of or increase one or more of the other feature, entirety, step, behaviour
Work, unit and/or component and/or their combination.
In the disclosure, therefore term " offer " " it is right to provide certain from broadly by covering all modes for obtaining object
As " including but not limited to " purchase ", " preparation/manufacture ", " arrangement/setting ", " installation/assembly ", and/or " order " object etc..
It should be appreciated by those skilled in the art that the boundary between aforesaid operations is merely illustrative.Multiple operations
It can be combined into single operation, single operation can be distributed in additional operation, and operating can at least portion in time
Divide and overlappingly executes.Moreover, alternative embodiment may include multiple examples of specific operation, and in other various embodiments
In can change operation order.But others are modified, variations and alternatives are equally possible.Therefore, the specification and drawings
It should be counted as illustrative and not restrictive.
In addition, embodiment of the present disclosure can also include following example:
1, a kind of method for manufacturing semiconductor device characterized by comprising
Dielectric layer is formed in substrate, wherein the substrate includes first area and second area；
Sacrificial layer is formed on the dielectric layer；
The dielectric layer and the sacrificial layer are carried out being patterned so as to be formed opening；
Operation is performed etching to the substrate by the opening, so that first groove is formed in the first region, with
And second groove is formed in the second area, wherein the depth of first groove in the substrate is less than second groove in the lining
Depth in bottom；
Remove the sacrificial layer.
2, the method according to 1, which is characterized in that the etching operation includes:
The first etching processing is carried out so that first groove and second groove reach to the substrate by the opening
The predetermined depth of first groove；And
First area is at least blocked, the second etching processing is carried out to the second area of the substrate, so that second groove reaches
To the predetermined depth of second groove.
3, the method according to 1, which is characterized in that the dielectric layer include pad oxide layer and be located at liner oxygen
Silicon nitride layer in compound layer.
4, the method according to 1, which is characterized in that thickness of the sacrificial layer on first area after etching operation is big
In the thickness on second area.
5, the method according to 1, which is characterized in that after the etching operation, the first area of the substrate and
There are the sacrificial layers on two regions.
6, the method according to 1, which is characterized in that the substrate and the sacrificial layer in the etching operation
Etching selection ratio is greater than or equal to 6:1.
7, the method according to 6, which is characterized in that the dielectric layer include pad oxide layer and be located at liner oxygen
Silicon nitride layer in compound layer, and the etching of the pad oxide layer and the sacrificial layer is selected in the etching operation
It selects than being greater than or equal to 10:1,4:1 is greater than or equal to the etching selection ratio of the silicon nitride layer and the sacrificial layer.
8, the method according to 1, which is characterized in that the sacrificial layer is made of amorphous carbon.
9, the method according to 8, which is characterized in that the step of forming the sacrificial layer include:
One layer of amorphous carbon is deposited using hydrocarbon as reaction gas and using chemical vapor deposition process
Using as the sacrificial layer.
10, the method according to 8, which is characterized in that the thickness of the sacrificial layer is in the range of 50~100 nanometers.
11, the method according to 8, which is characterized in that the step of removing the sacrificial layer include:
The sacrificial layer is removed using cineration technics.
12, the method according to 1, which is characterized in that further include:
After removing the sacrificial layer, fills first groove and second groove and carries out chemical mechanical polish process,
To be respectively formed first groove structure member and second groove structure member.
13, the method according to 12, which is characterized in that first groove structure member is the first shallow trench isolation portion, with
And second groove structure member is the second shallow trench isolation portion.
14, the method according to 13, which is characterized in that the semiconductor device is imaging sensor, and first area is
The pixel region of pixel array is formed, second area is the logic region to form the processing circuit for pixel array.
15, the method according to 12, which is characterized in that the step of filling first groove and second groove includes:
Liner layer is formed on the wall of first groove and second groove；
Deposition of insulative material is to fill up first groove and second groove；And
Steam annealing processing is carried out to the insulating materials deposited.
16, the method according to 12, which is characterized in that further include:
After carrying out chemical mechanical polish process, the material of filling carve, to adjust first groove structure
The height of component and second groove structure member.
Although being described in detail by some specific embodiments of the example to the disclosure, the skill of this field
Art personnel it should be understood that above example merely to be illustrated, rather than in order to limit the scope of the present disclosure.It is disclosed herein
Each embodiment can in any combination, without departing from spirit and scope of the present disclosure.It is to be appreciated by one skilled in the art that can be with
A variety of modifications are carried out without departing from the scope and spirit of the disclosure to embodiment.The scope of the present disclosure is limited by appended claims
It is fixed.
Claims (10)
1. a kind of method for manufacturing semiconductor device characterized by comprising
Dielectric layer is formed in substrate, wherein the substrate includes first area and second area；
Sacrificial layer is formed on the dielectric layer；
The dielectric layer and the sacrificial layer are carried out being patterned so as to be formed opening；
Operation is performed etching to the substrate by the opening, so that first groove is formed in the first region, Yi Ji
Second groove is formed in second area, wherein the depth of first groove in the substrate is less than second groove in the substrate
Depth；And
Remove the sacrificial layer.
2. the method according to claim 1, wherein the etching operation includes:
The first etching processing is carried out so that first groove and second groove reach first to the substrate by the opening
The predetermined depth of groove；And
First area is at least blocked, the second etching processing is carried out to the second area of the substrate, so that second groove reaches the
The predetermined depth of two grooves.
3. the method according to claim 1, wherein the dielectric layer include pad oxide layer and be located at lining
Pad the silicon nitride layer on oxide skin(coating).
4. the method according to claim 1, wherein thickness of the sacrificial layer after etching operation on first area
Degree is greater than the thickness on second area.
5. the method according to claim 1, wherein after the etching operation, the first area of the substrate
With there are the sacrificial layers on second area.
6. the method according to claim 1, wherein to the substrate and the sacrifice in the etching operation
The etching selection ratio of layer is greater than or equal to 6:1.
7. according to the method described in claim 6, it is characterized in that, the dielectric layer include pad oxide layer and be located at lining
The silicon nitride layer on oxide skin(coating) is padded, and to the quarter of the pad oxide layer and the sacrificial layer in the etching operation
Erosion selection is greater than or equal to 4:1 than being greater than or equal to 10:1, to the etching selection ratio of the silicon nitride layer and the sacrificial layer.
8. the method according to claim 1, wherein the sacrificial layer is made of amorphous carbon.
9. according to the method described in claim 8, it is characterized in that, the step of forming the sacrificial layer includes:
One layer of amorphous carbon is deposited using hydrocarbon as reaction gas and using chemical vapor deposition process to make
For the sacrificial layer.
10. according to the method described in claim 8, it is characterized in that, range of the thickness of the sacrificial layer at 50~100 nanometers
It is interior.
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