CN109190748B

CN109190748B - CP test probe optimal path algorithm

Info

Publication number: CN109190748B
Application number: CN201811074043.9A
Authority: CN
Inventors: 陈湘芳
Original assignee: Shanghai Corelli Software Co ltd
Current assignee: Shanghai Corelli Software Co ltd
Priority date: 2018-09-14
Filing date: 2018-09-14
Publication date: 2021-09-17
Anticipated expiration: 2038-09-14
Also published as: CN109190748A

Abstract

The invention provides an algorithm of an optimal path of a CP test probe, which comprises the following steps: step one, representing a chip to be tested by coordinates according to a chip state diagram of a wafer; step two, clustering the chips marked in the step one by using an improved algorithm based on the combined hierarchical clustering; step three, the clustering ending distance is consistent with the probe distribution (N M) of the probe card, and step four, the coordinates of the upper left corner of each class are used as new coordinates of the class; and step five, finding the shortest path passing through all the classes through the ant colony algorithm, wherein the shortest path is the optimal path for the probe to move. The CP test probe optimal path algorithm greatly improves the efficiency of path setting, effectively reduces the labor cost and the test time, and improves the productivity. The algorithm combines a plurality of dynamic parameters to calculate the optimal path, thereby effectively reducing the number of times of the probe card contacting the wafer, improving the testing efficiency and reducing the influence on the product quality caused by the testing as much as possible.

Description

CP test probe optimal path algorithm

Technical Field

The invention relates to an algorithm for a CP test probe optimal path, and belongs to the field of chip testing.

Background

In the semiconductor packaging industry, CP testing is a contact testing that leaves traces of probe contacts on the wafer, which can affect the quality of the chip to some extent, and probe cards with probes are a test consumable, which directly affects the cost of testing. In addition, the effective and rapid test path can also reduce the test time to the maximum extent, thereby improving the productivity. The path optimization is mainly used in two conditions, namely re-testing of a partially failed chip and testing of a skipped bump failed chip, and the two conditions are mainly characterized in that the chips to be tested are distributed discretely rather than directly testing the whole wafer. The main purpose of path optimization is to reduce the times of the probe card contacting the chip, thereby improving the test efficiency; the contact to the chip which does not need to be tested is reduced, and the repeated contact of the chip which needs to be tested is avoided, so that the influence of the test on the quality of the chip is reduced. Different probe cards can test different numbers of chips in one-time contact test, the number of chips of a single wafer is also greatly different, and the distribution of the chips to be tested in the wafer is disordered. In the CP test industry, the existing test equipment provides a probe card test path setting, but there are two problems that the automatic test can only simply set the starting point of the path, and whether the setting is a horizontal zigzag or a vertical zigzag. In the free path setting, the path can only be manually set for the single wafer, the mode has low efficiency, and the Fab operator is not competent and can only be adjusted by an engineer, thereby greatly increasing the labor cost. Most importantly, the designed path is only relatively optimal, and the difference of experience and professional level of engineers directly influences the optimization degree of the path.

Disclosure of Invention

The present invention is directed to providing an algorithm for CP test probe optimal path to solve the above problems.

An algorithm for CP test probe optimal path, characterized by comprising the steps of:

step one, representing a chip to be tested by coordinates according to a chip state diagram of a wafer;

step two, clustering the chips marked in the step one by using an improved algorithm based on the combined hierarchical clustering;

step three, the clustering ending distance is consistent with the probe distribution (N M) of the probe card, (N, M) - > (length, width),

step four, taking the coordinates of the upper left corner of each class as new coordinates of the class;

and step five, finding the shortest path passing through all the classes through the ant colony algorithm, wherein the shortest path is the optimal path for the probe to move.

Further, the CP test probe optimal path algorithm of the present invention has the following features:

the improved algorithm of hierarchical clustering in the second step comprises the following steps:

step 2.1, regarding each chip to be tested as a class, and calculating the minimum distance between every two chips;

step 2.2, finding out two classes with the minimum distance, combining the two classes into a new class if the distances between all chips needing to be tested between the two classes are within (N, M), otherwise, marking the two classes as final classes, and enabling the two classes not to participate in subsequent cluster calculation;

step 2.3, recalculating the distances between the new class and all classes;

step 2.4, repeat step 2.2 and step 2.3 until all classes are identified as final classes.

Further, the CP test probe optimal path algorithm of the present invention further has the following features: and step six, controlling the probe to move and detect along the shortest path obtained in the step five.

Advantageous effects of the invention

The CP test probe optimal path algorithm greatly improves the efficiency of path setting, effectively reduces the labor cost and the test time, and improves the productivity. The algorithm combines a plurality of dynamic parameters to calculate the optimal path, thereby effectively reducing the number of times of the probe card contacting the wafer, improving the testing efficiency and reducing the influence on the product quality caused by the testing as much as possible.

Drawings

FIG. 1 is a schematic diagram of a position of a chip to be tested on a wafer;

fig. 2 is a schematic diagram of a clustering process.

Detailed Description

The following describes embodiments of the present invention with reference to the drawings.

Step one, representing a chip to be tested by coordinates according to a chip state diagram of a wafer, wherein a black circular area in the diagram represents a whole round crystal, and a white square in the black area represents the position of the chip to be tested, as shown in fig. 1;

step two, clustering the chips identified in the step one by using an improved algorithm based on combined hierarchical clustering;

and step three, the clustering ending distance is consistent with the probe distribution (N M) of the probe card. (N, M) - > (Length, Width). For example, if the probe card contacts 4 chips at a time, the end-of-cluster distance is (2, 2).

And step four, taking the coordinates of the upper left corner of each class as new coordinates of the class.

And step six, controlling the probe to move and detect along the shortest path obtained in the step five.

The improved algorithm of hierarchical clustering in the second step, as shown in fig. 2, includes the following steps:

step 2.3, recalculating the distances between the new class and all classes;

step 2.4, repeat steps 2.2 and 2.3 until all classes are identified as final classes, the result being shown in steps 2.5 and 2.6 of fig. 2.

The ant colony algorithm in the fifth step is a probability type algorithm used for finding the optimized path.

The finding of the shortest path by ants is due to pheromones and the environment, assuming that there are two paths leading from the nest to the food, the number of ants on the two paths is almost the same at the beginning: the ants return immediately after reaching the end point, the ants on the short-distance road have short round-trip time and high repetition frequency, the number of the ants in round trip in unit time is large, the left pheromone is also large, more ants can be attracted, and more pheromones can be left. While long distance paths are the opposite, so more and more ants gather on the shortest path.

Rule:

(1) sensing range

The ant observes a grid world with a speed radius of typically 3 and an observable and moving range of 3x3 grids.

(2) Environmental information

The environment where ants are located is provided with obstacles, other ants and pheromones, wherein the pheromones comprise food pheromones (left by ants finding food) and nest pheromones (left by ants finding nests), and the pheromones disappear at a certain rate.

(3) Rules of foraging

Ants search for food in the perception range, and if the ants perceive the food, the food will pass; otherwise, the ant walks to a place with a large number of pheromones, and each ant makes a mistake with a small probability, but does not move to the direction with the largest number of pheromones. Ants have similar rules for finding their nests, and only respond to nest pheromones.

(4) Rules of movement

The ants move in the direction of the most pheromones, and when no pheromone is guided around, the ants move inertially according to the original movement direction. But also remember the most recently walked point to prevent in-situ rotation.

(5) Rule of avoiding obstacles

When the ant has a barrier in the moving direction, other directions are randomly selected; when the pheromone is guided, the pheromone moves according to the foraging rule.

(6) Rules for distributing pheromones

When a food or nest is just found, the ants emit the most pheromones; as one walks away, the emitted pheromones will gradually decrease.

Compared with other optimization algorithms, the ant colony algorithm has the following characteristics:

(1) and a positive feedback mechanism is adopted, so that the search process is continuously converged and finally approaches to an optimal solution.

(2) Each individual can change the surrounding environment by releasing the pheromone, and each individual can sense the real-time change of the surrounding environment, and the individuals communicate indirectly through the environment.

(3) The searching process adopts a distributed computing mode, and a plurality of individuals simultaneously carry out parallel computing, so that the computing power and the operating efficiency of the algorithm are greatly improved.

(4) The heuristic probability search mode is not easy to fall into local optimum and is easy to find out the global optimum solution.

The method provided by the invention can effectively improve the testing speed and reduce the times of the probe card contacting the chip through the transformation method under the existing system condition.

1. The algorithm greatly improves the efficiency of path setting, effectively reduces the labor cost and the idle time of the test equipment, and improves the productivity.

2. The algorithm combines a plurality of dynamic parameters to calculate the optimal path, thereby effectively reducing the number of contact chips of the probe card. Thereby improving the testing efficiency and reducing the influence on the product quality caused by the testing as much as possible.

Claims

1. A CP test probe optimal path method is characterized by comprising the following steps:

step two, clustering the chips marked in the step one by using an improved algorithm based on the merged hierarchical clustering, wherein the improved algorithm based on the merged hierarchical clustering comprises the following steps:

step 2.3, recalculating the distances between the new class and all classes;

step 2.4, repeating step 2.2 and step 2.3 until all classes are identified as final classes;

step three, the clustering ending distance is consistent with the probe distribution N M of the probe card, (N, M) - > (length, width),

2. The CP method for testing an optimal path of a probe according to claim 1, further comprising: