CN109190281A - A kind of multi-core DSP platform algorithm development method and device - Google Patents
A kind of multi-core DSP platform algorithm development method and device Download PDFInfo
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- G06F30/32—Circuit design at the digital level
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Abstract
The invention discloses a kind of multi-core DSP platform algorithm development method and device, this method includes being built on algorithm simulating platform to the first algorithm of multi-core DSP according to user, obtaining N number of accounting method module；Generating algorithm code and drive code set, and be integrated into pre-stored skeleton code, obtain engineering code；Engineering code is compiled, N number of executable file is obtained；It will be in the non-volatile memory cells of loading of executed file to multi-core DSP.Compared with the existing technology, during the exploitation and deployment of multi-core DSP platform algorithm, automatically generating, compile and downloading for code is realized, the development difficulty of algorithm personnel is greatly reduced, increases the iteration speed of algorithm on hardware platform.
Description
Technical field
The present invention relates to embedded system technology field, more particularly to a kind of multi-core DSP platform algorithm development method and
Device.
Background technique
The platform algorithm development of existing multi-core DSP (Digital Signal Processing, Digital Signal Processing),
Common mode is that building and emulating for algorithm is carried out on algorithm simulating platform；It builds after finishing, in IDE environment
The generation of algorithm is carried out under (Integrated Development Environment, Integrated Development Environment) using C/C++ code
Code is realized, and is finally compiled and is downloaded using IDE environment.
Inventor in the research process of the prior art to having found, in the development process of platform algorithm, algorithm platform is taken
Founding a capital, it is manually implemented by user to realize with the code of IDE environment, causes the development rate to multi-core DSP platform slow, low efficiency.
Summary of the invention
In order to solve the above technical problems, the embodiment of the invention provides a kind of multi-core DSP platform algorithm development method and dresses
It sets, technical solution is as follows:
A kind of multi-core DSP platform algorithm development method, comprising:
The first algorithm of the multi-core DSP is built on algorithm simulating platform according to user, obtains N number of accounting method mould
Block, N are positive integer, are communicated between the different accounting method modules by IPC communication module, in the accounting method module
It is integrated with drive module；
Generating algorithm code and drive code set, and be integrated into pre-stored skeleton code, engineering code is obtained, it is described
Algorithmic code is corresponding with the algorithm in N number of accounting method module, and the drive code set is corresponding with the drive module；
The engineering code is compiled, N number of executable file, the executable file and the accounting method mould are obtained
Block corresponds；
It will be in the non-volatile memory cells of the loading of executed file to the multi-core DSP.
Preferably, it by before in the non-volatile memory cells of the loading of executed file to the multi-core DSP, also wraps
It includes:
It will be in the random access memory cell of the loading of executed file to the multi-core DSP；
Using identical data source, the algorithm is obtained in the simulation result and the multicore of the algorithm simulating platform
Operation result in DSP；
Judge whether the simulation result is identical as the operation result；
If so, by the non-volatile memory cells of the loading of executed file to the multi-core DSP.
Preferably, when the simulation result is identical as the operation result, by the loading of executed file to described
Before in the non-volatile memory cells of multi-core DSP, further includes:
Obtain the runing time of the multi-core DSP；
Judge the runing time whether in preset time range；
If so, by the non-volatile memory cells of the loading of executed file to the multi-core DSP.
Preferably, when the simulation result and the operation result be not identical or when the runing time is not described default
When in time range, further includes:
The second algorithm of the multi-core DSP is built on the algorithm simulating platform according to user, obtains updated N
A accounting method module, and N number of accounting method module is replaced with updated N number of accounting method module.
Preferably, generating algorithm code and drive code set, and be integrated into pre-stored skeleton code, obtain engineering generation
Code, comprising:
The Code Generator for calling the algorithm simulating platform generates the algorithmic code；
The drive code set is generated, and the drive code set is integrated into the skeleton code；
The algorithmic code is integrated into the skeleton code for having integrated the drive code set, the engineering code is obtained.
A kind of multi-core DSP platform algorithm development device, comprising:
First acquisition unit, for being built on algorithm simulating platform to the first algorithm of the multi-core DSP according to user,
N number of accounting method module is obtained, N is positive integer, it is communicated between the different accounting method modules by IPC communication module,
Drive module is integrated in the accounting method module；
First processing units are used for generating algorithm code and drive code set, and are integrated into pre-stored skeleton code,
Obtain engineering code, the algorithmic code is corresponding with the algorithm in N number of accounting method module, the drive code set with it is described
Drive module is corresponding；
Compilation unit obtains N number of executable file, the executable file for being compiled to the engineering code
It is corresponded with the accounting method module；
First download unit, for the non-volatile memory cells by the loading of executed file to the multi-core DSP
In.
Preferably, further includes:
Second download unit, for the non-volatile memory cells by the loading of executed file to the multi-core DSP
In before, will be in the random access memory cell of the loading of executed file to the multi-core DSP；
The second processing unit obtains the algorithm in the imitative of the algorithm simulating platform for using identical data source
Operation result in true result and the multi-core DSP；
First judging unit, for judging whether the simulation result is identical as the operation result, if so, can by described in
File download is executed into the non-volatile memory cells of the multi-core DSP.
Preferably, further includes:
Second acquisition unit is the simulation result and the operation result for the result when first judging unit
When identical, before in the non-volatile memory cells of the loading of executed file to the multi-core DSP, the multicore is obtained
The runing time of DSP；
Second judgment unit, for whether in preset time range to judge the runing time, if so, being held described
Style of writing part is downloaded in the non-volatile memory cells of the multi-core DSP.
Preferably, further includes:
Third processing unit, for when the simulation result and the operation result it is not identical or when the runing time not
When in the preset time range, the second algorithm of the multi-core DSP is taken on the algorithm simulating platform according to user
It builds, obtains updated N number of accounting method module, and N number of accounting method mould is replaced with updated N number of accounting method module
Block.
Preferably, the first processing units, comprising:
First generation subelement generates the algorithm generation for calling the Code Generator of the algorithm simulating platform
Code；
Second generates subelement, is integrated into the frame generation for generating the drive code set, and by the drive code set
In code；
Integrated subelement is obtained for the algorithmic code to be integrated into the skeleton code for having integrated the drive code set
To the engineering code.
Technical solution provided by the invention passes through after user builds multi-core DSP progress algorithm on algorithm simulating platform
Be arranged script call relation, can by the way of one-touch completion code generation, compiling and downloading.Relative to existing skill
Art realizes automatically generating, compile and downloading for code, greatly during the exploitation and deployment of multi-core DSP platform algorithm
The development difficulty for reducing algorithm personnel increases the iteration speed of algorithm on hardware platform.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention without any creative labor, may be used also for those of ordinary skill in the art
To obtain other drawings based on these drawings.
Fig. 1 is a kind of a kind of flow diagram of multi-core DSP platform algorithm development method provided by the embodiment of the present invention；
Fig. 2 is a kind of another process signal of multi-core DSP platform algorithm development method provided by the embodiment of the present invention
Figure；
Fig. 3 is the structural schematic diagram that IPC communication is carried out between accounting method module provided by the embodiment of the present invention；
Fig. 4 is a kind of a kind of structural schematic diagram of multi-core DSP platform algorithm development device provided by the embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that the described embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on this
Embodiment in invention, every other reality obtained by those of ordinary skill in the art without making creative efforts
Example is applied, shall fall within the protection scope of the present invention.
Referring to Fig. 1, Fig. 1 is a kind of a kind of reality of multi-core DSP platform algorithm development method provided in an embodiment of the present invention
Existing flow chart, this method comprises:
Step S101, the first algorithm of multi-core DSP is built on algorithm simulating platform according to user, obtains N number of accounting
Method module.
Wherein, N is positive integer.
By IPC communication, (Inter-Process Communication leads between process between different accounting method modules
Letter) module communicated.When specific implementation, user calls the IPC communication module in IPC Driver Library, and in IPC communication module
Parameter configured, to realize the communication between different IPs algoritic module.IPC communication module is realizing different IPs algoritic module
Between communication when, the algorithm fusion between each monokaryon can be got up by the way of cabling connection, in model level structure
At a complete algorithm.
Algorithm simulating platform in the present embodiment can be matlab or simulink, be obtained based on algorithm simulating platform
Accounting method module can be graphical module (simulink), be also possible to function module (matlab).
In practical application, when building to multi-core DSP progress algorithm, user according to demand both can be in multi-core DSP
All cores build algorithm, only can also build algorithm to the part core in multi-core DSP.
When specifically building, user needs to need the core built to build respectively to each, every in the core for needing to build
Each of a core runs an algorithm, and the needs of building of monokaryon algorithm carry out on specific frame module, build after algorithm
Core is referred to as accounting method module.
In practical application, according to demand, user both can in each accounting method module Integrate Design, can also be only
The Integrate Design in the accounting method module of part.
Drive module is integrated in accounting method module, the interface of drive module can be defeated with the algorithm in accounting method module
Enter output interface to be coupled.Drive module is based on interface, is driven and customized according to the peripheral hardware of different multi-core DSP platforms
, meet the encapsulation of the interface driver of modeling software platform modeling specification.
Drive module, which has been reserved, needs the parameter and setting modified, can when user is from peripheral hardware Driver Library calling driver module
Drive module is added in accounting method module in a manner of modifying using parameter and configure setting.Drive module is supported imitative in algorithm
Straight simulation is run on true platform, and the language of driving can be c/c++ code language, be also possible to packaged library file, such as
Lib file.
In practical application, for different hardware, the drive module of preset quantity can be provided previously, user directly carries out
Calling；Can also provide simultaneously voluntarily makes the template that driving is packaged into module when user has new package requirements
With preceding carrying out the configuration of module parameter and setting and carry out the encapsulation of module.
Step S102, generating algorithm code and drive code set, and be integrated into pre-stored skeleton code, obtain engineering
Code.
Algorithmic code is corresponding with the algorithm in N number of accounting method module, and drive code set is corresponding with drive module.
In practical application, step S102 can be subdivided into three steps when realizing, as follows:
Using scripting language or tool, the Code Generator of algorithm simulating platform, generating algorithm code, such as c/ are called
C++ code；
Using scripting language or tool, drive code set corresponding with drive module is generated, drive code set is integrated into pre-
In the skeleton code first stored, or by drive code set be integrated by skeleton code generate library file in；
Wherein, pre-stored skeleton code can be c/c++ code, and the library file that skeleton code generates can be lib
File, the function of script include the replacement of filename, the movement of file, the integration of duplicated code, header file include, library file
Calling, global variable statement.
Using the function of scripting language or script, algorithmic code is integrated in the skeleton code of integrated driving code, at
For a complete engineering code.
Wherein, the function of script include the replacement of filename, the movement of file, library file calling.
Scripting language in above-mentioned steps can be bat, m, tlc, python or java script.
Step S103, engineering code is compiled, obtains N number of executable file, executable file and accounting method module
It corresponds.
Using the function of scripting language and script, the corresponding IDE tools chain such as CCS of multi-core DSP platform is called, engineering is compiled
For code to generate executable file, each accounting method module generates individual executable file.
Wherein, scripting language can be bat/m/python/java script, the function of script include tools chain selection and
It calls, the deletion of intermediate file.
It should be noted that when specific implementation, can on algorithm simulating platform inlet porting script, when needing using foot
This language or tool generating algorithm code, drive code set or when being compiled to engineering code, can be called by entrance script
Corresponding script such as calls the script of generating algorithm code with generating algorithm code.
It step S104, will be in the non-volatile memory cells of loading of executed file to multi-core DSP.
In the present embodiment, step S102- step S104 is realized automatically by multi-core DSP platform algorithm development device,
Step S102- step S104 is realized using scripting language or tool by multi-core DSP platform algorithm development device.
Technical solution provided in this embodiment is led to after user builds multi-core DSP progress algorithm on algorithm simulating platform
Cross setting script call relation, can by the way of one-touch completion code generation, compiling and downloading.Relative to existing skill
Art realizes automatically generating, compiling for code, and realize automatically during the exploitation and deployment of multi-core DSP platform algorithm
The deployment for downloading to realize the algorithm on multi-core DSP of code, greatly reduces the development difficulty of algorithm personnel, increases
The iteration speed of algorithm on hardware platform is added.
On the basis of a upper embodiment, in order to realize the consistency comparison of algorithm model and multi-core DSP, reference Fig. 2 is
Another flow chart of a kind of multi-core DSP platform algorithm development method provided by the invention, wherein extremely by loading of executed file
Before in the non-volatile memory cells of multi-core DSP, further includes:
It step S201, will be in the random access memory cell of loading of executed file to multi-core DSP.
Step S202, using identical data source, algorithm is obtained in the simulation result and multi-core DSP of algorithm simulating platform
Operation result.
Step S203, judge whether simulation result is identical as operation result, it is no to then follow the steps if executing step S204
S206。
Step S204, the runing time of multi-core DSP is obtained.
Step S205, whether in preset time range to judge runing time, if so, executing step S207, otherwise execute
Step S206.
Consistency comparison in the present embodiment includes the consistency comparison of quick uniformity test and runing time performance,
Wherein step S202 and step S203 are accomplished that the quick uniformity test to algorithm model and multi-core DSP, step S204 with
Step S205 is accomplished that the consistency comparison of runing time performance.
Need to illustrate when, not fully limit in the present embodiment and execute sequence between step S202 and step S204.
I.e. in the present embodiment step S202 can both be executed before step S204, and in other embodiments, step S202 can also be with
It executes after step s 204.
Step S206, the second algorithm of multi-core DSP is built on algorithm simulating platform according to user, is obtained updated
N number of accounting method module, and N number of accounting method module is replaced with updated N number of accounting method module.
When consistency comparison does not meet expected, user is taken according to what consistency compared as a result, updating in accounting method module
The algorithm built, until consistency comparison meets expection.
It step S207, will be in the non-volatile memory cells of loading of executed file to multi-core DSP.
It, will be in the non-volatile memory cells of loading of executed file to multi-core DSP when consistency comparison meets expected.
In practical application, by loading of executed file into multi-core DSP, including by loading of executed file to multi-core DSP
Random access memory cell neutralization will be in the non-volatile memory cells of loading of executed file to multi-core DSP.
Wherein, random access memory cell can be RAM, and non-volatile memory cells can be FLASH.
Embodiment corresponding to Fig. 2 is illustrated combined with specific embodiments below:
It is based on KeyStone framework that multi-core DSP platform, which selects TMS320C6678, TMS320C6678 (abbreviation DSP6678),
8 core dsp processors, the frequency of each CorePac core is up to 1.25GHz, powerful fixed point and floating-point operation ability are provided,
Chip interior is integrated with the peripheral hardwares such as Multicore Navigator, RapidIO, gigabit Ethernet and EDMA simultaneously.
Algorithm simulating platform selects simulink environment, and matlab version selects matlab 2017b.
The process of specific algorithm exploitation is as follows:
Step 1: building algorithm model in simulink, building for the algorithm of each core individually carries out, and monokaryon is calculated
Method needs to carry out in specific frame, writes finish in advance according to the multicore starting of DSP6678 and communication mechanism in frame, directly
It drags model and adds algorithm.
It is assumed that user needs in core0-core7 to build algorithm respectively, for example, what core0 built is data Allocation Algorithms,
What core2 was responsible for is the parsing of CAN interface data, and what core3 was responsible for is the reception of Ethernet data, and core7 is responsible for driving LED
The mark of equal carry out state, core1, core4, core5 and core6 are responsible for carrying out the processing of data, such as core1 is filtered
Processing, core4 carry out windowing algorithm operation.
Step 2: using IPC communication module carry out multicore connection, IPC communication module is encapsulated, by each core module it
Between the mode of line carry out IPC communication.As shown in figure 3, if core1-core7 carries out the interaction of data with core0, it will
Core1-core7 is connected with core0 respectively, meanwhile, core3 and core6 can also be interacted with core7, such purpose
It is the interaction by data, (algorithm setting core7 is responsible for the operating condition between core7 real time monitoring core3 and core6
Condition monitoring).
Step 3: algorithm and peripheral drive module being integrated, peripheral drive module is the DSP6678 platform selected
Drive the modularized encapsulation carried out.
In practical application, DSP6678 platform is in advance by UDP's (User Datag Protocol, User Datagram Protocol)
It sends and receivees and is encapsulated as UDP_rcv and UDP_send module, onboard LED is encapsulated as LED module, CAN receiving module is sealed
Dress is CAN_rcv module, and user will be directly attached if necessary to module more than use with upper module and any core, when
It so is also required to be configured accordingly, a block diagram can be provided with upper module and selected for user.With UDP_rcv and UDP_send mould
For block, when user's dragging UDP_rcv module, need to input corresponding IP address and port.
Step 4: using tlc scripting language, configuration simulink generates the rule of code, generating algorithm code, Ge Gehe
Between code generate respectively.
Step 5: using bat scripting language, drive module is generated to the C code of drive module, and carry out with skeleton code
Integration, skeleton code is the principal function code write in advance.
Step 6: using bat scripting language, algorithmic code is integrated into the skeleton code in step 5, generation one is complete
At engineering code.
Step 7: calling the Compile toolchain of IED environment CCS using bat script, generate 8 executable files, 8 can hold
Style of writing part respectively corresponds 8 cores of DSP6678.
Step 8: calling the download tool chain of CCS compiler using bat script, downloaded to by JTAG or serial ports
In the random access memory cell of DSP6678 platform.
It should be pointed out that step 3- step 8 is automatic running, i.e., after the completion of complete algorithm is built,
Siminlik uses a compiling download button, and executable text is finally generated in DSP6678 platform random access memory cell
Part.
Step 9: being emulated on simulink using algorithm, data source is sent to algorithm model by simulink
The data and emulation data returned with DSP6678 platform, DSP6678 carry out real-time uniformity comparison, and will transport in DSP6678
Capable time performance (i.e. time used in uniformity comparison) uploads, result that user compares according to consistency and algorithm when
Between runnability, algorithm model is iterated.
Proof of algorithm speed is greatly improved by the way of comparing in real time.
Step 10: when algorithm iteration maturation, using non-volatile memory cells download module, loading of executed file being arrived
In the non-volatile memory cells of DSP6678.
Referring to Fig. 4, a kind of structure that Fig. 4 is multi-core DSP platform algorithm development device provided in an embodiment of the present invention is shown
Be intended to, the course of work of each module in the structural schematic diagram referring to Fig.1 in corresponding embodiment method implementation procedure, the dress
It sets and includes:
First acquisition unit 410, for being built on algorithm simulating platform to the first algorithm of multi-core DSP according to user,
N number of accounting method module is obtained, N is positive integer, is communicated between different accounting method modules by IPC communication module, is calculated
Drive module is integrated in method module；
First processing units 420 are used for generating algorithm code and drive code set, and are integrated into pre-stored skeleton code
In, engineering code is obtained, algorithmic code is corresponding with the algorithm in N number of accounting method module, and drive code set is opposite with drive module
It answers；
Preferably, first processing units 420 include:
First generates subelement, for calling the Code Generator of algorithm simulating platform, generating algorithm code；
Second generates subelement, is integrated into skeleton code for generating drive code set, and by drive code set；
Integrated subelement obtains work for being integrated into algorithmic code in the skeleton code for having integrated the drive code set
Range code.
Compilation unit 430 obtains N number of executable file, executable file and accounting for being compiled to engineering code
Method module corresponds；
First download unit 440, for will be in the non-volatile memory cells of loading of executed file to multi-core DSP.
In order to realize the consistency comparison of algorithm model and multi-core DSP, further includes:
Second download unit will for by before in the non-volatile memory cells of loading of executed file to multi-core DSP
Loading of executed file is into the random access memory cell of multi-core DSP；
The second processing unit, for use identical data source, obtain algorithm algorithm simulating platform simulation result and
Operation result in random access memory cell；
First judging unit, for judging whether simulation result is identical as operation result.
Second acquisition unit, for when the result of the first judging unit be simulation result it is identical as operation result when, can
Before file download is executed into the non-volatile memory cells of multi-core DSP, the runing time of multi-core DSP is obtained；
Second judgment unit, for whether in preset time range to judge runing time, if so, by under executable file
It is loaded onto the non-volatile memory cells of multi-core DSP.
Third processing unit, for when the simulation result and the operation result it is not identical or when running between not pre-
If when in time range, being built on algorithm simulating platform to the second algorithm of multi-core DSP according to user, obtaining updated N
A accounting method module, and N number of accounting method module is replaced with updated N number of accounting method module.
Technical solution provided in this embodiment is led to after user builds multi-core DSP progress algorithm on algorithm simulating platform
Cross setting script call relation, can by the way of one-touch completion code generation, compiling and downloading.Relative to existing skill
Art realizes automatically generating, compiling for code, and realize automatically during the exploitation and deployment of multi-core DSP platform algorithm
The deployment for downloading to realize the algorithm on multi-core DSP of code, greatly reduces the development difficulty of algorithm personnel, increases
The iteration speed of algorithm on hardware platform is added.
Description and claims of this specification and term " first ", " second ", " third " " in above-mentioned attached drawing
The (if present)s such as four " are to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should manage
The data that solution uses in this way are interchangeable under appropriate circumstances, so that the embodiment of the present invention described herein for example can be to remove
Sequence other than those of illustrating or describe herein is implemented.In addition, term " includes " and " having " and theirs is any
Deformation, it is intended that cover it is non-exclusive include, for example, containing the process, method of a series of steps or units, system, production
Product or equipment those of are not necessarily limited to be clearly listed step or unit, but may include be not clearly listed or for this
A little process, methods, the other step or units of product or equipment inherently.
For device or system embodiments, since it essentially corresponds to embodiment of the method, thus related place referring to
The part of embodiment of the method illustrates.Device or system embodiment described above is only schematical, wherein described
Unit may or may not be physically separated as illustrated by the separation member, and component shown as a unit can be with
It is or may not be physical unit, it can it is in one place, or may be distributed over multiple network units.It can
It is achieved the purpose of the solution of this embodiment with selecting some or all of the modules therein according to the actual needs.This field is common
Technical staff can understand and implement without creative efforts.
In several embodiments provided by the present invention, it should be understood that disclosed system, device and method are not having
It has more than in the spirit and scope of the present invention, can realize in other way.Current embodiment is a kind of demonstration
Example, should not be taken as limiting, given particular content should in no way limit the purpose of the present invention.For example, the unit or
The division of subelement, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple lists
First or multiple subelements combine.In addition, multiple units can with or component may be combined or can be integrated into another and be
System, or some features can be ignored or not executed.
In addition, described system, the schematic diagram of device and method and different embodiments, without departing from the scope of the present invention
It is interior, it can be with other systems, module, techniques or methods combination or integrated.Another point, shown or discussed mutual coupling
It closes or direct-coupling or communication connection can be through some interfaces, the indirect coupling or communication connection of device or unit can be with
It is electrically mechanical or other forms.
The above is only a specific embodiment of the invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (10)
1. a kind of multi-core DSP platform algorithm development method characterized by comprising
The first algorithm of the multi-core DSP is built on algorithm simulating platform according to user, obtains N number of accounting method module, N is
Positive integer is communicated between the different accounting method modules by IPC communication module, is integrated in the accounting method module
Drive module；
Generating algorithm code and drive code set, and be integrated into pre-stored skeleton code, obtain engineering code, the algorithm
Code is corresponding with the algorithm in N number of accounting method module, and the drive code set is corresponding with the drive module；
The engineering code is compiled, N number of executable file, the executable file and the accounting method module one are obtained
One is corresponding；
It will be in the non-volatile memory cells of the loading of executed file to the multi-core DSP.
2. the method according to claim 1, wherein by the loading of executed file to the multi-core DSP
Before in non-volatile memory cells, further includes:
It will be in the random access memory cell of the loading of executed file to the multi-core DSP；
Using identical data source, the algorithm is obtained in the simulation result and the multi-core DSP of the algorithm simulating platform
Operation result；
Judge whether the simulation result is identical as the operation result；
If so, by the non-volatile memory cells of the loading of executed file to the multi-core DSP.
3. according to the method described in claim 2, it is characterized in that, when the simulation result is identical as the operation result,
Before in the non-volatile memory cells of the loading of executed file to the multi-core DSP, further includes:
Obtain the runing time of the multi-core DSP；
Judge the runing time whether in preset time range；
If so, by the non-volatile memory cells of the loading of executed file to the multi-core DSP.
4. according to the method described in claim 3, it is characterized in that, when the simulation result and the operation result it is not identical or
When the runing time is not in the preset time range, further includes:
The second algorithm of the multi-core DSP is built on the algorithm simulating platform according to user, obtains updated N number of core
Algoritic module, and N number of accounting method module is replaced with updated N number of accounting method module.
5. the method according to claim 1, wherein generating algorithm code and drive code set, and being integrated into advance
In the skeleton code of storage, engineering code is obtained, comprising:
The Code Generator for calling the algorithm simulating platform generates the algorithmic code；
The drive code set is generated, and the drive code set is integrated into the skeleton code；
The algorithmic code is integrated into the skeleton code for having integrated the drive code set, the engineering code is obtained.
6. a kind of multi-core DSP platform algorithm development device characterized by comprising
First acquisition unit is obtained for being built on algorithm simulating platform to the first algorithm of the multi-core DSP according to user
N number of accounting method module, N are positive integer, are communicated between the different accounting method modules by IPC communication module, described
Drive module is integrated in accounting method module；
First processing units are used for generating algorithm code and drive code set, and are integrated into pre-stored skeleton code, obtain
Engineering code, the algorithmic code is corresponding with the algorithm in N number of accounting method module, the drive code set and the driving
Module is corresponding；
Compilation unit obtains N number of executable file, the executable file and institute for being compiled to the engineering code
State accounting method module one-to-one correspondence；
First download unit, for will be in the non-volatile memory cells of the loading of executed file to the multi-core DSP.
7. device according to claim 6, which is characterized in that further include:
Second download unit, for by it in the non-volatile memory cells of the loading of executed file to the multi-core DSP
Before, it will be in the random access memory cell of the loading of executed file to the multi-core DSP；
The second processing unit obtains the algorithm in the emulation knot of the algorithm simulating platform for using identical data source
Operation result in fruit and the multi-core DSP；
First judging unit, for judging whether the simulation result is identical as the operation result, if so, by described executable
File download is into the non-volatile memory cells of the multi-core DSP.
8. device according to claim 7, which is characterized in that further include:
Second acquisition unit is that the simulation result is identical as the operation result for the result when first judging unit
When, before in the non-volatile memory cells of the loading of executed file to the multi-core DSP, obtain the multi-core DSP
Runing time；
Second judgment unit, for whether in preset time range to judge the runing time, if so, by the executable text
Part is downloaded in the non-volatile memory cells of the multi-core DSP.
9. device according to claim 8, which is characterized in that further include:
Third processing unit, for when the simulation result and the operation result it is not identical or when the runing time not in institute
When stating in preset time range, the second algorithm of the multi-core DSP is built on the algorithm simulating platform according to user, is obtained
N number of accounting method module is replaced to updated N number of accounting method module, and with updated N number of accounting method module.
10. device according to claim 6, which is characterized in that the first processing units, comprising:
First generation subelement generates the algorithmic code for calling the Code Generator of the algorithm simulating platform；
Second generates subelement, is integrated into the skeleton code for generating the drive code set, and by the drive code set；
Integrated subelement obtains institute for the algorithmic code to be integrated into the skeleton code for having integrated the drive code set
State engineering code.
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