CN109189476A - The control stream of FPGA executes method, apparatus, equipment and medium - Google Patents
The control stream of FPGA executes method, apparatus, equipment and medium Download PDFInfo
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- CN109189476A CN109189476A CN201811094593.7A CN201811094593A CN109189476A CN 109189476 A CN109189476 A CN 109189476A CN 201811094593 A CN201811094593 A CN 201811094593A CN 109189476 A CN109189476 A CN 109189476A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30065—Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
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Abstract
Method, apparatus, equipment and medium are executed the invention discloses the control stream of FPGA a kind of, and the step of this method includes: to receive the cycle-index of incoming data content and routine call logic, and obtain routine call logic；The routine call logic of first circulation number is continuously performed to carry out calculation process, generating process data to data content；When quantity summation is less than nominal cycle number, update cycle-index, and process data and cycle-index are transmitted to next FPGA device,, according to cycle-index and nominal cycle number, the routine call logic of second circulation number is continuously performed to process data using next FPGA device；Receive and process incoming new data content.This method improves FPGA device under big data environment to the treatment effeciency of overall data.In addition, the present invention also provides the control stream executive device of FPGA a kind of, equipment and medium, beneficial effect are same as above.
Description
Technical field
The present invention relates to data processing field, more particularly to a kind of FPGA control stream execute method, apparatus, equipment and
Medium.
Background technique
Currently FPGA device is being carried out in use, being usually to control the form control operation program of stream and execute, with reality
Now to the processing of data flow.Control stream refers to the sequence by certain logic arrangement program element, executed with this determination procedure.
Usually, it is control circulation frequently with a kind of program control form that circulation, which executes (while_loop), is being passed through
When the mode that circulation executes handles data stream, control stream would generally control single FPGA according to preset loop number and set
Standby circulation executes in loop structure body, for carrying out a series of routine call logic of relevant treatments, loop structure to data stream
Generated output data after body completely executes each time, is required to input number when executing as the loop structure body next time
According to, until after reaching nominal cycle number, the processing of complete paired data stream.
But due to carrying out the data of circulation execution in the environment of the processing of the big datas such as the cloud computing of current mainstream
Stream total amount is usually relatively bulky, when only controlling circular treatment of the single FPGA device execution to data flow according to control stream,
The data volume of the can be carried out circular treatment of single is limited, therefore lower for the adaptibility to response of mass data, and then is difficult to ensure
FPGA device is under big data environment to the treatment effeciency of overall data.
It can be seen that the control stream execution method of FPGA a kind of is provided, with opposite raising FPGA device in big data environment
Under to the treatment effeciency of overall data, be those skilled in the art's urgent problem to be solved.
Summary of the invention
The object of the present invention is to provide the control streams of FPGA a kind of to execute method, apparatus, equipment and medium, with opposite raising
FPGA device is under big data environment to the treatment effeciency of overall data.
In order to solve the above technical problems, the present invention provides the control stream execution method of FPGA a kind of, which is characterized in that packet
It includes:
The cycle-index of incoming data content and routine call logic is received, and obtains routine call logic；
The routine call logic of first circulation number is continuously performed to carry out calculation process, generating process number to data content
According to；Wherein, the quantity summation of first circulation number and cycle-index is less than or equal to the nominal cycle of routine call logic
Number；
When quantity summation is less than nominal cycle number, cycle-index is updated, and by process data and cycle-index
It is transmitted to next FPGA device, to utilize next FPGA device according to cycle-index and nominal cycle number, to process
Data continuously perform the routine call logic of second circulation number；
Receive and process incoming new data content.
Preferably, in the routine call logic for continuously performing first circulation number to carry out calculation process to data content,
After generating process data, this method further comprises:
When quantity summation is equal to nominal cycle number, process data is set as result data.
Preferably, the cycle-index of incoming data content and routine call logic is being received, and is obtaining program tune
Before logic, this method further comprises:
Judge whether current FPGA device meets preset condition；
If it is, executing the cycle-index for receiving incoming data content and routine call logic, and obtain journey
The step of sequence calling logic.
Preferably, preset condition is specially and is in idle condition.
Preferably, routine call logic is obtained specifically:
It obtains and first passes through the routine call logic that OpenCL SDK writes and is burned onto PROM in advance.
Preferably, after process data is set as result data, this method further comprises:
Result data is transmitted to user equipment, to record by user equipment and show result data.
In addition, the present invention also provides the control stream executive devices of FPGA a kind of, comprising:
Data reception module for receiving the cycle-index of incoming data content and routine call logic, and obtains
Program fetch calling logic；
Circular treatment module, for continuously performing the routine call logic of first circulation number to transport to data content
Calculation processing, generating process data；Wherein, first circulation number and the quantity summation of cycle-index are less than or equal to routine call
The nominal cycle number of logic；
Data transmission module, for when quantity summation is less than nominal cycle number, updating cycle-index, and by process
Data and cycle-index are transmitted to next FPGA device, with using next FPGA device according to cycle-index and specified
Cycle-index continuously performs the routine call logic of second circulation number to process data；
New data respond module, for receiving and processing incoming new data content.
Preferably, which further comprises:
As a result setting module, for when quantity summation is equal to nominal cycle number, process data to be set as number of results
According to.
In addition, the present invention also provides the control streams of FPGA a kind of to execute equipment, comprising:
Memory, for storing computer program；
Processor, when for executing computer program the step of the realization such as control stream execution method of above-mentioned FPGA.
In addition, being stored with meter on computer readable storage medium the present invention also provides a kind of computer readable storage medium
Calculation machine program, when computer program is executed by processor the step of the realization such as control stream execution method of above-mentioned FPGA.
The control stream execution method of FPGA provided by the present invention is received by current FPGA device in incoming data
The cycle-index of appearance and routine call logic, and then after obtaining the routine call logic, continuous logarithmic is executed according to content
The routine call logic of first circulation number, generating process data.First circulation number and the quantity summation of cycle-index are small
In or equal to nominal cycle number of routine call logic at the end of recycling execution.When the program tune for executing first circulation number
Nominal cycle number has not yet been reached with the cycle-index after logic, i.e., when the circulation of routine call logic executes not yet completion,
Process data and current cycle-index are transmitted to next FPGA device, and using next FPGA device according to working as
Preceding cycle-index and nominal cycle number continues the routine call logic that second circulation number is executed to process data.
And current FPGA device continues to after process data is transmitted to next FPGA device and handles incoming new data
Content.This method is that multiple FPGA devices progress, each FPGA device are distributed in the operation that circulation is executed routine call logic
After receiving data content, the calculation process of certain cycle-index is only carried out to data content by routine call logic, i.e., will
Result data is transferred to next FPGA device and carries out subsequent circular treatment, and continues to and respond new data content, because
For through single FPGA device cyclic program calling logic, this method has been shared by multiple FPGA devices to be followed for this
Ring handles the operating pressure of data, and on this basis, each FPGA device can be after completing previous cycle and executing, can be with stream
The mode that waterline executes continues to and responds incoming new data content, therefore the opposite processing that ensure that mass data
Ability, and then FPGA device is improved under big data environment to the treatment effeciency of overall data.In addition, the present invention also provides one
The control stream executive device, equipment and medium, beneficial effect for planting FPGA are same as above.
Detailed description of the invention
In order to illustrate the embodiments of the present invention more clearly, attached drawing needed in the embodiment will be done simply below
It introduces, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ordinary skill people
For member, without creative efforts, it is also possible to obtain other drawings based on these drawings.
The flow chart for the control stream execution method that Fig. 1 is a kind of FPGA provided in an embodiment of the present invention；
Fig. 2 is the device that the control stream execution method of FPGA is realized in a kind of scene embodiment provided in an embodiment of the present invention
Topological diagram；
The flow chart for the control stream execution method that Fig. 3 is another kind FPGA provided in an embodiment of the present invention；
The structure chart for the control stream executive device that Fig. 4 is a kind of FPGA provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, rather than whole embodiments.Based on this
Embodiment in invention, those of ordinary skill in the art are without making creative work, obtained every other
Embodiment belongs to the scope of the present invention.
Core of the invention is to provide the control stream execution method of FPGA a kind of, with opposite raising FPGA device in big data
To the treatment effeciency of overall data under environment.Another core of the invention is to provide the control stream executive device of FPGA a kind of, sets
Standby and medium.
In order to enable those skilled in the art to better understand the solution of the present invention, with reference to the accompanying drawings and detailed description
The present invention is described in further detail.
Embodiment one
The flow chart for the control stream execution method that Fig. 1 is a kind of FPGA provided in an embodiment of the present invention.Referring to FIG. 1,
FPGA control stream execution method specific steps include:
Step S10: the cycle-index of incoming data content and routine call logic is received, and obtains routine call
Logic.
It should be noted that the executing subject of this step is FPGA device, current FPGA device is passed in reception
After the cycle-index of data content and routine call logic, routine call logic is obtained, routine call logic herein is
Data are carried out with a series of logical order of procedure operation.Such as need successively to call when handling data execute A program,
C program and B program, then routine call logic is then A-C-B, is executed repeatedly since routine call logic needs to recycle,
Routine call logic is equivalent to complete loop structure body.In this step, to the incoming data content of current FPGA device and
The equipment of cycle-index can be other FPGA devices with current FPGA device there are correspondence, be also possible to include user
Including terminal, for initiating the CPU device to data contents processing.When to the incoming data content of current FPGA device and
The equipment of cycle-index is with current FPGA device there are when other FPGA devices of correspondence, and the data content being passed to exists
It substantially should be process data obtained from the pre- circular treatment for first passing through other FPGA devices；To the incoming number of current FPGA device
When according to content and the equipment of cycle-index is CPU device, the data content transmitted should be original data content, and
The cycle-index transmitted is 0.
Step S11: the routine call logic of first circulation number is continuously performed to carry out calculation process, life to data content
At process data.
Wherein, the quantity summation of first circulation number and cycle-index is less than or equal to the specified of routine call logic and follows
Ring number.
This step is to execute the routine call logic of first circulation number to data content in FPGA device, and herein
First circulation number should be according to the nominal cycle number of the routine call logic and cycle-index is set, it is therefore an objective to
Ensure that first circulation number is less than or equal to the nominal cycle number of routine call logic with the quantity summation of cycle-index.It needs
It is noted that the nominal cycle number in this step refers to that routine call logic needs to recycle the total degree executed.
Step S12: when quantity summation is less than nominal cycle number, cycle-index is updated, and by process data and
Cycle-index is transmitted to next FPGA device, with secondary according to cycle-index and nominal cycle using next FPGA device
Number, the routine call logic of second circulation number is continuously performed to process data.
It is understood that quantity summation is less than nominal cycle number, illustrate to recycle execution in current FPGA device
The obtained process data of routine call logic, and non-final result data need to carry out subsequent circular treatment to it, because
This is transmitted to next FPGA device in this step, by obtained process data and cycle-index, and next
According to cycle-index and nominal cycle number in FPGA device, the program tune of second circulation number is continuously performed to process data
Use logic.It is emphasized that next FPGA device is receiving the incoming process data of current FPGA device and is recycling
The operation taken after number, the behaviour for receiving incoming data content with current FPGA device and being taken after cycle-index
Make, it is inherently identical, execute between the current FPGA device of this step and next FPGA device be in contrast,
Therefore for data content and cycle-index to be transmitted to other FPGA devices of current FPGA device, current FPGA phase
When in " the next FPGA device " of other FPGA devices.In addition, it is necessary to guarantee, the second circulation number of this step with
The quantity summation of cycle-index should be less than or equal to routine call logic nominal cycle number.
Step S13: incoming new data content is received and processed.
It is understood that this step is to pass through stream after the circular treatment of the complete paired data content of current FPGA device
The mode that waterline executes receives and processes incoming new data content again, to realize under big data environment to mass data
Processing.In addition, identical as step S10-S12 to the concrete operations content of new data content received and processed in this step.
The control stream execution method of FPGA provided by the present invention is received by current FPGA device in incoming data
The cycle-index of appearance and routine call logic, and then after obtaining the routine call logic, continuous logarithmic is executed according to content
The routine call logic of first circulation number, generating process data.First circulation number and the quantity summation of cycle-index are small
In or equal to nominal cycle number of routine call logic at the end of recycling execution.When the program tune for executing first circulation number
Nominal cycle number has not yet been reached with the cycle-index after logic, i.e., when the circulation of routine call logic executes not yet completion,
Process data and current cycle-index are transmitted to next FPGA device, and using next FPGA device according to working as
Preceding cycle-index and nominal cycle number continues the routine call logic that second circulation number is executed to process data.
And current FPGA device continues to after process data is transmitted to next FPGA device and handles incoming new data
Content.This method is that multiple FPGA devices progress, each FPGA device are distributed in the operation that circulation is executed routine call logic
After receiving data content, the calculation process of certain cycle-index is only carried out to data content by routine call logic, i.e., will
Result data is transferred to next FPGA device and carries out subsequent circular treatment, and continues to and respond new data content, because
For through single FPGA device cyclic program calling logic, this method has been shared by multiple FPGA devices to be followed for this
Ring handles the operating pressure of data, and on this basis, each FPGA device can be after completing previous cycle and executing, can be with stream
The mode that waterline executes continues to and responds incoming new data content, therefore the opposite processing that ensure that mass data
Ability, and then FPGA device is improved under big data environment to the treatment effeciency of overall data.
Embodiment two
A kind of scene embodiment is provided below, Fig. 2 is to realize in a kind of scene embodiment provided in an embodiment of the present invention
The device topological diagram of the control stream execution method of FPGA.As shown in Fig. 2, the quantity of FPGA is at least 2 (FPGA1 and FPGA2),
FPGA1 is received by the CPU data content being passed to and cycle-index, so FPGA1 according to the execution of cycle-index in data
Hold the routine call logic for executing first circulation number, generating process data, and process data is transmitted to FPGA2 and continues to locate
Reason, and proceed to respond to and handle new data content, FPGA2 obtain process data and continue after cycle-index as
FPGA1 receives operation when data content, executes the program tune of second circulation number to process data according to cycle-index
With logic, and data result data.After first circulation number and second circulation number, cycle-index is had reached
When nominal cycle number, the result data of FPGA2 output is final processing result；When by first circulation number and the
After two cycle-indexes, when cycle-index is also not up to nominal cycle number, then processing result is continued to be input to subsequent
Circulation is carried out in FPGA and executes processing, until cycle-index obtains final processing result when reaching nominal cycle number.
Embodiment three
On the basis of the above embodiments, the present invention also provides a series of preferred embodiments.
The flow chart for the control stream execution method that Fig. 3 is another kind FPGA provided in an embodiment of the present invention.Step in Fig. 3
S10-S13 is identical as Fig. 1, and details are not described herein.
As shown in figure 3, as a preferred embodiment, in the routine call logic for continuously performing first circulation number
To carry out calculation process to data content, after generating process data, this method further comprises:
Step S20: when quantity summation is equal to nominal cycle number, process data is set as result data.
It should be noted that first circulation number and the quantity summation of cycle-index are equal to nominal cycle number, then say
After the bright processing for carrying out first circulation number to data content according to routine call logic, global cycle number has reached specified follow
Ring number, the process data obtained from are final result data, therefore in this step, when quantity summation is equal to specified
When cycle-index, process data is set as result data.This step considers quantity summation equal to nominal cycle number
Situation, and the operation of corresponding contents is taken, it is opposite to improve the integrality of scheme and the reliability of execution.This step and step
Belong to operation content in varied situations between rapid S12, therefore in practical situations, after generating process data, can only execute
This step and step S12 a certain step therein.
In addition, as a preferred embodiment, having received incoming data content and routine call logic
Cycle-index, and before obtaining routine call logic, this method further comprises:
Judge whether current FPGA device meets preset condition；
If it is, executing the cycle-index for receiving incoming data content and routine call logic, and obtain journey
The step of sequence calling logic.
It should be noted that due to consideration that carrying out data processing there may be current FPGA device, or it is current
Not yet burning has situations such as routine call logic for carrying out circular treatment to data content in FPGA device, thus may lead
Current FPGA device is caused to can not be successfully the data content that reception or processing are passed to, therefore in order to ensure be passed to data content energy
Enough smoothly to be received and handled by current FPGA device, present embodiment is to incoming data content and routine call
Before cycle-index is received of logic, needs first to judge whether current FPGA device meets preset condition, when meeting,
The cycle-index for receiving incoming data content and routine call logic can be just executed, and obtains the step of routine call logic
Suddenly.In addition, the setting of preset condition can not be handled the data content of transmission with reference to current FPGA device
A series of states, the particular content of preset condition should be current FPGA device without above-mentioned state, for example, current FPGA is set
For when being in business occupied state, the data content of new incoming can not be handled, then preset condition should be current FPGA
Equipment is in idle condition.
In addition, on the basis of the above embodiment, as a preferred embodiment, preset condition is specially to be in
Idle state.
It is understood that in view of can not be in the data of new incoming when FPGA device is in business occupied state
Appearance is handled, and when carrying out between FPGA device data interaction, often will appear the first FPGA device to next
The case where FPGA device sends data, and the data processing task in next FPGA device not yet handles completion, so it is next
A FPGA device leads to not the data content for handling new incoming, the present embodiment loss of new data and then guarantee in order to prevent
The reliability of current FPGA device work, only received when current FPGA device is in idle condition incoming data content and
The cycle-index of routine call logic.
In addition, as a preferred embodiment, obtaining routine call logic specifically:
It obtains and first passes through the routine call logic that OpenCL SDK writes and is burned onto PROM in advance.
It should be noted that OpenCL is the frame for writing program for heterogeneous platform, OpenCL standard can be natural
The algorithm content realized in FPGA device of description.And the parallel function of FPGA is very powerful, compared with other devices, to the greatest extent
The consequence for occurring any failure when may extract parallel function is all very serious, and OpenCL standard is able to solve much this kind of ask
Topic, it supports programming personnel explicitly to set and control parallel processing operations, compared with the continuous program of pure C language description,
OpenCL standard can be more natural matching FPGA device highly-parallel characteristic.Present embodiment is write by OpenCL SDK
Routine call logic improves compatibility when FPGA device executes routine call logic, improves when FPGA device works
Reliability.In advance by routine call logic be burned onto FPGA device PROM (Programmable Read-Only Memory,
Programmable read only memory) after, FPGA device can be obtained quickly according to demand and run the routine call logic, it is ensured that
Whole execution efficiency.
In addition, as a preferred embodiment, this method is further after process data is set as result data
Include:
Result data is transmitted to user equipment, to record by user equipment and show result data.
It is understood that after process data is set as result data, in order to ensure user can view accordingly
Result data is transmitted to user equipment by result data, present embodiment, and then is recorded by user equipment and shown the result
Data, it is ensured that user, can efficiently in a user device after carrying out circular treatment to data by FPGA device
The result data for obtaining circular treatment, improves user experience.
Example IV
Hereinbefore the embodiment of the control stream execution method of FPGA is described in detail, the present invention also provides
A kind of control stream executive device of FPGA corresponding with this method, due to the embodiment of device part and the embodiment of method part
It corresponds to each other, therefore the embodiment of device part refers to the description of the embodiment of method part, wouldn't repeat here.
The structure chart for the control stream executive device that Fig. 4 is a kind of FPGA provided in an embodiment of the present invention.The embodiment of the present invention
The control stream executive device of the FPGA of offer, comprising:
Data reception module 10, for receiving the cycle-index of incoming data content and routine call logic, and
Obtain routine call logic.
Circular treatment module 11, for continuously performing the routine call logic of first circulation number to carry out to data content
Calculation process, generating process data；Wherein, first circulation number and the quantity summation of cycle-index are less than or equal to program tune
With the nominal cycle number of logic.
Data transmission module 12, for when quantity summation is less than nominal cycle number, updating cycle-index, and incited somebody to action
Number of passes according to and cycle-index is transmitted to next FPGA device, with using next FPGA device according to cycle-index and volume
Determine cycle-index, the routine call logic of second circulation number is continuously performed to process data.
New data respond module 13, for receiving and processing incoming new data content.
The control stream executive device of FPGA provided by the present invention is received by current FPGA device in incoming data
The cycle-index of appearance and routine call logic, and then after obtaining the routine call logic, continuous logarithmic is executed according to content
The routine call logic of first circulation number, generating process data.First circulation number and the quantity summation of cycle-index are small
In or equal to nominal cycle number of routine call logic at the end of recycling execution.When the program tune for executing first circulation number
Nominal cycle number has not yet been reached with the cycle-index after logic, i.e., when the circulation of routine call logic executes not yet completion,
Process data and current cycle-index are transmitted to next FPGA device, and using next FPGA device according to working as
Preceding cycle-index and nominal cycle number continues the routine call logic that second circulation number is executed to process data.
And current FPGA device continues to after process data is transmitted to next FPGA device and handles incoming new data
Content.The present apparatus is that multiple FPGA devices progress, each FPGA device are distributed in the operation that circulation is executed routine call logic
After receiving data content, the calculation process of certain cycle-index is only carried out to data content by routine call logic, i.e., will
Result data is transferred to next FPGA device and carries out subsequent circular treatment, and continues to and respond new data content, because
For through single FPGA device cyclic program calling logic, the present apparatus has been shared by multiple FPGA devices to be followed for this
Ring handles the operating pressure of data, and on this basis, each FPGA device can be after completing previous cycle and executing, can be with stream
The mode that waterline executes continues to and responds incoming new data content, therefore the opposite processing that ensure that mass data
Ability, and then FPGA device is improved under big data environment to the treatment effeciency of overall data.
On the basis of embodiment three, the device further include:
As a result setting module, for when quantity summation is equal to nominal cycle number, process data to be set as number of results
According to.
Embodiment five
The present invention also provides the control streams of FPGA a kind of to execute equipment, comprising:
Memory, for storing computer program；
Processor, when for executing computer program the step of the realization such as control stream execution method of above-mentioned FPGA.
The control stream of FPGA provided by the present invention executes equipment, is received in incoming data by current FPGA device
The cycle-index of appearance and routine call logic, and then after obtaining the routine call logic, continuous logarithmic is executed according to content
The routine call logic of first circulation number, generating process data.First circulation number and the quantity summation of cycle-index are small
In or equal to nominal cycle number of routine call logic at the end of recycling execution.When the program tune for executing first circulation number
Nominal cycle number has not yet been reached with the cycle-index after logic, i.e., when the circulation of routine call logic executes not yet completion,
Process data and current cycle-index are transmitted to next FPGA device, and using next FPGA device according to working as
Preceding cycle-index and nominal cycle number continues the routine call logic that second circulation number is executed to process data.
And current FPGA device continues to after process data is transmitted to next FPGA device and handles incoming new data
Content.This equipment is that multiple FPGA devices progress, each FPGA device are distributed in the operation that circulation is executed routine call logic
After receiving data content, the calculation process of certain cycle-index is only carried out to data content by routine call logic, i.e., will
Result data is transferred to next FPGA device and carries out subsequent circular treatment, and continues to and respond new data content, because
For through single FPGA device cyclic program calling logic, this equipment has been shared by multiple FPGA devices to be followed for this
Ring handles the operating pressure of data, and on this basis, each FPGA device can be after completing previous cycle and executing, can be with stream
The mode that waterline executes continues to and responds incoming new data content, therefore the opposite processing that ensure that mass data
Ability, and then FPGA device is improved under big data environment to the treatment effeciency of overall data.
In addition, being stored with meter on computer readable storage medium the present invention also provides a kind of computer readable storage medium
Calculation machine program, when computer program is executed by processor the step of the realization such as control stream execution method of above-mentioned FPGA.
The control stream of FPGA provided by the present invention executes computer readable storage medium, is connect by current FPGA device
The cycle-index of incoming data content and routine call logic is received, and then after obtaining the routine call logic, continuously
The routine call logic of first circulation number, generating process data are executed to data content.It first circulation number and has recycled time
Several quantity summations is less than or equal to nominal cycle number of routine call logic at the end of recycling execution.When execution first follows
Nominal cycle number has not yet been reached in cycle-index after the routine call logic of ring number, i.e. the circulation of routine call logic is held
When row is not yet completed, process data and current cycle-index are transmitted to next FPGA device, and utilize next
FPGA device continues to execute second circulation number to process data according to current cycle-index and nominal cycle number
Routine call logic.And current FPGA device continues to and locates after process data is transmitted to next FPGA device
The incoming new data content of reason.This computer readable storage medium be will circulation execute routine call logic operation distribute to it is more
A FPGA device carries out, and each FPGA device only carries out data content by routine call logic after receiving data content
Result data is transferred to next FPGA device and carries out subsequent circular treatment by the calculation process of certain cycle-index, and
New data content is continued to and responds, therefore for through single FPGA device cyclic program calling logic, this
Computer readable storage medium has shared the operating pressure of circular treatment data by multiple FPGA devices, on this basis, often
A FPGA device can be continued to and be responded incoming in such a way that assembly line executes after completing previous cycle and executing
New data content, therefore the opposite processing capacity that ensure that mass data, and then improve FPGA device in big data ring
To the treatment effeciency of overall data under border.
Method, apparatus, equipment and medium is executed to the control stream of FPGA provided by the present invention a kind of above to have carried out in detail
It is thin to introduce.Each embodiment is described in a progressive manner in specification, the highlights of each of the examples are with other realities
The difference of example is applied, the same or similar parts in each embodiment may refer to each other.For device disclosed in embodiment, set
For standby and medium, since it is corresponded to the methods disclosed in the examples, so being described relatively simple, related place is referring to side
Method part explanation.It should be pointed out that for those skilled in the art, not departing from the principle of the invention
Under the premise of, it can be with several improvements and modifications are made to the present invention, these improvement and modification also fall into the claims in the present invention
In protection scope.
It should also be noted that, in the present specification, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes that
A little elements, but also including other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in the process, method, article or apparatus that includes the element.
Claims (10)
1. the control stream execution method of FPGA a kind of characterized by comprising
The cycle-index of incoming data content and routine call logic is received, and obtains described program calling logic；
The described program calling logic of first circulation number is continuously performed to carry out calculation process to the data content, was generated
Number of passes evidence；Wherein, the quantity summation of the first circulation number and the cycle-index is called less than or equal to described program
The nominal cycle number of logic；
When the quantity summation is less than the nominal cycle number, the cycle-index is updated, and by the process data
And the cycle-index is transmitted to next FPGA device, it is secondary to have been recycled according to using next FPGA device
The several and described nominal cycle number continuously performs the described program calling logic of second circulation number to the process data；
Receive and process incoming new data content.
2. the method according to claim 1, wherein in the described program for continuously performing first circulation number
Calling logic is to carry out calculation process to the data content, and after generating process data, this method further comprises:
When the quantity summation is equal to the nominal cycle number, the process data is set as result data.
3. the method according to claim 1, wherein receiving incoming data content and routine call described
The cycle-index of logic, and before obtaining described program calling logic, this method further comprises:
Judge whether current FPGA device meets preset condition；
If it is, executing the cycle-index for receiving incoming data content and routine call logic, and obtain institute
The step of stating routine call logic.
4. according to the method described in claim 3, it is characterized in that, the preset condition is specially to be in idle condition.
5. the method according to claim 1, wherein the acquisition described program calling logic specifically:
It obtains and first passes through the described program calling logic that OpenCL SDK writes and is burned onto PROM in advance.
6. according to method described in claim 2 to 5 any one, which is characterized in that set the process data described
After result data, this method further comprises:
The result data is transmitted to the user equipment, to record by the user equipment and show the number of results
According to.
7. the control stream executive device of FPGA a kind of characterized by comprising
Data reception module for receiving the cycle-index of incoming data content and routine call logic, and obtains institute
State routine call logic；
Circular treatment module, for continuously perform the described program calling logic of first circulation number with to the data content into
Row calculation process, generating process data；Wherein, the quantity summation of the first circulation number and the cycle-index be less than or
Equal to the nominal cycle number of described program calling logic；
Data transmission module, for updating the cycle-index when the quantity summation is less than the nominal cycle number,
And the process data and the cycle-index are transmitted to next FPGA device, to utilize next FPGA device
According to the cycle-index and the nominal cycle number, the process data is continuously performed described in second circulation number
Routine call logic；
New data respond module, for receiving and processing incoming new data content.
8. device according to claim 7, which is characterized in that the device further comprises:
As a result setting module, for when the quantity summation is equal to the nominal cycle number, the process data to be set
For result data.
9. the control stream of FPGA a kind of executes equipment characterized by comprising
Memory, for storing computer program；
Processor realizes the control stream such as FPGA as claimed in any one of claims 1 to 6 when for executing the computer program
The step of execution method.
10. a kind of computer readable storage medium, which is characterized in that be stored with computer on the computer readable storage medium
Program realizes that the control stream such as FPGA as claimed in any one of claims 1 to 6 is held when the computer program is executed by processor
The step of row method.
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