CN109188376A - Digital TR component sends board synchronous test system - Google Patents
Digital TR component sends board synchronous test system Download PDFInfo
- Publication number
- CN109188376A CN109188376A CN201810967807.0A CN201810967807A CN109188376A CN 109188376 A CN109188376 A CN 109188376A CN 201810967807 A CN201810967807 A CN 201810967807A CN 109188376 A CN109188376 A CN 109188376A
- Authority
- CN
- China
- Prior art keywords
- board
- pinboard
- fpga development
- test system
- send
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/40—Means for monitoring or calibrating
- G01S7/4004—Means for monitoring or calibrating of parts of a radar system
Abstract
The invention discloses digital TR components to send board synchronous test system, including the end PC, FPGA development board, pinboard, send board, arrow net analyzer, frequency spectrograph and signal source, the transmission board is connect with frequency spectrograph, arrow net analyzer and pinboard respectively, pinboard is connect with FPGA development board, the signal converting of board will be sent to FPGA development board, FPGA development board is also connect with the end PC, and signal source is docked with transmission board and pinboard respectively.It to the transmission board card of digital TR component in application, can carry out automatically-synchronously testing, promotion testing efficiency and accuracy.
Description
Technical field
The present invention relates to TR module testing technical fields, and in particular to digital TR component sends board synchronous test system.
Background technique
In modern radar technology, phased-array radar occupies highly important status, and wherein TR component is that entire radar closes
One of key member.The formation of conventional phased array radar emission wave beam is realized by phase shift and amplitude weighting, and this work
Make often in radio frequency band, by TR component each on front phase shifter and attenuator complete.Due to radio-frequency phase shifter
Digit cannot be made very high, therefore wave beam more spends and just compares larger, to lower wave beam and more spend, must just improve phase shifter
Digit, this is with simulation system come highly difficult when realizing.With the rapid development of digital technology, the complexity of previous digital display circuit
It is greatly reduced with high cost, reliability is continuously improved, so that in the past must be with the system that analog device is realized by digital display circuit
It is substituted, in addition digital display circuit has many advantages, such as repeatability, controllability and also convenient for integrated, therefore digital display circuit is used for thunder
Up to middle ever more popular.Based on this, it is contemplated that realize, in addition the phase shift of radio frequency and amplitude weighting are changed to low-frequency range by digital circuit
Using DBF (Digital Beam Form) reception technique, it is digital digital TR component concept that this, which just introduces transmitting-receiving, i.e.,
It is controlled and the input and output of data are all ordered series of numbers formulas.Digital TR component, which is divided into, sends board (T plate) and reception board (R
Plate), typical case is respectively used to sending and receiving for data as shown in instruction sheet 2, at present for the survey of digital TR component
What examination was mostly also performed manually by, there is no the more perfect Auto-Test System of system is formed, need to occupy a large amount of manpowers,
And testing efficiency is lower, is easy to appear mistake.
Summary of the invention
The present invention sends board synchronous test system in view of the deficienciess of the prior art, providing number TR component, answers
Used time can carry out automatically-synchronously testing to the transmission board card of digital TR component, promote testing efficiency and accuracy.
The invention is realized by the following technical scheme:
Digital TR component sends board synchronous test system, including the end PC, FPGA development board, pinboard, transmission board, arrow
Net analyzer, frequency spectrograph and signal source, the transmission board connect with frequency spectrograph, arrow net analyzer and pinboard respectively, transfer
Plate is connect with FPGA development board, will send the signal converting of board to FPGA development board, and FPGA development board is also connect with the end PC, letter
Number source respectively with send board and pinboard docks, in which:
Signal source provides the sampling clock of 480MHz to send board, while when providing for pinboard the reference of 1.92GHz
Clock, sampling clock and reference clock are homologous；
On the one hand pinboard is used to send the signal converting of board Yu FPGA development board, on the other hand mention for FPGA development board
For the reference clock of 120MHz；
Frequency spectrograph is another on the one hand to the center frequency point and range parameter for sending board output 645HMz ± 15MHz signal
Aspect is used to send the frequency-domain analysis of board；
Arrow net analyzer is used to measure the phase equalization for sending board；
FPGA development board realizes that the high-speed data based on 204B agreement exchanges with board is sent；
The end PC is used to carry out chip configuration to FPGA development board, realizes data interaction.
Preferably, the FPGA development board uses VC707 type development board.
Preferably, the pinboard is FMC-DBF pinboard.
Preferably, the transmission board is arranged with KJ30J interface, and FPGA development board is equipped with FMC interface, pinboard respectively with
The FMC interface of FPGA development board and the KJ30J interface docking for sending board.
Preferably, digital analog converter is equipped in the transmission board.
The present invention has the advantage that and the utility model has the advantages that
1, number TR component of the invention sends board synchronous test system, can carry out certainly to digital TR component transmission board card
Dynamic synchronization parameter measurement；
2, number TR component of the invention sends board synchronous test system, can effectively improve digital TR component and sends board
Testing efficiency and accuracy.
3, number TR component of the invention sends board synchronous test system, easy to use, can save manual testing's link.
Detailed description of the invention
Attached drawing described herein is used to provide to further understand the embodiment of the present invention, constitutes one of the application
Point, do not constitute the restriction to the embodiment of the present invention.In the accompanying drawings:
Fig. 1 is the structural diagram of the present invention；
Fig. 2 is the typical case schematic diagram for sending board and receiving board of existing number TR component；
Fig. 3 is the data flowchart that board is sent in embodiment；
Fig. 4 is the internal functional block diagram that board is sent in embodiment.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below with reference to embodiment and attached drawing, to this
Invention is described in further detail, and exemplary embodiment of the invention and its explanation for explaining only the invention, are not made
For limitation of the invention.
Embodiment
As shown in Figure 1, number TR component send board synchronous test system, including the end PC, FPGA development board, pinboard,
Send board, arrow net analyzer, frequency spectrograph and signal source, the transmissions board respectively with frequency spectrograph, swear net analyzer and switching
Plate connection, pinboard connect with FPGA development board, will send the signal converting of board to FPGA development board, FPGA development board also with
The connection of the end PC, signal source are docked with transmission board and pinboard respectively, in which:
Signal source provides the sampling clock of 480MHz to send board, while when providing for pinboard the reference of 1.92GHz
Clock, sampling clock and reference clock are homologous；
On the one hand pinboard is used to send the signal converting of board Yu FPGA development board, on the other hand mention for FPGA development board
For the reference clock of 120MHz；
Frequency spectrograph is another on the one hand to the center frequency point and range parameter for sending board output 645HMz ± 15MHz signal
Aspect is used to send the frequency-domain analysis of board；
Arrow net analyzer is used to measure the phase equalization for sending board；
FPGA development board realizes that the high-speed data based on 204B agreement exchanges with board is sent；
The end PC is used to carry out chip configuration to FPGA development board, realizes data interaction.
It is handed over when it is implemented, carrying out chip configuration to FPGA development board by the end PC and it being made to stick into row data with transmission board
Mutually, and to transmission board card synchronize drive control, send signal that board test generates by output port by frequency spectrograph and
Arrow net analyzer receives, and frequency spectrograph carries out frequency-domain analysis to the output signal for sending board, and arrow net analyzer is to transmission board
Output signal carries out phase equalization measurement, thus can carry out synchronised automatic measurement to transmission board card.
As shown in figure 3, the data for sending board mainly pass through following four step:
One, 0MHz ± 15MHz (sample rate 240MHz) baseband I Q data is transmitted to by GM4840 by JESD204B interface
Data path.JESD204B interface uses 4 lane, rate 4.8Gbps；
Two, 0MHz ± 15MHz baseband I Q data passes through 2 times of interpolations and passes through low-pass filtering, and data sampling rate is by 240MHz
It is promoted to 480MHz；
Three, GM4840 sample rate is 480MHz, and NCO is set as 165MHz.0MHz ± 15MHz baseband I Q data passes through NCO
Mixing, obtains 165MHz ± 15MHz real data；
Four, it opens DAC mixing function and improves second and third Nyquist signal energy, it is final to choose the exported by DAC
Three band 645MHz ± 15MHz signals.
Wherein, the I/Q data of Serdes0 ± and Serdes1 ± transmission channel A, Serdes2 ± logical with Serdes3 ± transmission
The I/Q data of road B.
It sends board built-in function and is received as shown in figure 4, sending board from high-speed interface (JESD204B-01 interface standard)
To 4 circuit-switched datas, carry out generating 2 tunnel intermediate-freuqncy signals after framing next stage system is sent to by DA handles.The board uses
GM4840 is as DA chip, sampling clock 480MHz, data transfer rate 240MSPS.
Send board main feature include:
(1) input characteristics:
A, input signal: 14BitIQ sampling serial data flow；
B, input signal uses rate: 240MSPS；
C, input signal centre frequency: zero intermediate frequency；
D, IQ orthogonality: gain error≤0.2%, phase error≤0.2 °.
(2) output characteristics:
A, D/A converts output services frequency 645MHz ± 15MHz；
B, output power: -7 ± 1dBm；
C, width phase change :≤1 °/dB；
D, spurious reduction: >=60dBc (in bandwidth 645MHz ± 15MHz)；
E, power stability :≤± 0.2dB/24h；
F, phase stability :≤± 1 °/for 24 hours；
G, each plate same channels phase equalization :≤± 5 °；
H, third order intermodulation: input frequency interval 5MHz, when general power is lower than two carrier wave of frequency power 7dB, third order intermodulation
≤-29dBc；
I, integrated temperature detection, voltage detecting and failure report an error function.
Above-described specific embodiment has carried out further the purpose of the present invention, technical scheme and beneficial effects
It is described in detail, it should be understood that being not intended to limit the present invention the foregoing is merely a specific embodiment of the invention
Protection scope, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (5)
1. number TR component sends board synchronous test system, which is characterized in that including the end PC, FPGA development board, pinboard, hair
Send board, arrow net analyzer, frequency spectrograph and signal source, the transmissions board respectively with frequency spectrograph, swear net analyzer and pinboard
Connection, pinboard connect with FPGA development board, will send the signal converting of board to FPGA development board, FPGA development board also with PC
End connection, signal source are docked with transmission board and pinboard respectively, in which:
Signal source provides the sampling clock of 480MHz to send board, while providing the reference clock of 1.92GHz for pinboard, adopts
Sample clock and reference clock are homologous；
On the one hand pinboard is used to send the signal converting of board Yu FPGA development board, on the other hand provide for FPGA development board
The reference clock of 120MHz；
Frequency spectrograph is on the one hand to the center frequency point and range parameter for sending board output 645HMz ± 15MHz signal, on the other hand
For sending the frequency-domain analysis of board；
Arrow net analyzer is used to measure the phase equalization for sending board；
FPGA development board realizes that the high-speed data based on 204B agreement exchanges with board is sent；
The end PC is used to carry out chip configuration to FPGA development board, realizes data interaction.
2. number TR component according to claim 1 sends board synchronous test system, which is characterized in that the FPGA is opened
It sends out plate and uses VC707 type development board.
3. number TR component according to claim 1 sends board synchronous test system, which is characterized in that the pinboard
For FMC-DBF pinboard.
4. number TR component according to claim 1 or 2 or 3 sends board synchronous test system, which is characterized in that described
Transmission board is arranged with KJ30J interface, and FPGA development board is equipped with FMC interface, pinboard respectively with the FMC interface of FPGA development board and
Send the KJ30J interface docking of board.
5. number TR component according to claim 1 sends board synchronous test system, which is characterized in that the transmission board
Digital analog converter is equipped in card.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810967807.0A CN109188376A (en) | 2018-08-23 | 2018-08-23 | Digital TR component sends board synchronous test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810967807.0A CN109188376A (en) | 2018-08-23 | 2018-08-23 | Digital TR component sends board synchronous test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109188376A true CN109188376A (en) | 2019-01-11 |
Family
ID=64919233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810967807.0A Withdrawn CN109188376A (en) | 2018-08-23 | 2018-08-23 | Digital TR component sends board synchronous test system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109188376A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111505593A (en) * | 2020-04-30 | 2020-08-07 | 北京无线电测量研究所 | Frequency synthesis comprehensive test system and test method |
-
2018
- 2018-08-23 CN CN201810967807.0A patent/CN109188376A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111505593A (en) * | 2020-04-30 | 2020-08-07 | 北京无线电测量研究所 | Frequency synthesis comprehensive test system and test method |
| CN111505593B (en) * | 2020-04-30 | 2022-03-29 | 北京无线电测量研究所 | Frequency synthesis comprehensive test system and test method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20190111 |
|
| WW01 | Invention patent application withdrawn after publication |