CN109168191B - Terminal processor adjusting method and terminal processor adjusting device - Google Patents

Terminal processor adjusting method and terminal processor adjusting device Download PDF

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CN109168191B
CN109168191B CN201811055792.7A CN201811055792A CN109168191B CN 109168191 B CN109168191 B CN 109168191B CN 201811055792 A CN201811055792 A CN 201811055792A CN 109168191 B CN109168191 B CN 109168191B
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CN109168191A (en
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陈晓青
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Xiamen Meitu Mobile Technology Co Ltd
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W52/00Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02Power saving arrangements
    • H04W52/0209Power saving arrangements in terminal devices
    • H04W52/0261Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M1/00Substation equipment, e.g. for use by subscribers
    • H04M1/72Mobile telephones; Cordless telephones, i.e. devices for establishing wireless links to base stations without route selection
    • H04M1/724User interfaces specially adapted for cordless or mobile telephones
    • H04M1/72448User interfaces specially adapted for cordless or mobile telephones with means for adapting the functionality of the device according to specific conditions
    • H04M1/72454User interfaces specially adapted for cordless or mobile telephones with means for adapting the functionality of the device according to specific conditions according to context-related or environment-related conditions
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00Reducing energy consumption in communication networks
    • Y02D30/70Reducing energy consumption in communication networks in wireless communication networks

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Abstract

The application provides a terminal processor adjusting method and a terminal processor adjusting device, and relates to the technical field of processor adjustment. The method comprises the following steps: acquiring a processor parameter u (k-1) at the k-1 time, a processor parameter u (k-2) at the k-2 time, a katon parameter y (k) at the k time, and a pseudo partial derivative estimator at the k-1 time
Figure DDA0001795615310000011
According to the processor parameter u (k-1) at the k-1 moment, the processor parameter u (k-2) at the k-2 moment, the katon parameter y (k), and the pseudo-partial derivative estimation number
Figure DDA0001795615310000012
And a preset katton parameter y (k +1) at the k +1 th moment*Calculating the pseudo-partial derivative estimation number at the kth time by adopting a model-free self-adaptive control MFAC algorithm
Figure DDA0001795615310000013
Estimating the number according to the pseudo partial derivative at the k-th time
Figure DDA0001795615310000014
Calculating a processor parameter u (k) at the k-th moment; and adjusting the actual processor parameter u (k) at the k time according to the processor parameter u (k) at the k time. The optimal processor parameter at the balance moment is obtained through the pause parameter at the current moment, and the optimal processor parameter is utilized to adjust the actual processor parameter of the terminal, so that the pause problem is solved, the power is saved, and the use effect of the terminal is optimized.

Description

Terminal processor adjusting method and terminal processor adjusting device
Technical Field
The invention relates to the technical field of processor adjustment, in particular to a terminal processor adjusting method and a terminal processor adjusting device.
Background
With the popularization of smart phones, people have higher and higher performance requirements on the smart phones, wherein the problems of jamming and power consumption are particularly prominent, but the two factors are mutually exclusive in most cases.
In the prior art, the problem of jamming is usually solved by increasing the running memory of the mobile phone or the consumption of a Central Processing Unit (CPU) and the like.
But the increase of the running memory of the mobile phone and the increase of the CPU consumption can lead to the acceleration of the power consumption of the mobile phone, thereby greatly reducing the cruising ability of the mobile phone.
Disclosure of Invention
The present invention provides a method and a device for adjusting a terminal processor to solve the problem of conflict between the mobile phone stuck and the mobile phone standby power.
In order to achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:
in a first aspect, an embodiment of the present application provides a method for adjusting a terminal processor, including: acquiring a processor parameter u (k-1) at the k-1 time, a processor parameter u (k-2) at the k-2 time, a katon parameter y (k) at the k time, and a pseudo partial derivative estimator at the k-1 time
Figure BDA0001795615290000021
Wherein k is an integer greater than or equal to 3.
Based on the processor parameter u (k-1) at the time point k-1, the processor parameter u (k-2) at the time point k-2, the katon parameter y (k) at the time point k, and the estimated pseudo-partial derivative number at the time point k-1
Figure BDA0001795615290000022
And a preset katton parameter y (k +1) at the k +1 th moment*Calculating the pseudo-partial derivative estimation number at the kth time by adopting a model-free self-adaptive control MFAC algorithm
Figure BDA0001795615290000023
Based on the processor parameter u (k-1) at the k-1 th time, the pause parameter y (k) at the k-1 th time, and the preset pause parameter y (k +1) at the k +1 th time*And the estimated number of pseudo partial derivatives at the k-th time
Figure BDA0001795615290000024
And calculating a processor parameter u (k) at the k-th time by adopting an MFAC algorithm, wherein the katon parameter y (k) at the k-th time is data acquired at the k-th time in real time.
And adjusting the actual processor parameter u (k) at the k time according to the processor parameter u (k) at the k time.
Further, the pseudo-partial derivative estimator at the k-th time is calculated by adopting a model-free adaptive control MFAC algorithm
Figure BDA0001795615290000025
The method comprises the following steps:
using a formula
Figure BDA0001795615290000031
Calculating the pseudo partial derivative estimator at the kth moment
Figure BDA0001795615290000032
Where η is the step sequence and Δ u (k-1) is the difference between the processor parameters u (k-1) and u (k-2) at time k-1 and k-2.
Further, the calculating the processor parameter u (k) at the k-th time by using the MFAC algorithm includes:
using a formula
Figure BDA0001795615290000033
And calculating the processor parameter u (k) at the k-th time, wherein rho is the step length sequence and lambda is the weighting factor.
Further, the processor parameters u (k) include: the number distribution of different types of cores in the processor and the core frequency of each type of core; the above-mentioned katon parameter y (k) includes a frame rate and a dropped frame number.
Further, the predetermined katton parameter y (k +1) at the k +1 th time*Constant is [60, 0 ]]。
In a second aspect, an embodiment of the present application provides a terminal processor adjusting apparatus, including: the device comprises an acquisition module, a calculation module and a determination module.
An acquisition module for acquiring the processor parameter u (k-1) at the k-1 time, the processor parameter u (k-2) at the k-2 time, the katon parameter y (k) at the k time, and the pseudo-partial derivative estimation number at the k-1 time
Figure BDA0001795615290000034
Wherein k is an integer greater than or equal to 3.
A calculation module for calculating the estimated number of pseudo-partial derivatives according to the processor parameter u (k-1) at the k-1 time, the processor parameter u (k-2) at the k-2 time, the katon parameter y (k) at the k time, and the estimated number of pseudo-partial derivatives at the k-1 time
Figure BDA0001795615290000041
And a preset katton parameter y (k +1) at the k +1 th moment*Calculating the pseudo-partial derivative estimation number at the kth time by adopting a model-free self-adaptive control MFAC algorithm
Figure BDA0001795615290000042
Based on the processor parameter u (k-1) at the k-1 th time, the katon parameter y (k) at the k-1 th time, and the katon parameter y (k +1) at the preset k +1 th time*And the estimated number of pseudo partial derivatives at the k-th time
Figure BDA0001795615290000045
And calculating a processor parameter u (k) at the k time by adopting an MFAC algorithm, wherein the katon parameter y (k) at the k time is data acquired at the k time in real time.
And the determining module is used for adjusting the actual processor parameter u (k) at the k time according to the processor parameter u (k) at the k time.
Further, the calculation module is specifically configured to:
using a formula
Figure BDA0001795615290000043
Calculating the pseudo partial derivative estimator at the kth moment
Figure BDA0001795615290000046
Where η is the step sequence and Δ u (k-1) is the difference between the processor parameters u (k-1) and u (k-2) at time k-1 and k-2.
Further, the calculation module is specifically further configured to:
using a formula
Figure BDA0001795615290000044
And calculating the processor parameter u (k) at the k-th time, wherein rho is the step length sequence and lambda is the weighting factor.
Further, the processor parameters u (k) include: the number distribution of different types of cores in the processor and the core frequency of each type of core; the katon parameter y (k) includes a frame rate and a dropped frame number.
Further, the predetermined katton parameter y (k +1) at the k +1 th time*Constant is [60, 0 ]]。
The beneficial effect of this application is: the method comprises the steps of establishing a balance relation between processor parameters and stuck parameters by adopting a model-free adaptive control MFAC algorithm according to preset constant stuck parameter values, obtaining the processor parameters at the current time by utilizing the stuck parameters acquired at the current time in real time, and adjusting the actual processor parameters of the mobile phone terminal through the processor parameters so that the mobile phone can not be stuck and relatively save electricity.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic flowchart of a terminal processor adjustment method according to an embodiment of the present application;
fig. 2 is a timing diagram of a terminal processor adjustment method according to an embodiment of the present application;
fig. 3 is a first schematic structural diagram of a terminal processor adjustment apparatus according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a terminal processor adjustment apparatus according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
First embodiment
Fig. 1 is a schematic flow chart of a terminal processor adjustment method provided in an embodiment of the present application, and fig. 2 is a timing relationship diagram of the terminal processor adjustment method provided in the embodiment of the present application.
The method can be executed by a mobile phone, a tablet computer, a server, an intelligent television and other terminal devices, but is not particularly limited. As shown in fig. 1, the terminal processor adjusting method includes:
s101, obtaining a processor parameter u (k-1) at the k-1 moment, a processor parameter u (k-2) at the k-2 moment, a stuck parameter y (k) at the k moment and a pseudo-partial derivative estimation number at the k-1 moment
Figure BDA0001795615290000071
Wherein k is an integer greater than or equal to 3.
Specifically, referring to fig. 2, the cycle may be divided according to a preset time period, that is, a period of time is intercepted, and data is collected from the 0 th time, where the kth time is the kth time period.
The kth time may represent a time period of the current time.
S102, based on the processor parameter u (k-1) at the k-1 time, the processor parameter u (k-2) at the k-2 time, the stuck parameter y (k) at the k time, and the estimated number of pseudo-partial derivatives at the k-1 time
Figure BDA0001795615290000072
And a preset katton parameter y (k +1) at the k +1 th moment*Calculating the pseudo-partial derivative estimation number at the kth time by adopting a model-free self-adaptive control MFAC algorithm
Figure BDA0001795615290000073
Specifically, the preset katton parameter at the k +1 th time
Figure BDA0001795615290000074
To ensure the terminal does not have the better stuck parameter, when the current stuck parameter y (k) is equal to or close to y (k +1)*And meanwhile, the terminal is smoother in use.
It should be noted that, the MFAC (Model Free Adaptive control) algorithm has a relatively complex scale and structure of a network control system, and a network environment changes at any time, and the MFAC algorithm can control the system only by using current online data, and can be well adapted to the change of the system. In addition, the MFAC algorithm is adopted for calculation, the control principle is simple and easy to use, the calculated amount is small, the robustness is strong, the calculation is carried out only by using input and output data, and a controlled system model does not need to be established.
S103, according to the processor parameter u (k-1) at the k-1 time, the pause parameter y (k) at the k time, and the pause parameter y (k +1) at the preset k +1 time*And the estimated number of pseudo partial derivatives at the k-th time
Figure BDA0001795615290000081
And calculating a processor parameter u (k) at the k time by adopting an MFAC algorithm, wherein the katon parameter y (k) at the k time is data acquired at the k time in real time.
It should be noted that, in the terminal system, the processor parameter u (0) at the 0 th time and the processor parameter u (1) at the 1 st time are given values, or may also be values obtained by real-time acquisition. In addition, the initial value of the pseudo-partial derivative estimation number
Figure BDA0001795615290000082
Also given as numerical values.
Specifically, the stuck parameter y (k) represents the stuck condition of the terminal, the processor parameter u (k) represents the operating load of the processor, and the stuck parameter y (k) and the processor parameter u (k) can be balanced by adjusting the processor parameter u (k) in real time, so that the stuck condition can be reduced, the operating consumption of the processor can be better, overload operation cannot occur as much as possible, and the cruising ability of the terminal is ensured as much as possible.
S104, according to the processor parameter u (k) at the k-th time, adjusting the actual processor parameter u (k) at the k-th time.
It should be noted that, the calculated processor parameter u (k) and the stuck parameter y (k) acquired in real time at the current time satisfy a balance relationship, that is, if the currently acquired stuck parameter y (k) does not satisfy the condition of the more optimal stuck parameter, at this time, the load of the processor is increased by increasing the terminal processor parameter u (k), so as to optimize the system, solve the stuck phenomenon, and at the same time, the load of the processor is not too high, so that the endurance of the terminal is not greatly affected. If the stuck parameter y (k) of the current set meets the condition of the better stuck parameter, at this time, the load of the processor can be reduced by reducing the parameter u (k) of the terminal processor, so that the effect of continuation of the journey can be achieved under the condition of no sticking.
In this embodiment, a balance relation between a morton parameter y (k) and a processor parameter u (k) is constructed in real time by acquiring historical data of the processor parameter u (k) and the morton parameter y (k) in the terminal and using a model-free adaptive control MFAC algorithm, and a better processor parameter u (k) at the current time is obtained by calculating through the balance relation and the morton parameter y (k) acquired at the current time k.
Further, the pseudo-partial derivative estimator at the k-th time is calculated by adopting a model-free adaptive control MFAC algorithm
Figure BDA0001795615290000091
The method comprises the following steps:
using a formula
Figure BDA0001795615290000092
Calculating the pseudo partial derivative estimator at the kth moment
Figure BDA0001795615290000093
Where η is the step sequence and Δ u (k-1) is the difference between the processor parameters u (k-1) and u (k-2) at time k-1 and k-2.
Specifically, in the formula, Δ u (k-1) represents a processor parameter difference, i.e., a difference between a current time and a previous time of the processor parameter, where Δ u (k-1) is u (k-1) -u (k-2).
Further, the calculating the processor parameter u (k) at the k-th time by using the MFAC algorithm includes:
using a formula
Figure BDA0001795615290000101
And calculating the processor parameter u (k) at the k-th time, wherein rho is the step length sequence and lambda is the weighting factor.
Specifically, in this embodiment, the processor parameter u (k) and the katon parameter y (k) of the terminal system satisfy the non-linear system expression: y (k +1) ═ f [ y (k), u (k), k]Where u (k) represents the input to the system and y (k) represents the output of the system. The input and output of the device can be controlled and measured, namely, the preset stuck parameter y (k +1)*There is a bounded feasible control input signal u (k) such that the system output at this input y (k) equals the desired output of the system, i.e. the predetermined stuck parameter y (k +1)*. In addition, for the current control input signal u (k), it is satisfied that its partial derivatives are continuous, and there are arbitrary k and Δ u (k) ≠ 0, with Δ y (k +1) | ≦ b | Δ u (k), |, where | Δ y (k +1) | y (k +1) | - | y (k) |, Δ u (k) | u (k) — u (k-1); b is a constant.
Thus, when Δ u (k) ≠ 0, there must be a quantity called the pseudo-partial derivative, such that y (k +1) -y (k) ≠ φT(k) Delta u (k), wherein | phi (k) | is less than or equal to b, and b is a constant.
The above formula y (k +1) -y (k) ═ phiT(k) Δ u (k) is called a system-wide model, which is actually a way to linearize the dynamics of a nonlinear system by introducing pseudo-gradient vectors, so that the original discrete-time nonlinear system can be replaced by a series of dynamic linear time-varying models, but to make this replacement reasonable, there is a large relation with the input control signal, because Δ u (k) is guaranteed to be equal to 0 in dynamic closed-loop operation, and it is also needed to guarantee that u (k) cannot be changed too much, otherwise, it is unreasonable to adopt this replacement method.
The above formula is expressed by substitution as: Δ y (k) ═ Φ (k-1) Δ u (k-1), so that,the next moment prediction for the current moment is expressed as: Δ y (k +1) ═ Φ (k) Δ u (k). Wherein Δ y (k +1) ═ y*(k +1) -y (k), Δ u (k) -u (k-1). Using a system design criterion function J (u (k)) ═ y*(k+1)-y(k+1)|2+λ|u(k)-u(k-1)|2The term λ | u (k) -u (k-1) & gtdoes not count2The addition of the control valve plays a role in limiting the change of the control quantity, thereby achieving the purpose of overcoming the steady-state error of the system. After deriving u (k) using a criterion function and making it equal to zero, the computational expression for the processor parameters u (k) can be obtained as:
Figure BDA0001795615290000111
wherein ρ is a step sequence, which can be adjusted according to the requirement. The introduction of the weight coefficient lambda mainly has the following two functions, namely, the condition that the denominator is zero is avoided, and the limitation effect on the processor parameter u (k) is achieved, so that the delta u (k) is limited in a limited range, the rationalization of the generic model is ensured, and the pseudo-gradient limiting effect is achieved.
In addition, for the estimation of the pseudo gradient φ (k) in the generic model, the following estimation criterion function is used:
Figure BDA0001795615290000112
by deriving this function and making it zero, the estimation algorithm that yields the pseudo-gradient is:
Figure BDA0001795615290000113
wherein the content of the first and second substances,
Figure BDA0001795615290000114
the introduction of (b) plays a role in limiting the pseudo action gradient phi (k), eta is a step length sequence, mu is a weight factor, and the parameters are all adjustable parameters and can be properly adjusted according to actual conditions.
It should be noted that, in the MFAC algorithm, each iteration of calculation is performed, a minimum value is obtained, and in the MFAC algorithm, when a minimum criterion function is used for derivation, a step length of each derivation span is a step length sequence.
According to the above-mentioned calculation process, finally respectively calculating to obtain calculation formula of pseudo partial derivative estimated value phi (k),
Figure BDA0001795615290000121
and the calculation formula of the processor parameter u (k)
Figure BDA0001795615290000122
Two calculation formulas are regarded as an equation set and are matched with each other to carry out calculation, and the formulas
Figure BDA0001795615290000123
Substituting calculated phi (k) into formula
Figure BDA0001795615290000124
Calculating u (k), wherein k is an integer greater than or equal to 3, and performing multiple iterations in this way to finally obtain a balance relation between the processor parameter u (k) and the currently acquired katton parameter y (k).
For example: firstly, according to the initial values u (0) and u (1) of the processor parameters given by the system and the initial value of the pseudo partial derivative estimated value
Figure BDA0001795615290000125
The current real-time collected stuck parameter y (2) and the preset stuck parameter y (3)*Calculating the estimated value of the pseudo partial derivative of the current time of the system
Figure BDA0001795615290000126
In addition, the estimated value is based on the pseudo partial derivative
Figure BDA0001795615290000127
The current real-time collected stuck parameter y (2) and the preset stuck parameter y (3)*And calculating a processor parameter u (2) when the stuck condition and the endurance condition of the terminal in the current terminal system are better, and performing iterative calculation for multiple times to obtain a balance relation formula of the stuck parameter y (k) acquired at the kth moment and the calculated processor parameter u (k).
Further, the processor parameters u (k) include: the number distribution of different types of cores in the processor and the core frequency of each type of core; the above-mentioned katon parameter y (k) includes a frame rate and a dropped frame number.
Further, the predetermined katton parameter y (k +1) at the k +1 th time*Constant is [60, 0 ]]。
Specifically, the core types in the processor include: the number of each type of core and the corresponding core frequency determine the operation load of the processor. In the katon parameter, fps (frame rate) per second represents the number of times that the graphics processor can update per second when processing fields, and a high frame rate can obtain smoother and more vivid animation. Generally, 30fps is acceptable, but increasing performance to 60fps can significantly improve cross-talk and fidelity. In addition, when the sf drop frame number is zero, the user does not feel that the karton phenomenon exists.
It should be noted that, to prevent the terminal from being stuck, fps may be abstracted to 60, sf may be abstracted to 0, that is, the number of frames per second needs to reach 60, and no frame drop occurs, so that the card is not perceived by human eyes. The preset katton parameter y (k +1) at the k +1 th time*I.e. the expected stuck parameter in the system.
Specifically, in the present embodiment, in the first aspect, when the terminal has a stuck phenomenon, it is assumed that fps and sf of the current acquisition are 50 and 2 in the terminal system, that is, the stuck parameter y (k) is [50,2 ═ 2]And at this point, the core distribution in the processor parameters of the system is: if the large core is 1, the medium core is 4, the small core is 3, the large core frequency is 1092000, the medium core frequency is 184600, and the small core frequency is-1, then at the current moment, the processor parameter u (k) in the terminal system is 1,4,3,1092000,184600, -1]. Because the currently acquired stuck parameter y (k) ═ 50,2]The expected better Kadun parameter y (k +1) is not achieved*=[60,0]If the operation load of the processor is not increased, the terminal will have a pause phenomenon, but if the operation load of the processor is increased blindly, the power consumption of the terminal will be increased. Therefore, by using the balance relation between the processor parameter u (k) and the stuck parameter y (k) obtained by the above calculation, the terminal can be calculated not to be stuck, and the processor operation load is not too high at this timeLet u (k) be calculated as u (k) ═ 4,3,1,1092000, -1]The actual processor parameter u (k) of the system may then be set to [1,4,3,1092000,184600, -1]And adjusting the processor parameters according to the calculated processor parameters, namely, adjusting the processor parameters to u (k) ═ 4,3,1,1092000 and 1]In this case, the purpose of optimizing the system can be achieved.
In the second aspect, when the terminal does not have a stuck phenomenon, it is assumed that the currently acquired stuck parameters fps and sf are both normal values, and at this time, the operating load of the processor may exceed a normal level, i.e., overload operation, so that a large part of operation consumption is unnecessary, and if the terminal is always in an overload operating state, the power waiting time of the terminal will be seriously affected, i.e., the terminal has better cruising ability, at this time, the operating load of the current processor needs to be properly reduced, according to the balance relation formula of the processor parameter u (k) and the stuck parameter y (k) obtained by the above calculation, a better value of the processor parameter under the better value can be calculated, under the condition of the current normal stuck parameter, the processor load under the better value can be ensured that the terminal is not stuck continuously, and at the same time, the operating load of the processor is relatively reduced, assuming that the processor parameter u (k) ([ 0,4, -1,0,184600, -1] obtained by calculation at this time, the actual processor parameter u (k) ([ 1,4,3,1092000,184600, -1] of the system can be adjusted to u (k) ([ 0,4, -1,0,184600, -1], that is, the load of the processor is reduced, thereby achieving the purpose of saving power.
Second embodiment
Fig. 3 is a schematic structural diagram of a terminal processor adjustment apparatus according to an embodiment of the present application, and as shown in fig. 3, the terminal processor adjustment apparatus includes: an obtaining module 301, a calculating module 302, and a determining module 303, wherein:
an obtaining module 301, configured to obtain a processor parameter u (k-1) at a time k-1, a processor parameter u (k-2) at a time k-2, a stuck parameter y (k) at a time k, and a pseudo-partial derivative estimate number at a time k-1
Figure BDA0001795615290000151
Wherein k is greater than or equal to3, or an integer of 3.
A calculating module 302, configured to estimate the number of pseudo-partial derivatives according to the processor parameter u (k-1) at the time k-1, the processor parameter u (k-2) at the time k-2, the katton parameter y (k) at the time k, and the pseudo-partial derivatives at the time k-1
Figure BDA0001795615290000152
And a preset katton parameter y (k +1) at the k +1 th moment*Calculating the pseudo-partial derivative estimation number at the kth time by adopting a model-free self-adaptive control MFAC algorithm
Figure BDA0001795615290000153
Based on the processor parameter u (k-1) at the k-1 th time, the katon parameter y (k) at the k-1 th time, and the katon parameter y (k +1) at the preset k +1 th time*And the estimated number of pseudo partial derivatives at the k-th time
Figure BDA0001795615290000154
And calculating a processor parameter u (k) at the k time by adopting an MFAC algorithm, wherein the katon parameter y (k) at the k time is data acquired at the k time in real time.
The determining module 303 is configured to adjust the actual processor parameter u (k) at the kth time according to the processor parameter u (k) at the kth time.
Further, the calculation module 302 is specifically configured to:
using a formula
Figure BDA0001795615290000161
Calculating the pseudo partial derivative estimator at the kth moment
Figure BDA0001795615290000163
Where η is the step sequence and Δ u (k-1) is the difference between the processor parameters u (k-1) and u (k-2) at time k-1 and k-2.
Further, the calculating module 302 is specifically further configured to:
using a formula
Figure BDA0001795615290000162
Computing processor parameters at time kAnd u (k), wherein rho is the step length sequence and lambda is the weighting factor.
Further, the processor parameters u (k) include: the number distribution of different types of cores in the processor and the core frequency of each type of core; the katon parameter y (k) includes a frame rate and a dropped frame number.
Further, the predetermined katton parameter y (k +1) at the k +1 th time*Constant is [60, 0 ]]。
The apparatus may be configured to execute the method provided by the method embodiment, and the specific implementation manner and the technical effect are similar and will not be described herein again.
These above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs), among others. For another example, when one of the above modules is implemented in the form of a Processing element scheduler code, the Processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
Fig. 4 is a schematic structural diagram of a second terminal processor adjustment apparatus according to an embodiment of the present application, and as shown in fig. 4, the apparatus includes: a processor 401 and a memory 402, wherein:
the memory 402 is used for storing programs, and the processor 401 calls the programs stored in the memory 402 to execute the above-mentioned method embodiments. The specific implementation and technical effects are similar, and are not described herein again.
Optionally, the invention also provides a program product, for example a computer-readable storage medium, comprising a program which, when being executed by a processor, is adapted to carry out the above-mentioned method embodiments.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute some steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

Claims (10)

1. A method for adjusting a terminal processor, comprising:
acquiring a processor parameter u (k-1) at the k-1 time, a processor parameter u (k-2) at the k-2 time, a katon parameter y (k) at the k time, and a pseudo partial derivative estimator at the k-1 time
Figure FDA0001795615280000011
Wherein k is an integer greater than or equal to 3;
according to the processor parameter u (k-1) at the k-1 time, the processor parameter u (k-2) at the k-2 time, the stuck parameter y (k) at the k time and the pseudo-partial derivative estimation number at the k-1 time
Figure FDA0001795615280000012
And a preset katton parameter y (k +1) at the k +1 th moment*Calculating the pseudo-partial derivative estimation number at the kth time by adopting a model-free self-adaptive control MFAC algorithm
Figure FDA0001795615280000013
According to the processor parameter u (k-1) at the k-1 th moment, the pause parameter y (k) at the k-1 th moment and the pause parameter y (k +1) at the preset k +1 th moment*And the estimated number of pseudo partial derivatives at the k-th time
Figure FDA0001795615280000014
Calculating a processor parameter u (k) at the k-th moment by adopting an MFAC algorithm, wherein the katon parameter y (k) at the k-th moment is data acquired at the k-th moment in real time;
and adjusting the actual processor parameter u (k) at the k time according to the processor parameter u (k) at the k time.
2. The method of claim 1, wherein the computing the pseudo-partial derivative estimate at time k is performed using a model-free adaptive control algorithm (MFAC)
Figure FDA0001795615280000021
The method comprises the following steps:
using a formula
Figure FDA0001795615280000022
Calculating the pseudo partial derivative estimator at the kth moment
Figure FDA0001795615280000023
Where η is the step sequence and Δ u (k-1) is the difference between the processor parameters u (k-1) and u (k-2) at time k-1 and k-2.
3. The method for adjusting a terminal processor according to claim 1, wherein the calculating the processor parameter u (k) at the k-th time by using an MFAC algorithm comprises:
using a formula
Figure FDA0001795615280000024
And calculating the processor parameter u (k) at the k-th time, wherein rho is the step length sequence and lambda is the weighting factor.
4. The method of claim 1, wherein the processor parameter u (k) comprises: the number distribution of different types of cores in the processor and the core frequency of each type of core; the katon parameter y (k) includes a frame rate and a dropped frame number.
5. The method of claim 1, wherein the predetermined katon parameter y (k +1) at time k +1*Constant is [60, 0 ]]。
6. An apparatus for adjusting a terminal processor, comprising: the device comprises an acquisition module, a calculation module and a determination module;
the acquisition module is used for acquiring the processor parameter u (k-1) at the k-1 moment, the processor parameter u (k-2) at the k-2 moment, the katon parameter y (k) at the k moment and the pseudo-partial derivative estimation number at the k-1 moment
Figure FDA0001795615280000031
Wherein k is an integer greater than or equal to 3;
the calculation module is used for estimating the number of pseudo partial derivatives according to the processor parameter u (k-1) at the k-1 moment, the processor parameter u (k-2) at the k-2 moment, the katon parameter y (k) at the k moment and the pseudo partial derivatives at the k-1 moment
Figure FDA0001795615280000032
And a preset katton parameter y (k +1) at the k +1 th moment*Calculating the pseudo-partial derivative estimation number at the kth time by adopting a model-free self-adaptive control MFAC algorithm
Figure FDA0001795615280000033
According to the processor parameter u (k-1) at the k-1 th moment, the pause parameter y (k) at the k-1 th moment and the pause parameter y (k +1) at the preset k +1 th moment*And the estimated number of pseudo partial derivatives at the k-th time
Figure FDA0001795615280000034
Calculating a processor parameter u (k) at the k-th moment by adopting an MFAC algorithm, wherein the katon parameter y (k) at the k-th moment is data acquired at the k-th moment in real time;
and the determining module is used for adjusting the actual processor parameter u (k) at the k-th moment according to the processor parameter u (k) at the k-th moment.
7. The terminal processor adjustment apparatus according to claim 6, wherein the calculation module is specifically configured to:
using a formula
Figure FDA0001795615280000035
Calculating the pseudo partial derivative estimator at the kth moment
Figure FDA0001795615280000036
Where eta is the step length sequenceAnd delta u (k-1) is the difference between the processor parameters u (k-1) and u (k-2) at time k-1 and k-2.
8. The terminal processor adjustment apparatus according to claim 6, wherein the calculation module is further specifically configured to:
using a formula
Figure FDA0001795615280000041
And calculating the processor parameter u (k) at the k-th time, wherein rho is the step length sequence and lambda is the weighting factor.
9. The terminal processor adjustment apparatus of claim 6, wherein the processor parameters u (k) comprise: the number distribution of different types of cores in the processor and the core frequency of each type of core; the katon parameter y (k) includes a frame rate and a dropped frame number.
10. The terminal processor adjustment device according to claim 6, wherein the predetermined katon parameter y (k +1) at the k +1 th time*Constant is [60, 0 ]]。
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