CN109167573A - A kind of demodulator circuit - Google Patents
A kind of demodulator circuit Download PDFInfo
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- CN109167573A CN109167573A CN201810980224.1A CN201810980224A CN109167573A CN 109167573 A CN109167573 A CN 109167573A CN 201810980224 A CN201810980224 A CN 201810980224A CN 109167573 A CN109167573 A CN 109167573A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C1/00—Amplitude modulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
- H04L27/04—Modulator circuits; Transmitter circuits
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Abstract
This application provides a kind of demodulator circuits convenient for integrated, without peripheral amplifier, resistance, capacitor, to reduce the volume and cost and demodulated complex degree of demodulator circuit.The demodulator circuit, comprising: sequentially connected rectification module, band logical amplification module, differential amplification module, decision device and decoder module；Rectification module, for being rectified to the ASK amplitude-modulated signal of input, the ASK amplitude-modulated signal after being rectified；Band logical amplification module obtains ASK envelope signal for the ASK amplitude-modulated signal after rectification to be filtered and amplified；Differential amplification module obtains the demodulated digital signal that the decision device can identify for detecting and amplifying the rising edge and failing edge of the ASK envelope signal；Decision device obtains deburring demodulated digital signal for filtering out the burr of the demodulated digital signal；Decoder module obtains data packets for decoding the deburring demodulated digital signal.
Description
Technical field
The application belongs to electronic technology field, and in particular to a kind of demodulator circuit.
Background technique
The market demand of wireless charging technology is increasing, and wherein the city of the QI standard of wireless charging alliance (WPC) accounts for rate
The most extensively.According to QI standard, release various corresponding signal demodulation schemes in market.
Since the substandard ASK amplitude-modulated signal frequency of QI is down to 2kHz or so, Most current demodulation scheme is low in order to realize
The functions such as pass filter, blocking, it is still desirable to which multiple periphery amplifiers, resistance, capacitor, this is unfavorable for the integrated of demodulator circuit
Change.Therefore these demodulation schemes can no longer meet growing inexpensive demand, be unfavorable for reduce application circuit volume,
Also it is unfavorable for reducing debugging complexity.
Summary of the invention
To solve the above-mentioned problems, this application provides a kind of demodulator circuit can in order to integrated, without peripheral amplifier,
Resistance, capacitor, to reduce the volume and cost and demodulated complex degree of demodulator circuit.
This application provides a kind of demodulator circuits, comprising: sequentially connected rectification module, band logical amplification module, differential are put
Big module, decision device and decoder module；
The rectification module, for being rectified to the ASK amplitude-modulated signal of input, the ASK amplitude-modulated signal after being rectified；
The band logical amplification module obtains ASK envelope for the ASK amplitude-modulated signal after rectification to be filtered and amplified
Signal；
The differential amplification module obtains institute for detecting and amplifying the rising edge and failing edge of the ASK envelope signal
State the demodulated digital signal that decision device can identify；
The decision device obtains deburring demodulated digital signal for filtering out the burr of the demodulated digital signal；
The decoder module obtains data packets for decoding the deburring demodulated digital signal.
Optionally, the band logical amplification module includes: sequentially connected input direct-current biasing circuit, band-pass filter unit
And buffer.
Optionally, the circuit further include: low-pass filter, the low-pass filter are set to the bandpass filter list
Between the connecting pin and ground terminal of the first and described buffer.
Optionally, the band-pass filter unit include: the first amplifier, first capacitor and the second capacitor, first resistor,
Second resistance, 3rd resistor and the 4th resistance；The first resistor and the second resistance are sequentially connected in series；4th resistance and
Second capacitor is sequentially connected in series；Separate described the second of the output end of the input direct-current biasing circuit and the 4th resistance
One end of capacitor connects, one end of separate 4th resistance of second capacitor and the first resistor, first electricity
Hold and the negative input end of first amplifier connects；The second resistance, the first capacitor and first amplifier
Output end connection, output end of the connecting pin as the band-pass filter unit；The positive input of first amplifier
End is connect with the first power supply；The 3rd resistor is connected to the connection of first power supply and the first resistor and second resistance
Between end.
Optionally, the differential amplification module includes: clock generator, differential sluggishness control unit, and is sequentially connected in series
Differentiation element and Cascaded amplification module.
Optionally, the clock generator, for being not overlapping zeroing certainly mutually for input clock signal processing and amplifying
Phase.
Optionally, the differentiation element include: first from zeroing switches, second from zeroing switches, first amplification switch, adopt
Sample capacitor and the second amplifier；Described first amplifies switch in parallel, the band logical amplification module from zeroing switches and described first
Output end connect described first from zeroing switches and it is described first amplification switch the first parallel connected end, described first from zeroing opens
It closes and the second parallel connected end of the first amplification switch is sequentially connected in series with the sampling capacitance, the second amplifier；Described second certainly
Zeroing switches are connected between the input terminal and output end of second amplifier；Described first from zeroing switches and described second
It is closed from zeroing switches when the input clock signal is from zeroing phase, it is disconnected when the input clock signal is amplification phase
It opens；The first amplification switch is disconnected when the input clock signal is from zeroing phase, is to put in the input clock signal
It is closed when big phase.
Optionally, the Cascaded amplification module includes at least one amplifying unit being sequentially connected in series；The amplifying unit packet
Include: self-regulated zero capacitance, amplifier and from zeroing switches, the self-regulated zero capacitance and amplifier series connection are described to open from zeroing
Connection is connected between the input terminal and output end of the amplifier；It is described from zeroing switches the input clock signal be self-regulated
It is closed when zero phase, is disconnected when the input clock signal is amplification phase.
Optionally, the differential sluggishness control unit includes: the register being sequentially connected in series and cascade subelement and self-regulated
Zero negates switch, amplification negates switch and feedback capacity；The input signal of the register control terminal is input clock signal, defeated
Enter clock signal be from zeroing clock, the register be rising edge clock register, the input terminal of the register with it is described
The output end of differential amplification module connects；The cascade subelement includes at least one concatenated amplifier or phase inverter；It is described
The output end for cascading subelement negates switch with the zeroing certainly, the amplification negates switch and connects, and the amplification negates switch
The other end connect with the output end of any amplifier in the concatenated differentiation element and Cascaded amplification module；The feedback electricity
Hold the input terminal for being connected to the next stage amplifier of any amplifier and the zeroing certainly negates switch and takes with the amplification
Between the anti-connecting pin switched；The amplification negates switch closure when the input clock signal is from zeroing phase, described
Input clock signal disconnects when being amplification phase；It is described to break from returning to zero to negate to switch when the input clock signal is from zeroing phase
It opens, is closed when the input clock signal is amplification phase.
Optionally, the differential sluggishness control unit includes: the register being sequentially connected in series and cascade subelement and self-regulated
Zero negates switch, amplification negates switch and feedback capacity；The input signal of the register control terminal is input clock signal, defeated
Enter clock signal be from zeroing clock, the register be rising edge clock register, the input terminal of the register with it is described
The output end of differential amplification module connects；The cascade subelement includes at least one concatenated amplifier or phase inverter；It is described
The output end for cascading subelement negates switch with the zeroing certainly, the amplification negates switch and connects, and the amplification negates switch
The other end connect with the output end of the band logical amplification module；The feedback capacity is connected to the input of second amplifier
End and the zeroing certainly negate switch and the amplification negates between the connecting pin of switch；The amplification negates switch described defeated
Entering clock signal is closure when returning to zero phase certainly, is disconnected when the input clock signal is amplification phase；It is described to be negated out from zeroing
It closes and is disconnected when the input clock signal is from zeroing phase, is closed when the input clock signal is amplification phase.
Optionally, the decision device includes multichannel voting machine.
The application has the advantages that
This demodulator circuit detects by differential amplifying unit and amplifies the rising edge and failing edge of the ASK envelope signal,
Obtain the demodulated digital signal that the determining device can identify；Circuit is simplified, circuit cost is reduced；In addition this demodulator circuit
Without peripheral bulky capacitor or big resistance, being fully integrated, considerably reduce the size of demodulator circuit.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of demodulator circuit disclosed in the present application；
Fig. 2 is the structural schematic diagram of band logical amplification module circuit in Fig. 1 disclosed in the present application；
Fig. 3 is the schematic diagram of the amplitude-frequency response simulation result of band logical amplification module disclosed in the present application；
Fig. 4 is the structural schematic diagram of differential amplification module circuit in Fig. 1 disclosed in the present application；
Fig. 5 is the schematic diagram for the not overlapping clock that clock generator 131 generates in Fig. 4 disclosed in the present application；
Fig. 6 is a kind of concrete structure schematic diagram of the differential amplification module circuit of Fig. 4 disclosed in the present application；
Fig. 7 is another concrete structure schematic diagram of the differential amplification module circuit of Fig. 4 disclosed in the present application；
Fig. 8 is the transient response simulation result schematic diagram of each node in the application circuit.
Specific embodiment
It is as shown in Figure 1 a kind of structural schematic diagram of demodulator circuit disclosed in the present application.The demodulator circuit 100, comprising: according to
Rectification module 110, band logical amplification module 120, differential amplification module 130, determining device 140 and the decoder module 150 of secondary connection；
Rectification module 110, for being rectified to the ASK amplitude-modulated signal of input, the ASK amplitude-modulated signal after being rectified；
Band logical amplification module 120 obtains ASK envelope letter for the ASK amplitude-modulated signal after rectification to be filtered and amplified
Number；
Differential amplification module 130 obtains decision device for detecting and amplifying the rising edge and failing edge of ASK envelope signal
140 demodulated digital signals that can be identified；
Decision device 140 obtains deburring demodulated digital signal for filtering out the burr of demodulated digital signal；
Decoder module 150 obtains data packets for decoding deburring demodulated digital signal.
As shown in Fig. 2, above-mentioned band logical amplification module 120 includes: sequentially connected input direct-current biasing circuit 121, band logical
Filter cell 122 and buffer 123.
Wherein, input direct-current biasing circuit 121 includes: resistance RB1、RB2；Above-mentioned buffer 123 can be buffer buffering
Device, the output end vo 2 of buffer 123 are the output end of band logical amplification module 120.
Above-mentioned band logical amplification module 120 can also include: low-pass filter 124, which is set to band logical
Between filter cell 122 and the connecting pin and ground terminal of buffer 123.The low-pass filter 124 is for further filtering out
High-frequency signal.
Above-mentioned band-pass filter unit 122 includes: the first amplifier, first capacitor C2 and the second capacitor C1, first resistor
R3, second resistance R4,3rd resistor R5 and the 4th resistance R1；
First resistor R3 and second resistance R4 are sequentially connected in series；4th resistance R1 and the second capacitor C1 are sequentially connected in series；Input is straight
The one end far from the second capacitor C1 for flowing the 4th resistance R1 of output end of biasing circuit 121 connects, the second capacitor C1 far from the
Negative input end-the connection of one end of four resistance R1 and first resistor R3, first capacitor C2 and the first amplifier；Second resistance
The output end vo 1 of R4, first capacitor C2 and the first amplifier connect, output end of the connecting pin as band-pass filter unit 122；
The positive input terminal of first amplifier is connect with the first power supply VCM；3rd resistor R5 is connected to the first power supply VCM and first resistor R3
Between the connecting pin of second resistance R4.The whole transmission function of bandpass amplifier described in Fig. 2 can be expressed as following formula:
Wherein poleCapacitance multiplication function is shown, increase can be passed throughValue, reduce pole, play
It reduces capacity area and then reduces the effect of cost.It is illustrated in figure 3 the gain amplitude-frequency characteristic of band logical amplification module 120.Its
Middle dotted line indicates the amplitude-frequency characteristic of low-pass filter input signal, and solid line indicates the whole amplitude-frequency characteristic of bandpass amplifier.
Be illustrated in figure 4 the circuit diagram of differential amplification module 130, differential amplification module 130 include: clock generator 131,
Differential sluggishness control unit 134, and the differentiation element 132 and Cascaded amplification module 133 that are sequentially connected in series.
Wherein, clock generator 131, for handling input clock signal for the not overlapping phase of zeroing certainly and amplification phase.
It is illustrated in figure 5 the schematic diagram of the not overlapping clock of the generation of clock generator 131.Wherein ΦazFor zeroing clock certainly, Φ bazFor
From negating for zeroing clock, ΦampTo amplify clock, Φ bampFor negating for amplification clock.
As shown in fig. 6, above-mentioned differentiation element 132 include: first from zeroing switches 1321, second from zeroing switches 1322,
First amplification switch 1323, sampling capacitance C1 and the second amplifier；First amplifies switch 1323 from zeroing switches 1321 and first
Parallel connection, the connection of output end vo 2 first of band logical amplification module from zeroing switches 1321 and the first amplification switch 1323 first simultaneously
Join end, first amplifies the second parallel connected end and sampling capacitance C1, the second amplifier of switch 1323 from zeroing switches 1321 and first
It is sequentially connected in series；Second is connected between the input terminal and output end of the second amplifier from zeroing switches 1322；First opens from zeroing
It closes 1321 and second to be closed from zeroing switches 1322 when input clock signal is from zeroing phase, is amplification in input clock signal
It is disconnected when phase；First amplification switch 1323 is disconnected when input clock signal is from zeroing phase, is amplification in input clock signal
It is closed when phase.
Above-mentioned differentiation element 132 is used to detect and amplify the difference in the front and back period of its input signal.In the self-regulated of clock
Zero phase, amplifier both ends are closed the switch from zeroing, and the left pole plate of sampling capacitance C1 acquires input signal, the right pole plate of sampling capacitance C1
Acquire the offset voltage that amplifier is formed from zeroing；In the amplification phase of clock, amplifier both ends are disconnected from zeroing switches, sampling
The left pole plate of capacitor C1 continues to acquire input signal, after the completion of amplifier is established, exports the differential signal after being amplified, the differential
Signal, that is, input signal is in amplification phase and the difference from the phase that returns to zero.
With continued reference to Fig. 6, above-mentioned Cascaded amplification module 133 includes the 1330 (Fig. 6 of at least one amplifying unit being sequentially connected in series
It show two amplifying units)；Amplifying unit 1330 includes: self-regulated zero capacitance C0, amplifier and from zeroing switches 1331, self-regulated
Zero capacitance C0 and amplifier series connection, are connected between the input terminal of amplifier and output end from zeroing switches 1331；It is opened from zeroing
It closes 1331 to be closed when input clock signal is from zeroing phase, be disconnected when input clock signal is amplification phase.
Cascaded amplification module 133 is used to amplify the output signal of differentiation element 132, until output decision circuit can identify
Voltage.In clock from zeroing phase, amplifier unit is closed the switch from zeroing, the output of the left pole plate acquisition prime of capacitor C0
Imbalance, the offset voltage of right pole plate acquisition amplifier；In the amplification phase of clock, amplifying unit is disconnected from zeroing switches, amplification
The output signal of prime is further amplified device.Multiple amplifying units help to improve whole gain amplifier, to improve inspection
Survey resolution ratio.
With continued reference to Fig. 6, above-mentioned differential sluggishness control unit 134 includes: the register being sequentially connected in series and cascade subelement
1340, and from zeroing negates switch 1341, amplification negates switch 1342 and feedback capacity C；
The input signal of the register control terminal is input clock signal, and input clock signal is from zeroing clock, institute
Stating register is rising edge clock register；
Cascading subelement 1340 includes at least one concatenated amplifier or phase inverter (being illustrated as two phase inverters)；
The output end of subelement 1340 is cascaded with from zeroing negates switch 1341, amplification negates switch 1342 and connects, is amplified
The other end for negating switch 1342 connect (figure with the output end of any amplifier in concatenated differentiation element and Cascaded amplification module
In, the amplifier out of the other end and differentiation element that amplification negates switch 1342 connects)；Feedback capacity C is connected to this
(in figure, one end of feedback capacity C is connected to first of Cascaded amplification module to the input terminal of the next stage amplifier of one amplifier
Amplifier in) and negate switch C from zeroing and amplify between the connecting pin for negating switch；Amplification negates switch 1342 defeated
Entering clock signal is closure when returning to zero phase certainly, is disconnected when input clock signal is amplification phase；Switch 1342 is negated from zeroing to exist
Input clock signal is to disconnect when returning to zero phase certainly, is closed when input clock signal is amplification phase.
Differential sluggishness control unit 134 acts on for realizing two: first is that eliminating influence of the noise to differential function, preventing
Maloperation；Second is that when signal differentiation value is approximate or when be 0 (voltage saturation or temporary stabilization), a maintenance upper period
Differentiation result.Differential sluggishness control unit generates corresponding signal and feeds back to pre-amplifier according to the output voltage of differentiator
Or first differentiator, to have the function that sluggish control.
A kind of implementation of differential sluggishness control unit 134: the registers latch of control circuit is contained as shown in Figure 6
The output valve of upper periodic differential device, control circuit are high (or low) according to the current data of register, correspondingly by power supply electricity
Press (or ground) by capacitive feedback to pre-amplifier, to realize sluggish control.Hysteresis voltage in figure can be by following
Expression formula is configured.
Wherein assume that input and output voltage operating point of the amplifier from after returning to zero is located at the half of supply voltage, i.e.,
0.5VDD；Gain is the gain of the first differentiation element.
The alternatively specific structure of differential amplification module circuit, as shown in fig. 7, differential sluggishness control unit 134
It include: the register being sequentially connected in series and cascade subelement, and from zeroing negates switch 1341, amplification negates switch 1342 and anti-
Feed holds C；
The input signal of register control terminal is input clock signal, and input clock signal is from zeroing clock, register
For rising edge clock register, the input terminal of register is connect with the output end of the differential amplification module；
Cascading subelement includes at least one concatenated amplifier or phase inverter (being illustrated as two phase inverters)；Cascade
For the output end of unit with from zeroing negates switch 1341, amplification negates switch 1342 and connects, amplification negates the another of switch 1342
End is connect with the output end vo 2 of band logical amplification module；Feedback capacity C is connected to the input terminal of the second amplifier and negates from zeroing
Switch 1341 and amplification negate between the connecting pin of switch 1342；It is from zeroing that amplification, which negates switch 1342 in input clock signal,
It is closed when phase, is disconnected when input clock signal is amplification phase；Negating switch 1342 in input clock signal from zeroing is self-regulated
It disconnects when zero phase, is closed when input clock signal is amplification phase.
Above-mentioned decision device is Digital Logical Circuits, for handling the output of differential amplification module, and then is ruled out final defeated
Result out.Decision device may include multichannel voting machine, may be due to the output burr of noise generation to filter out differentiator.
It should be noted that the circuit of the attached drawing is all single-ended signal processing, but the application is equally applicable to fully differential
Signal processing.
It is illustrated in figure 8 the transient response emulation schematic diagram of important node of the invention.Wherein, VINDIt is from wireless charging
Electric coil, ASK modulated signal comprising data packets；VINIt is the data information envelope signal after over commutation；Vo1Be through
Cross the voltage signal of the bandpass filtering unit of bandpass filtering modules block；VoIt is the output signal of differential amplification module；VoutIt is decision device
Final output signal.It, can be by the final output signal of decision device in conjunction with the decoding circuit or microcontroller (MCU) of rear class
It is further processed, obtains digital data information packet.
It is the embodiment of the embodiment of the present invention above, it is noted that those skilled in the art are come
It says, without departing from the principles of the embodiments of the present invention, several improvements and modifications can also be made, these improvements and modifications
It is considered as protection scope of the present invention.
Claims (10)
1. a kind of demodulator circuit characterized by comprising sequentially connected rectification module, band logical amplification module, differential amplify mould
Block, decision device and decoder module；
The rectification module, for being rectified to the ASK amplitude-modulated signal of input, the ASK amplitude-modulated signal after being rectified；
The band logical amplification module obtains ASK envelope signal for the ASK amplitude-modulated signal after rectification to be filtered and amplified；
The differential amplification module obtains described sentencing for detecting and amplify the rising edge and failing edge of the ASK envelope signal
The certainly demodulated digital signal that device can identify；
The decision device obtains deburring demodulated digital signal for filtering out the burr of the demodulated digital signal；
The decoder module obtains data packets for decoding the deburring demodulated digital signal.
2. circuit according to claim 1, which is characterized in that the band logical amplification module includes: sequentially connected input
DC bias circuit, band-pass filter unit and buffer.
3. circuit according to claim 2, which is characterized in that the circuit further include: low-pass filter, the low pass filtered
Wave device is set between the band-pass filter unit and the connecting pin and ground terminal of the buffer.
4. circuit according to claim 2 or 3, which is characterized in that the band-pass filter unit includes: the first amplification
Device, first capacitor and the second capacitor, first resistor, second resistance, 3rd resistor and the 4th resistance；
The first resistor and the second resistance are sequentially connected in series；
4th resistance and second capacitor are sequentially connected in series；
The output end of the input direct-current biasing circuit is connect with one end far from second capacitor of the 4th resistance, institute
Amplify with the first resistor, the first capacitor and described first one end far from the 4th resistance for stating the second capacitor
The negative input end of device connects；
The second resistance, the first capacitor are connected with the output end of first amplifier, described in the connecting pin conduct
The output end of band-pass filter unit；
The positive input terminal of first amplifier is connect with the first power supply；The 3rd resistor is connected to first power supply and institute
It states between first resistor and the connecting pin of second resistance.
5. circuit according to claim 1, which is characterized in that the differential amplification module includes: clock generator, differential
Sluggish control unit, and the differentiation element and Cascaded amplification module that are sequentially connected in series.
6. circuit according to claim 5, which is characterized in that the clock generator, being used for will be at input clock signal
It manages as the not overlapping phase of zeroing certainly and amplification phase.
7. circuit according to claim 6, which is characterized in that the differentiation element includes: first from zeroing switches, second
From zeroing switches, the first amplification switch, sampling capacitance and the second amplifier；
Described first from zeroing switches and it is described first amplification switch in parallel, the band logical amplification module output end connection described in
First the first parallel connected end switched from zeroing switches and first amplification, described first amplifies from zeroing switches and described first
Second parallel connected end of switch is sequentially connected in series with the sampling capacitance, the second amplifier；
Described second between the input terminal and output end that zeroing switches are connected to second amplifier；
Described first is closed from zeroing switches when the input clock signal is from zeroing phase from zeroing switches and described second,
It is disconnected when the input clock signal is amplification phase；
The first amplification switch is disconnected when the input clock signal is from zeroing phase, is to put in the input clock signal
It is closed when big phase.
8. circuit as claimed in claim 7, which is characterized in that the Cascaded amplification module includes at least one being sequentially connected in series
Amplifying unit；
The amplifying unit includes: self-regulated zero capacitance, amplifier and from zeroing switches, the self-regulated zero capacitance and the amplifier
Series connection, it is described to be connected between the input terminal and output end of the amplifier from zeroing switches；
It is described to be closed from zeroing switches when the input clock signal is from zeroing phase, it is amplification in the input clock signal
It is disconnected when phase.
9. circuit as claimed in claim 8, which is characterized in that the differential sluggishness control unit includes: posting of being sequentially connected in series
Storage and cascade subelement, and from zeroing negates switch, amplification negates switch and feedback capacity；
The input signal of the register control terminal is input clock signal, and input clock signal is the clock that returns to zero certainly, described to post
Storage is rising edge clock register, and the input terminal of the register is connect with the output end of the differential amplification module；
The cascade subelement includes at least one concatenated amplifier or phase inverter；
The output end of the cascade subelement is with described from zeroing negates switch, the amplification negates switch and connects, the amplification
The other end for negating switch is connect with the output end of any amplifier in the concatenated differentiation element and Cascaded amplification module；Institute
State feedback capacity be connected to any amplifier next stage amplifier input terminal and it is described from zeroing negate switch and institute
Amplification is stated to negate between the connecting pin of switch；
The amplification negates switch closure when the input clock signal is from zeroing phase, is to put in the input clock signal
It is disconnected when big phase；
It is described to negate switch disconnection when the input clock signal is from zeroing phase from zeroing, be in the input clock signal
It is closed when amplifying phase.
10. circuit as claimed in claim 8, which is characterized in that
The differential sluggishness control unit includes: the register that is sequentially connected in series and cascade subelement, and from zeroing negate switch,
Amplification negates switch and feedback capacity；
The input signal of the register control terminal is input clock signal, and input clock signal is the clock that returns to zero certainly, described to post
Storage is rising edge clock register, and the input terminal of the register is connect with the output end of the differential amplification module；
The cascade subelement includes at least one concatenated amplifier or phase inverter；
The output end of the cascade subelement is with described from zeroing negates switch, the amplification negates switch and connects, the amplification
The other end for negating switch is connect with the output end of the band logical amplification module；The feedback capacity is connected to second amplification
The input terminal of device and the zeroing certainly negate switch and the amplification negates between the connecting pin of switch；
The amplification negates switch closure when the input clock signal is from zeroing phase, is to put in the input clock signal
It is disconnected when big phase；
It is described to negate switch disconnection when the input clock signal is from zeroing phase from zeroing, be in the input clock signal
It is closed when amplifying phase.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109962871A (en) * | 2019-03-28 | 2019-07-02 | 四川中微芯成科技有限公司 | ASK amplitude-modulated signal envelope detected system |
| CN110071560A (en) * | 2019-05-24 | 2019-07-30 | 深圳市乐得瑞科技有限公司 | A kind of wireless charging control circuit |
| CN116318213A (en) * | 2023-03-15 | 2023-06-23 | 浙江地芯引力科技有限公司 | Data receiving circuit and data transmission device |
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| US4065722A (en) * | 1976-12-27 | 1977-12-27 | Glenayre Electronics, Ltd. | Demodulation method and circuit for discretely modulated ac signals |
| US5949826A (en) * | 1995-12-22 | 1999-09-07 | Matsushita Electric Industrial Co., Ltd. | Data transmission and reception system |
| US20090185640A1 (en) * | 2007-05-16 | 2009-07-23 | Huawei Technologies Co., Ltd. | Demodulation circuit, digital microwave system and demodulation method |
| CN101789921A (en) * | 2009-01-23 | 2010-07-28 | 中芯国际集成电路制造(上海)有限公司 | Amplitude shift keying demodulator and method |
| US20100189196A1 (en) * | 2009-01-23 | 2010-07-29 | Semiconductor Manufacturing International (Shanghai) Corporation | Amplitude shift keyed (ask) demodulation pattern and use in radio frequency identification (rfid) |
| US20110164704A1 (en) * | 2010-01-07 | 2011-07-07 | Mstar Semiconductor, Inc. | Amplitude Modulation Demodulating Circuit and Method Thereof |
| CN105989313A (en) * | 2015-01-31 | 2016-10-05 | 江苏中科易正电子科技有限公司 | Radio-frequency identification label chip ASK demodulator and demodulation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109962871A (en) * | 2019-03-28 | 2019-07-02 | 四川中微芯成科技有限公司 | ASK amplitude-modulated signal envelope detected system |
| CN109962871B (en) * | 2019-03-28 | 2021-07-23 | 四川中微芯成科技有限公司 | ASK amplitude modulation signal envelope detection system |
| CN110071560A (en) * | 2019-05-24 | 2019-07-30 | 深圳市乐得瑞科技有限公司 | A kind of wireless charging control circuit |
| CN116318213A (en) * | 2023-03-15 | 2023-06-23 | 浙江地芯引力科技有限公司 | Data receiving circuit and data transmission device |
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