CN109166598B - Sense amplifier circuit, memory and signal amplifying method - Google Patents
Sense amplifier circuit, memory and signal amplifying method Download PDFInfo
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- CN109166598B CN109166598B CN201810940783.XA CN201810940783A CN109166598B CN 109166598 B CN109166598 B CN 109166598B CN 201810940783 A CN201810940783 A CN 201810940783A CN 109166598 B CN109166598 B CN 109166598B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
Abstract
The embodiment of the disclosure provides a sense amplifier circuit, a memory and a signal amplifying method, wherein the sense amplifier circuit comprises a sense amplifier, one end of the sense amplifier is connected with a first data line, and the other end of the sense amplifier is connected with a second data line; a first semiconductor switching element, a first end of which is connected with a first bit line, a second end of which is connected with the first data line, and a control end of which receives a first control signal; the first semiconductor switching element changes the opening degree according to the first control signal and the signal transmitted by the first bit line; a second semiconductor switching element having a first end connected to the second bit line, a second end connected to the second data line, and a control end receiving a second control signal; the second semiconductor switching element changes the turn-on degree according to a second control signal and a signal transmitted by the second data line. The sense amplifier circuit provided by the embodiment of the disclosure can reduce bit line coupling noise and improve overall sensing efficiency.
Description
Technical Field
The disclosure relates to the technical field of electronics, in particular to a sense amplifier circuit, a memory and a signal amplifying method.
Background
A Sense Amplifier (SA) is a functional device applied to a semiconductor memory, and when the Sense Amplifier is turned on at a proper time point, a weak signal stored in a memory cell can be amplified, so that data stored in the memory cell can be correctly written or read.
Referring to FIG. 1A, a conventional sense amplifier senses due to the coupling capacitance C existing between adjacent Bit lines (Bit lines) BL-BL The sense signal of the target bit line BL_T is affected by the sense signals of the adjacent bit line BL_N1 and the adjacent bit line BL_N2, and the resulting non-ideal effect is referred to as bit line coupling noise (Bit Line Coupling Noise) as shown in FIG. 1B. If the sense signal of the target sense amplifier SA_T and the sense signal of the adjacent sense amplifier SA_n1 or SA_n2 are opposite, the strongest coupling effect will be generated, so that the sense performance of the target sense amplifier SA_T will be weakened, and the sense malfunction will be caused in severe casesAnd (3) doing so.
It follows that there is a need for a new sense amplifier circuit that overcomes the drawbacks of the related art.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The disclosure is directed to a sense amplifier circuit, a memory and a signal amplifying method, and further, at least to some extent, to overcome the technical problems of strong bit line coupling effect and weakening of sense performance of the sense amplifier caused by the limitations and defects of the related art.
According to one aspect of the present disclosure, there is provided a sense amplifier circuit characterized by comprising:
one end of the sense amplifier is connected with the first data line, and the other end of the sense amplifier is connected with the second data line;
the first semiconductor switch element is connected with a first bit line at a first end, a first data line at a second end and a control end, wherein the control end receives a first control signal; the first semiconductor switching element changes the opening degree according to the first control signal and the signal transmitted by the first bit line;
a second semiconductor switching element, a first end of which is connected with a second bit line, a second end of which is connected with the second data line, and a control end of which receives a second control signal; the second semiconductor switching element changes an opening degree according to the second control signal and a signal transmitted by the second data line.
In an exemplary embodiment of the present disclosure, the first control signal and the second control signal are the same signal.
In one exemplary embodiment of the present disclosure, the first semiconductor switching element includes a first transistor having a first pole connected to the first bit line, a second pole connected to the first data line, and a gate receiving the first control signal.
In one exemplary embodiment of the present disclosure, the first transistor is an NMOS transistor.
In one exemplary embodiment of the present disclosure, the second semiconductor switching element includes a second transistor having a first electrode connected to the second data line, a second electrode connected to the second bit line, and a gate receiving the second control signal.
In an exemplary embodiment of the present disclosure, the second transistor is an NMOS transistor.
In one exemplary embodiment of the present disclosure, the sense amplifier includes:
the precharge circuit is respectively connected with the first data line and the second data line, and a control end of the precharge circuit receives an equalization control signal;
and the two induction signal input ends of the induction amplifying circuit respectively receive a first induction signal and a second induction signal.
In one exemplary embodiment of the present disclosure, the precharge circuit includes:
a third transistor having a first electrode connected to the first data line and a second electrode connected to the second data line, and a gate receiving the equalization control signal;
a first electrode of the fourth transistor is connected with the first data line, a second electrode of the fourth transistor receives a charging signal, and a grid electrode of the fourth transistor receives the balance control signal;
and a fifth transistor, a first pole of which is connected with the second data line, a second pole of which receives the charging signal, and a gate of which receives the equalization control signal.
In an exemplary embodiment of the present disclosure, the third transistor, the fourth transistor, and the fifth transistor are all NMOS transistors.
In one exemplary embodiment of the present disclosure, the sense amplifying circuit includes:
a sixth transistor, a first pole of which is connected with the second data line, a second pole of which receives the first induction signal, and a grid of which is connected with the first data line;
a seventh transistor, a first pole of which is connected with the first data line, a second pole of which receives the first induction signal, and a grid of which is connected with the second data line;
an eighth transistor, a first pole of which is connected to the second data line, a second pole of which receives the second sensing signal, and a gate of which is connected to the first data line;
and a ninth transistor, wherein a first pole of the ninth transistor is connected with the first data line, a second pole of the ninth transistor receives the second sensing signal, and a grid electrode of the ninth transistor is connected with the second data line.
In one exemplary embodiment of the present disclosure, the sixth transistor and the seventh transistor are PMOS transistors, and the eighth transistor and the ninth transistor are NMOS transistors.
According to one aspect of the present disclosure, there is provided a memory characterized by comprising a plurality of sense amplifier circuits as any of the above.
According to an aspect of the present disclosure, there is provided a signal amplifying method, which is characterized by comprising:
in the precharge stage, the first semiconductor switching element and the second semiconductor switching element are turned on by the first control signal and the second control signal respectively, and the first data line, the first bit line, the second data line and the second bit line are charged to a first voltage by the equalizing control signal;
in the charge sharing stage, charge sharing is carried out through a coupling capacitor between the first data line and the adjacent sense amplifier circuit, and signals of the first data line and the first bit line rise to a second voltage;
in the blocking stage, a first control signal is used for controlling the half-on of the first semiconductor switching element, and signal transmission between the first bit line and the first data line is blocked; controlling the second semiconductor switching element to be half-on by using a second control signal, and blocking signal transmission between the second bit line and the second data line;
in the sensing stage, the voltage difference between the first data line and the second data line is controlled and amplified by using the first sensing signal and the second sensing signal, so that the first data line signal is increased to a third voltage, and the second data line signal is decreased to a fourth voltage; in response to the voltage drop of the second data line signal, the second semiconductor switching element is turned on to gradually drop the second bit line voltage;
in the recovery stage, the first semiconductor element is controlled to be overloaded and started by a first control signal, so that a first bit line signal is raised to a third voltage; and controlling the overload start of the second semiconductor element by using a second control signal to enable the second bit line signal to drop to a fourth voltage.
In the sense amplifier circuit provided in the embodiments of the present disclosure, by timing control of the first semiconductor switching element Q1 and the second semiconductor switching element Q2, the signal swing generated in the sensing process of the sense amplifier SA can be blocked from the coupling capacitance C BL-BL Thereby reducing bit line coupling noise and improving the overall sensing performance of the sense amplifier circuit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.
Fig. 1A is a schematic diagram of a sense amplifier circuit in the related art.
FIG. 1B is a schematic diagram showing the effect of coupling effect on the sense amplification of the bit line signal.
Fig. 2 is a schematic diagram of a sense amplifier circuit in an exemplary embodiment of the present disclosure.
Fig. 3 is a schematic diagram of a sense amplifier circuit in another exemplary embodiment of the present disclosure.
Fig. 4 is a schematic diagram of a sense amplifier circuit in another exemplary embodiment of the present disclosure.
Fig. 5 is a flowchart of signal amplification method steps in another exemplary embodiment of the present disclosure.
Fig. 6 is an effect diagram of a signal amplifying method in an exemplary embodiment of the present disclosure.
Fig. 7A is a schematic diagram showing the effects of partial stages (precharge stage to charge sharing stage) of a signal amplifying method according to an exemplary embodiment of the present disclosure.
Fig. 7B is a schematic diagram showing the effect of partial stages (charge sharing stage to blocking stage) of a signal amplifying method according to an exemplary embodiment of the present disclosure.
Fig. 7C is an effect diagram of a partial stage (blocking stage to sensing stage) of a signal amplifying method according to an exemplary embodiment of the present disclosure.
Fig. 7D is an effect diagram of partial stages (sensing stage to recovery stage) of a signal amplifying method according to an exemplary embodiment of the present disclosure.
Fig. 8 is a schematic diagram comparing sense amplifier circuitry in an exemplary embodiment of the present disclosure with conventional sense amplifier circuitry in sense amplification.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.
Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and do not limit the number of their objects.
In an exemplary embodiment of the present disclosure, a sense amplifier circuit that can be applied to a semiconductor memory to amplify weak signals held in a memory cell of the memory is first provided. The semiconductor memory may be a dynamic random access memory DRAM, a static random access memory SRAM, or any other memory device having data writing and data reading functions.
Referring to FIG. 2, three sense amplifier circuits according to the present exemplary embodiment are provided adjacent to each other, wherein a coupling capacitance C is present between bit lines of each two adjacent sense amplifier circuits BL-BL 。
In a conventional sense amplifier circuit, each sense amplifier is connected to two signal transmission lines of a memory, respectively. While the sense amplifier circuit provided in the present exemplary embodiment may mainly include: a sense amplifier SA, a first semiconductor switching element Q1, and a second semiconductor switching element Q2. The first semiconductor device Q1 divides the signal transmission line connected to one side of the sense amplifier SA into a first bit line BL and a first data line DL, and the first semiconductor device Q2 divides the signal transmission line connected to the other side of the sense amplifier SA into a second bit line BLB and a second data line DLB.
Specifically, one end of the sense amplifier SA is connected to the first data line DL, and the other end of the sense amplifier SA is connected to the second data line DLB.
The first semiconductor switching element Q1 has a first end connected to the first bit line BL, a second end connected to the first data line DL, and a control end receiving a first control signal ISO1. The first semiconductor switching element Q1 may change its turn-on level according to the first control signal ISO1 and the signal transmitted on the first bit line BL, for example, the first semiconductor switching element Q1 may be maintained in a plurality of different turn-on levels such as a turned-off state, a half-on state, a full-on state, and an overload turn-on state according to control of the related signals. The degree of opening of the first semiconductor switching element Q1 can be adjusted accordingly in response to the change in the related signal.
The first terminal of the second semiconductor switching element Q2 is connected to the second bit line BLB, the second terminal is connected to the second data line DLB, and the control terminal receives the second control signal ISO2. The second semiconductor switching element Q2 may change its own turn-on degree according to the second control signal ISO2 and the signal transmitted on the second data line DLB. Similar to the first semiconductor switching element Q1, the second semiconductor switching element Q2 can be also maintained in various degrees of opening such as an off state, a half-on state, a full-on state, and an overload-on state according to control of the related signals. The degree of turn-on of the second semiconductor switching element Q2 can be adjusted accordingly according to the change of the related signal.
Due to the presence of the first semiconductor switching element Q1 and the second semiconductor switching element Q2, when the sense amplifier circuit provided in the present exemplary embodiment is used to sense-amplify the relevant signals, the degree of turn-on of the first semiconductor switching element Q1 and the second semiconductor switching element Q2 can be changed by control of the relevant signals at different timing stages. Thus, it is possible toThe signal transmission between the first bit line BL and the first data line DL may be turned on or blocked when necessary, and the signal transmission between the second bit line BLB and the second data line DLB may be turned on or blocked when necessary. Furthermore, the degree of conduction of the signal transmission can be adjusted by changing the degree of opening of the semiconductor switching element. In other words, by timing control of the first and second semiconductor switching elements Q1 and Q2, the signal swing generated during sensing of the sense amplifier SA can be blocked from the coupling capacitance C BL-BL Thereby reducing bit line coupling noise and improving the overall sensing performance of the sense amplifier circuit.
Referring to fig. 3, the first control signal ISO1 and the second control signal ISO2 may be the same control signal ISO on the basis of the above exemplary embodiment. In the sensing process of a sense amplifier circuit, a single control signal ISO can control the opening degree of the first semiconductor switching element Q1 and the opening degree of the second semiconductor switching element Q2 simultaneously, so that the circuit is simplified, the control efficiency is improved, and the control stability is improved.
In addition, in the present exemplary embodiment, the first semiconductor switching element Q1 may include a first transistor having a first pole connected to the first bit line BL and a second pole connected to the first data line DL, and a gate receiving the first control signal ISO1, that is, receiving the control signal ISO.
The second semiconductor switching element Q2 includes a second transistor having a first electrode connected to the second data line DLB and a second electrode connected to the second bit line BLB, and a gate receiving the second control signal ISO2, i.e., the control signal ISO.
In the present exemplary embodiment, the first transistor in the first semiconductor switching element Q1 may be an NMOS transistor, a PMOS transistor, or any other transistor component, and the second semiconductor switching element Q2 may be an NMOS transistor, a PMOS transistor, or any other transistor component, which is not particularly limited in this exemplary embodiment.
The semiconductor switching element is formed by adopting basic transistor components in the exemplary embodiment, and has the advantages of simple circuit structure, low cost and good stability.
Referring to fig. 4, in one exemplary embodiment of the present disclosure, a sense amplifier may mainly include a precharge circuit 410 and a sense amplifying circuit 420.
The precharge circuit 410 is connected to the first data line DL and the second data line DLB, respectively, and the control terminal of the precharge circuit 410 receives an equalization control signal EQ.
The sense amplifying circuit 420 is connected to the first data line DL and the second data line DLB, respectively, and two sense signal input terminals of the sense amplifying circuit 420 receive the first sense signal SAP and the second sense signal SAN, respectively.
In the present exemplary embodiment, the precharge circuit 410 may further include: a third transistor Q3, a fourth transistor Q4, and a fifth transistor Q5.
The first pole of the third transistor Q3 is connected to the first data line DL, the second pole is connected to the second data line DLB, and the gate receives the equalization control signal EQ.
The first pole of the fourth transistor Q4 is connected to the first data line DL, the second pole receives a charging signal DVC2, and the gate receives an equalization control signal EQ.
The first pole of the fifth transistor Q5 is connected to the second data line DLB, the second pole receives the charging signal DVC2, and the gate receives the equalization control signal EQ.
The precharge circuit 410 may precharge the first bit line BL, the second bit line BLB, the first data line DL, and the second data line DLB under the driving of the equalization control signal EQ.
Note that, the third transistor Q3, the fourth transistor Q4, and the fifth transistor Q5 may be NMOS transistors, PMOS transistors, or any other transistor components. In addition, in the case of realizing the same or similar circuit functions, the precharge circuit 410 provided in the present exemplary embodiment may be any other alternative circuit, which is not particularly limited in the present exemplary embodiment.
In the present exemplary embodiment, the sense amplifying circuit 420 may mainly include: a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, and a ninth transistor Q9.
The first pole of the sixth transistor Q6 is connected to the second data line DLB, the second pole receives the first sensing signal SAP, and the gate is connected to the first data line DL.
The seventh transistor Q7 has a first pole connected to the first data line DL, a second pole receiving the first sensing signal SAP, and a gate connected to the second data line DLB.
The first pole of the eighth transistor Q8 is connected to the second data line DLB, the second pole receives the second sensing signal SAN, and the gate is connected to the first data line DL.
The first pole of the ninth transistor is connected to the first data line DL, the second pole receives the second sense signal SAN, and the gate is connected to the second data line DLB.
The sense amplifying circuit 420 may sense and amplify the transmission signals in the first bit line BL, the second bit line BLB, the first data line DL, and the second data line DLB under the synergistic effect of the first sense signal SAP and the second sense signal SAN.
In the present exemplary embodiment, the sixth transistor Q6 and the seventh transistor Q7 may be PMOS transistors, and the eighth transistor Q8 and the ninth transistor Q9 may be NMOS transistors. In other embodiments, the sixth transistor Q6, the seventh transistor Q7, the eighth transistor Q8, and the ninth transistor Q9 may be NMOS transistors, PMOS transistors, or any other transistor components as desired. In addition, in the case of implementing the same or similar circuit functions, the sense amplifier circuit 420 provided in the present exemplary embodiment may be any other alternative circuit, which is not particularly limited in the present exemplary embodiment.
In another exemplary embodiment of the present disclosure, a memory is provided that includes a plurality of sense amplifier circuits as provided in any of the above exemplary embodiments, with a coupling capacitance between each two adjacent sense amplifier circuits. The specific composition of the sense amplifier circuit has been described in detail in the above exemplary embodiments, and thus will not be described here again.
In another exemplary embodiment of the present disclosure, a signal amplifying method is provided, which may mainly include the steps of:
step S510, in the precharge stage, the first semiconductor switching element and the second semiconductor switching element are turned on by the first control signal and the second control signal, respectively, and the first data line, the first bit line, the second data line and the second bit line are charged to the first voltage by the equalizing control signal.
In the present exemplary embodiment, the first control signal ISO1 and the second control signal ISO2 are the same control signal ISO. Referring to fig. 6 and 7A, during the precharge phase, first data line DL and second data line DLB will be charged to a first voltage (e.g., VDD/2 shown in fig. 6) first by control of equalization control signal EQ, and since control signal ISO is maintained at voltage VDD, first semiconductor element Q1 and second semiconductor element Q2 are both in an on state, and thus do not affect the function implementation of sense amplifier SA, first bit line BL and second bit line BLB will also be maintained at the same voltage VDD/2 as first data line DL and second data line DLB.
In step s520, in the charge sharing stage, the signals of the first data line and the first bit line rise to the second voltage through charge sharing with the coupling capacitance between the adjacent sense amplifier circuits.
Referring to fig. 6, 7A and 7B, in the charge sharing stage, the control signal ISO is continuously maintained at the voltage VDD, and the first semiconductor device Q1 and the second semiconductor device Q2 are in the on state, so that the signal transmission between the first data line DL and the first bit line BL is not blocked, and the signal transmission between the second data line DLB and the second bit line BLB is not blocked. The memory cells of the memory share charges through the coupling capacitance between the adjacent sense amplifier circuits, so that the first data line DL and the first bit line BL rise to the second voltage at the same time.
S530, in a blocking stage, controlling the half-on of the first semiconductor switching element by using a first control signal to block signal transmission between the first bit line and the first data line; and controlling the second semiconductor switching element to be half-on by using a second control signal, and blocking signal transmission between the second bit line and the second data line.
In the blocking phase, the first semiconductor switching element Q1 may be controlled to be half-on by the first control signal ISO1, and the second semiconductor switching element Q2 may be controlled to be half-on by the second control signal ISO2. In the present exemplary embodiment, the first control signal ISO1 and the second control signal ISO2 are the same control signal ISO. Referring to fig. 6, 7B and 7C, the control signal ISO is reduced from the voltage VDD to the voltage VDD/2, and continues to block the signal transmission between the first bit line BL and the first data line DL, and also continues to block the signal transmission between the second bit line BLB and the second data line DLB.
S540, in a sensing stage, the voltage difference between the first data line and the second data line is controlled and amplified by using the first sensing signal and the second sensing signal, so that the first data line signal is increased to a third voltage, and the second data line signal is decreased to a fourth voltage; in response to the voltage drop of the second data line signal, the second semiconductor switching element is turned on, so that the second bit line voltage gradually drops.
Referring to fig. 6, 7C and 7D, during the sensing phase, the control signal ISO is maintained at the voltage VDD/2, the first and second semiconductor switching elements Q1 and Q2 are continuously turned on half, and the sense amplifier SA amplifies the voltage difference between the first and second data lines DL and DLB under the synergistic effect of the first and second sense signals SAP and SAN, so that the signal of the first data line DL rises to the third voltage and the signal of the second data line DLB drops to the fourth voltage. In this stage, due to V GS,Q1 ＝V ISO -V BL ＜V TN Wherein V is ISO For controlling the voltage of the signal ISO, V BL For the voltage of the first bit line BL, V TN Since the threshold voltage of the first semiconductor switching element Q1 is set, the first semiconductor switching element Q1 is turned off, and the voltage of the first bit line BL is not affected by the voltage of the first data line DL. And due to V GS,Q2 ＝V ISO -V DLB ＞V TN Wherein V is DLB For the second dataThe voltage on line DLB, and therefore the second semiconductor switching element Q2, is turned on, and enters the source follower configuration (source follower configuration), so that the voltage on the second bit line BLB gradually drops and approaches the voltage on the second data line DLB slowly. In this case, the sense signal swing vs. coupling capacitance C can be effectively reduced BL-BL And thus bit line coupling noise can be reduced.
S550, in the recovery stage, the first semiconductor element is controlled to be turned on in an overload way by using the first control signal, so that the first bit line signal is raised to a third voltage; the second control signal is used for controlling the overload starting of the second semiconductor element so as to enable the second bit line signal to be reduced to a fourth voltage.
Referring to fig. 6 and 7D, in the restoration stage, the voltage of the control signal ISO rises to the erase voltage VPP as shown in fig. 6, that is, the voltages of the first control signal ISO1 and the second control signal ISO2 both rise to the erase voltage VPP. At this time, the first semiconductor switching element Q1 and the second semiconductor switching element Q2 are both in an overload on state (Over Drive), the voltage signal of the first data line DL may be completely transferred to the first bit line BL, and the voltage signal of the second data line DLB may be completely transferred to the second bit line BLB. Therefore, the voltage of the first bit line BL will rise to the same third voltage as the first data line DL, and the voltage of the second bit line BLB will also drop to the same fourth voltage as the second data item DLB, so that the sense amplifying process of the signal is completed. Referring to fig. 8, compared to a conventional sense amplifier circuit (i.e., a conventional SA circuit), the sense amplifier circuit (i.e., the SA circuit) provided by the present disclosure can obtain a better sensing effect in combination with the signal amplifying method provided by the present exemplary embodiment, and reduce the influence of bit line coupling noise.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (13)
1. A sense amplifier circuit, comprising:
one end of the sense amplifier is connected with the first data line, and the other end of the sense amplifier is connected with the second data line;
the first semiconductor switch element is connected with a first bit line at a first end, a first data line at a second end and a control end, wherein the control end receives a first control signal; the first semiconductor switching element changes the opening degree according to the first control signal and the signal transmitted by the first bit line;
a second semiconductor switching element, a first end of which is connected with a second bit line, a second end of which is connected with the second data line, and a control end of which receives a second control signal; the second semiconductor switching element changes the opening degree according to the second control signal and the signal transmitted by the second data line;
the process of amplifying the signals by the sense amplifier circuit comprises a pre-charging stage, a charge sharing stage, a blocking stage, a sensing stage and a restoration stage;
in the blocking stage, the first semiconductor switching element is controlled to be half-opened by the first control signal, and signal transmission between the first bit line and the first data line is blocked; controlling the second semiconductor switching element to be half-on by using the second control signal, and blocking signal transmission between the second bit line and the second data line;
in the sensing stage, a voltage difference value between the first data line and the second data line is controlled and amplified by using a first sensing signal and a second sensing signal, so that the first data line signal is increased to a third voltage, and the second data line signal is decreased to a fourth voltage; the second semiconductor switching element is turned on in response to a voltage drop of the second data line signal, so that the second bit line voltage gradually drops.
2. The sense amplifier circuit of claim 1 wherein the first control signal and the second control signal are the same signal.
3. The sense amplifier circuit of claim 1 wherein the first semiconductor switching element comprises a first transistor having a first pole connected to the first bit line and a second pole connected to the first data line, the gate receiving the first control signal.
4. A sense amplifier circuit according to claim 3 wherein the first transistor is an NMOS transistor.
5. The sense amplifier circuit of claim 1 wherein the second semiconductor switching element comprises a second transistor having a first pole connected to the second data line and a second pole connected to the second bit line, the gate receiving the second control signal.
6. The sense amplifier circuit of claim 5 wherein the second transistor is an NMOS transistor.
7. The sense amplifier circuit of claim 1, wherein the sense amplifier comprises:
the precharge circuit is respectively connected with the first data line and the second data line, and a control end of the precharge circuit receives an equalization control signal;
and the two induction signal input ends of the induction amplifying circuit respectively receive a first induction signal and a second induction signal.
8. The sense amplifier circuit of claim 7 wherein the precharge circuit comprises:
a third transistor having a first electrode connected to the first data line and a second electrode connected to the second data line, and a gate receiving the equalization control signal;
a first electrode of the fourth transistor is connected with the first data line, a second electrode of the fourth transistor receives a charging signal, and a grid electrode of the fourth transistor receives the balance control signal;
and a fifth transistor, a first pole of which is connected with the second data line, a second pole of which receives the charging signal, and a gate of which receives the equalization control signal.
9. The sense amplifier circuit of claim 8 wherein the third transistor, fourth transistor and fifth transistor are NMOS transistors.
10. The sense amplifier circuit of claim 7 wherein the sense amplifier circuit comprises:
a sixth transistor, a first pole of which is connected with the second data line, a second pole of which receives the first induction signal, and a grid of which is connected with the first data line;
a seventh transistor, a first pole of which is connected with the first data line, a second pole of which receives the first induction signal, and a grid of which is connected with the second data line;
an eighth transistor, a first pole of which is connected to the second data line, a second pole of which receives the second sensing signal, and a gate of which is connected to the first data line;
and a ninth transistor, wherein a first pole of the ninth transistor is connected with the first data line, a second pole of the ninth transistor receives the second sensing signal, and a grid electrode of the ninth transistor is connected with the second data line.
11. The sense amplifier circuit of claim 10 wherein the sixth transistor and the seventh transistor are PMOS transistors and the eighth transistor and the ninth transistor are NMOS transistors.
12. A memory comprising a plurality of sense amplifier circuits as claimed in any one of claims 1 to 11.
13. A signal amplification method applied to the sense amplifier circuit of any one of claims 1 to 11, the signal amplification method comprising:
in the precharge stage, the first semiconductor switching element and the second semiconductor switching element are turned on by the first control signal and the second control signal respectively, and the first data line, the first bit line, the second data line and the second bit line are charged to a first voltage by the equalizing control signal;
in the charge sharing stage, charge sharing is carried out through a coupling capacitor between the first data line and the adjacent sense amplifier circuit, and signals of the first data line and the first bit line rise to a second voltage;
in the blocking stage, a first control signal is used for controlling the half-on of the first semiconductor switching element, and signal transmission between the first bit line and the first data line is blocked; controlling the second semiconductor switching element to be half-on by using a second control signal, and blocking signal transmission between the second bit line and the second data line;
in the sensing stage, the voltage difference between the first data line and the second data line is controlled and amplified by using the first sensing signal and the second sensing signal, so that the first data line signal is increased to a third voltage, and the second data line signal is decreased to a fourth voltage; in response to the voltage drop of the second data line signal, the second semiconductor switching element is turned on to gradually drop the second bit line voltage;
in the recovery stage, the first semiconductor element is controlled to be overloaded and started by a first control signal, so that a first bit line signal is raised to a third voltage; and controlling the overload start of the second semiconductor element by using a second control signal to enable the second bit line signal to drop to a fourth voltage.
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| CN112863561A (en) | 2019-11-28 | 2021-05-28 | 长鑫存储技术有限公司 | Sense amplifier and control method thereof |
| CN111627474B (en) * | 2020-05-29 | 2022-06-10 | 西安紫光国芯半导体有限公司 | Transmission data bus driving circuit and method, and electronic device |
| CN114155896B (en) * | 2020-09-04 | 2024-03-29 | 长鑫存储技术有限公司 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
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