CN109165172A - Caching data processing method and relevant device - Google Patents
Caching data processing method and relevant device Download PDFInfo
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- CN109165172A CN109165172A CN201810977554.5A CN201810977554A CN109165172A CN 109165172 A CN109165172 A CN 109165172A CN 201810977554 A CN201810977554 A CN 201810977554A CN 109165172 A CN109165172 A CN 109165172A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
- G06F12/1018—Address translation using page tables, e.g. page table structures involving hashing techniques, e.g. inverted page tables
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the present application discloses a kind of caching data processing method, and the performance of last level cache is promoted by way of improving last level cache utilization rate, avoids the increase due to energy consumption caused by expanding last level cache space.The embodiment of the present application also provides corresponding relevant devices.The embodiment of the present application is applied to central processing unit CPU, which is equipped with last level cache space, is stored with tag array and data array in the last level cache space, this method comprises: receiving cache access request；When requesting to determine generation cache miss according to the cache access, the first data corresponding with cache access request are read；Judge to whether there is and consistent second data of first data in the data array；If there are second data in the data array, the first label corresponding with cache access request is obtained；First label is inserted into the tag array and first data are not stored in the data array.
Description
Technical field
This application involves computer software fields more particularly to a kind of caching data processing methods and relevant device.
Background technique
In chip multi-core processor system, due to central processing unit (the central processing relative on piece
Unit, CPU) processing speed, the delay of the outer main memory of chip is higher, in order to mitigate the performance gap of main memory and CPU outside piece, in chip
Portion is designed with spatial cache, stores those instruction and datas that may be accessed frequently, to reduce the access to main memory outside chip.
On piece spatial cache is divided into multiple levels with the distance away from CPU core.Wherein, the caching farthest apart from CPU core is known as
Last level cache (last level cache, LLC), the capacity of last level cache is larger, is shared by all CPU cores.In order to be promoted
The performance of last level cache can expand the size that last level cache is taken up space.
But expand the size in last level cache space, it not only will increase the area of chip shared by spatial cache, but also can lead
Cause the increase of CPU energy consumption.
Summary of the invention
The embodiment of the present application provides a kind of caching data processing method, by way of improving last level cache utilization rate come
The performance for promoting last level cache avoids the increase due to energy consumption caused by expanding last level cache space.The embodiment of the present application
Additionally provide corresponding relevant device.
In a first aspect, the embodiment of the present application provides a kind of caching data processing method, it is applied to central processing unit
CPU, the CPU are equipped with last level cache space, are stored with tag array and data array, this method packet in the last level cache space
It includes:
Receive cache access request；
When requesting to determine generation cache miss according to the cache access, reading and cache access request corresponding first
Data；
Judge to whether there is and consistent second data of first data in the data array；
If there are second data in the data array, the first label corresponding with cache access request is obtained；
First label is inserted into the tag array and first data are not stored in the data array.
Second aspect, the embodiment of the present application provide a kind of central processing unit CPU, which is equipped with last level cache space,
It is stored with tag array and data array in the last level cache space, which includes:
Receiving unit, for receiving cache access request；
Reading unit, for reading and the cache access when requesting to determine generation cache miss according to the cache access
Request corresponding first data；
Judging unit whether there is and consistent second data of first data in the data array for judging；
Acquiring unit, for when there are when second data, then obtain and cache access request pair in the data array
The first label answered；
It is inserted into unit, for when there are when second data, then first label being inserted into the mark in the data array
It signs in array.
The third aspect, the embodiment of the present application provide a kind of terminal, and the terminal includes: processor and memory, described to deposit
The instruction of data cached processing described in above-mentioned first aspect is stored in reservoir；
The processor is used to execute the instruction of the data cached processing stored in memory, executes such as above-mentioned first aspect
The step of method of described data cached processing.
Fourth aspect, the embodiment of the present application provide a kind of computer readable storage medium, the computer-readable storage medium
The instruction of data cached processing is stored in matter, when run on a computer, so that computer executes above-mentioned first aspect
The step of method of described data cached processing.
5th aspect, this application provides a kind of chip systems, which includes processor, for supporting network to set
It is standby to realize function involved in above-mentioned aspect, for example, for example sending or handling data and/or letter involved in the above method
Breath.In a kind of possible design, the chip system further includes memory, and the memory must for saving the network equipment
The program instruction and data wanted.The chip system, can be made of chip, also may include chip and other discrete devices.
As can be seen from the above technical solutions, the embodiment of the present application has the advantage that
CPU is determining that reading is requested with the cache access when cache miss occurs according to the cache access request received
Corresponding first data, if in last level cache exist with consistent second data of the first data, will only be requested with cache access
Corresponding first label is inserted into tag array, without first data are stored in data array, to reduce last level cache
The probability of middle storage identical data, to realize the promotion of last level cache utilization rate, and then improves the performance of last level cache, avoids
Due to expanding the increase of last level cache space bring energy consumption.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of processor chips provided by the embodiments of the present application；
Fig. 2 is the structural schematic diagram in last level cache space provided by the embodiments of the present application；
Fig. 3 is a kind of flow diagram of spatial cache data processing method provided by the embodiments of the present application；
Fig. 4 is another flow diagram of spatial cache data processing method provided by the embodiments of the present application；
Fig. 5 is a kind of structural schematic diagram of central processing unit provided by the embodiments of the present application；
Fig. 6 is a kind of structural schematic diagram of terminal provided by the embodiments of the present application.
Specific embodiment
The embodiment of the present application provides a kind of spatial cache data processing method, by improving last level cache space utilization rate
Mode promote the performance in last level cache space, avoid the increasing due to energy consumption caused by expanding last level cache space space
Add.The embodiment of the present application also provides corresponding relevant devices.
The embodiment of the present application can be applied to terminal, and referring to Fig. 1, operation has CPU10 in the processor chips of the terminal,
Wherein, the CPU10 run in processor chips can be multi-core processor, or single core processor.The processing of the terminal
It also is provided with memory space outside device chip, the memory space outside the processor chips becomes the outer main memory of piece.
It is additionally provided with spatial cache 20 in the embodiment of the present application, in processor chips, is frequently accessed for storing by CPU core
Instruction and data.Wherein, the spatial cache space on chip is divided into multiple levels, may include first with the distance away from CPU core
Grade spatial cache, second level spatial cache, third level spatial cache etc..Wherein, afterbody spatial cache namely last level cache
Space 200, distance CPU is farthest and capacity is maximum, is shared in multi-core processor by all CPU cores.
In the embodiment of the present application, above-mentioned terminal can be computer, tablet computer, PDA (Personal Digital
Assistant, personal digital assistant), mobile phone, vehicle-mounted computer, TV or other equipment with communication module etc., do not limit herein
It is fixed.
It include tag array 2001, data array 2002 and Hash in last level cache space 200 in the embodiment of the present application
Table 2003.
In the embodiment of the present application, multiple tag blocks are stored in tag array 2001, each tag block includes a mark
Label, outside piece in main memory, each label is used to one data block of unique identification, the tag array being stored in last level cache space
In include the outer main memory of label and piece in the value of label can be identical.In last level cache space, tag block and data block
Between corresponding relationship can be one-to-one, or many-one is also stored with corresponding data in each tag block
The storage address information of block.
In the embodiment of the present application, includes multiple data blocks in data array 2002, include above-mentioned and mark in each data block
Signing block, there are the data of mapping relations.
In the embodiment of the present application, a plurality of record is stored in Hash table 2003, record is one-to-one relationship with data block,
For recording the storage address of the cryptographic Hash and data block that generate according to the data in data block.
The caching data processing method in the application is described in detail below, refering to Fig. 3, the embodiment of the present application is provided
A kind of caching data processing method embodiment may include:
301, CPU obtains cache access request.
In the present embodiment, CPU in the process of running, when need use the data stored in processor chip exterior main memory
When, cache access request can be generated namely the CPU gets cache access request.
In the present embodiment, data corresponding with cache access request are included at least in cache access request in processor
Storage address in chip exterior main memory.
302, it when CPU requests to determine according to the cache access, and cache miss occurs, reads and cache access request pair
The first data answered.
In the present embodiment, CPU can be requested according to cache access in include the storage address search and be used for into main memory
The first label for identifying the data and the correspondence group where first label, the tag array of traversal last level cache space storage
In include the correspondence group, to judge whether to have existed in correspondence group that the tag array includes and the cache access is requested
Corresponding first label, if it exists the first label corresponding with cache access request, it is determined that cache hit occurs；If not depositing
In label corresponding with cache access request, it is determined that cache miss occurs.
After determining generation cache miss, CPU can be read from the main memory outside processor chips according to first label
Take first data.
303, CPU judge in the data array with the presence or absence of with consistent second data of first data, if the data matrix
There are second data in column, then 304 are entered step；If second data are not present in the data array, enter step
306。
In the present embodiment, due to being stored with data array in last level cache space, CPU, can after getting the first data
To judge to whether there is in data that the data array includes and consistent second data of first data.
304, CPU obtains the first label corresponding with cache access request.
In the present embodiment, since CPU has determined corresponding the according to cache access request in step 302
One label, available first label of CPU.
305, first label is inserted into the tag array and first data is not stored in the data array by CPU.
In the present embodiment, due to had existed in data array with consistent second data of the first data, CPU is no longer
First data are stored in the data array, the available storage location of second data in last level cache space of CPU will
First label is put into the tag block of tag array, and the call number of the tag block where first label is arranged, and makes this
Call number is directed toward the storage location of second data.
In the present embodiment, when first label is put into the tag block of the tag array by CPU, if the tag array
There is idle tag block in the correspondence group for including, one is randomly selected from the tag block of the free time；If in the tag array
All tag blocks are occupied, choose least recently used tag block, it should be understood that choose mode to tag block herein
Citing only for convenience of understand, specifically herein without limitation.
306, CPU executes other programs.
In the present embodiment, CPU is determining that reading is slow with this when cache miss occurs according to the cache access request received
Deposit corresponding first data of access request, if exist in last level cache with consistent second data of the first data, only will with it is slow
It deposits corresponding first label of access request to be inserted into tag array, without first data are stored in data array, to drop
The probability of identical data is stored in low last level cache, to realize the promotion of last level cache utilization rate, and then improves last level cache
Performance avoids the increase due to expanding last level cache space bring energy consumption.
Based on 3 described embodiment of earlier figures, referring particularly to Fig. 4, another caching number provided by the embodiments of the present application
May include: according to processing method embodiment
401, CPU obtains cache access request.
402, CPU is read and cache access request pair when requesting to determine generation cache miss according to the cache access
The first data answered.
In the present embodiment, step 401 and 402 similar with step 301 in aforementioned embodiment illustrated in fig. 3 and 302, herein not
It repeats again.
403, CPU generates the first cryptographic Hash corresponding with first data, and judges to whether there is and this in the Hash table
Consistent second cryptographic Hash of first cryptographic Hash, and if it exists, then enter step 404；If it does not exist, then 414 are entered step.
In the present embodiment, due to being also stored with Hash table in last level cache space, the Hash table include a plurality of record, every
Record is corresponded with a database in data array, call number and cryptographic Hash comprising the data block, wherein every number
It is generated according to the cryptographic Hash for including in block all in accordance with the data for including in the data block.Therefore, CPU, can after obtaining the first data
To generate corresponding with first data the first cryptographic Hash, traverse the Hash table with determine whether there is in the Hash table with this
Consistent second cryptographic Hash of one cryptographic Hash.
In the present embodiment, the call number for the data block for including in Hash table is directed toward the storage location of the data block.
404, CPU obtains the first call number for including in the target record where second cryptographic Hash.
In the present embodiment, when there is the second cryptographic Hash consistent with first cryptographic Hash in the Hash table, CPU can be with
Target record where reading second cryptographic Hash in a plurality of record that the Hash table includes, due to every in a plurality of record
Item record includes the call number of a data block, and CPU can read the first call number for including in the target record.
405, CPU reads third data from the storage location that first call number indicates, and judges the point data and be somebody's turn to do
Whether the first data are consistent, if unanimously, entering step 406；If inconsistent, 414 are entered step.
In the present embodiment, CPU reads third data from the storage location that first call number indicates, so judge this
Whether three data and first data are completely the same.Under the third data and the first data unanimous circumstances, determining should
Exist and consistent second data of the first data in data array.
In the present embodiment, when whether there is data consistent with the first data in judging data array, Hash is first judged
With the presence or absence of the second cryptographic Hash with the first cryptographic Hash in table, in the presence of obtain again and the consistent third number of second cryptographic Hash
According to and then judging whether third data are completely the same with the first data, so as to avoid will be in the first data and data array
Data compare one by one, reduce the workload of CPU.
406, CPU obtains the first label corresponding with cache access request.
407, first label is inserted into the tag array and first data is not stored in the data array by CPU.
In the present embodiment, step 406 and 407 similar with step 304 in aforementioned embodiment illustrated in fig. 3 and 305, herein not
It repeats again.
408, the field value of the counter field of the second data block is added one by CPU.
In the present embodiment, each data block also includes counter field, since the counter field is for identifying and the number
According to block have mapping relations tag block number, CPU it is available store second data the second data block, by this second
The field value of the counter field of data block adds one.The value of counter field can be the natural numbers such as 1,2,3 or 4, the counting
The value of device field is the citation times of the data in the second data block.Increase counter word in the application within the data block
Section, by counter field be can determine whether the data block is used frequent degree, thus when new data are written, avoid by
The data frequently used are deleted.
409, CPU judges the 4th data that whether there is not yet duplicate checking in the data array, if it exists the 4th data, then
Enter step 410；4th data if it does not exist then enter step 416.
In the present embodiment, each data block in data array also includes marker bit, which is used to indicate the data
Whether duplicate checking, CPU can read the marker bit for including in each data block to the data stored in block, to judge the data
With the presence or absence of the 4th data of not yet duplicate checking in array.As an example, being indicated in the data block when value of such as marker bit is 0
Data not yet duplicate checking；When the value of marker bit is 1, indicate that duplicate checking, specific marker bit take the data in the data block
Value, herein without limitation.
In the present embodiment, due to the only ability trigger data duplicate checking when sending cache miss, then by writing hit write-in end
Data the case where there may be not yet duplicate checkings of grade spatial cache, setting flag position is for identifying the data in each data block
Data in block whether duplicate checking, so that it is guaranteed that the data stored in last level cache space were performed duplicate checking operation, into
The utilization rate in one step raising last level cache space.
410, CPU judge in the data array with the presence or absence of with consistent 5th data of the 4th data, if it exists this
Five data, then enter step 411；5th data if it does not exist then enter step 416.
In the present embodiment, CPU determine to the 4th data after, can according to the corresponding relationship of data matrix and Hash table,
The cryptographic Hash that generates according to the 4th data is obtained, judges to whether there is in Hash table and the cryptographic Hash of the 4th data consistent the
Three cryptographic Hash, and if it exists, the record where third cryptographic Hash is read, to determine in data block corresponding with the third cryptographic Hash
Data, and then judge that whether corresponding with the third cryptographic Hash the 4th data data are consistent, if unanimously, being deposited in the data array
With consistent 5th data of the 4th data.
411, CPU obtains that there are the first tag blocks of mapping relations with the 4th data from the tag array.
In the present embodiment, since a data block can be every in data array with multiple tag blocks there are mapping relations
A data block can also include the first pointer field, and there are the multiple of mapping relations with the data block for first pointer field direction
The storage location of first tag block in tag block；It include the second pointer field in each tag block, which can
With other tag blocks being directed toward in multiple tag block.Therefore, when in data array exist and the 4th data the consistent 5th
When data, the available data block comprising the 4th data of CPU, so that it is determined that existing with the data block comprising the 4th data
Storage location of first tag block of mapping relations in the tag array, and then obtained and the 4th number from the tag array
According to there are the first tag blocks of mapping relations.
In the present embodiment, which can be one, or it is multiple, specifically herein without limitation.
412, the second call number that first tag block includes is revised as the storage location of the 5th data by CPU.
In the present embodiment, since each tag block in tag array corresponds to a data block, then each tag block is equal
Comprising call number, the call number for including in each tag block is directed to the storage location of the data corresponding with the tag block.
For CPU after obtaining first tag block, the second call number that can include by first tag block is revised as the 5th data
Storage location.
413, CPU sets zero for the field value for the counter field that the first data block includes.
It include the 4th data in first data block in the present embodiment, due to existing in data array and the 4th number
According to consistent 5th data, CPU can set zero for the field value for the counter field that first data block includes, and delete
Record corresponding with the 4th data in Hash table, to delete the 4th data.In the application, by by the field of counter field
The mode that value is set as zero deletes the 4th data, easy to operate, and avoids the work of the 4th data of erasing, reduces CPU's
Energy consumption.
414, CPU obtains the smallest third data block of field value of the counter field from the data array.
In the present embodiment, when the second data consistent with first data are not present in the data array,
415, first data are put into the third data block by CPU.
In the present embodiment, the first label is inserted into the tag array and first data are put into the third data
In block, and the call number of the tag block where first label is set to the storage location of the third data block, by the third
The field value of first pointer field of data block is set as storage position of the tag block where first label in tag array
It sets.
It should be appreciated that step 409 can execute the step for optional step if not executing step 409 to 413 to 413
Step 416 is directly executed after 408, or step 416 is directly executed after executing the step 415.
If execute step 409 to 413, the execution sequence of step 402 to 408 and step 409 to 413 without limitation, can
To first carry out step 402 to 408, then step 409 is executed to 413, can also first carry out step 409 to 413, then execute step
402 to 408；Step 414 and 415 with the execution of step 409 to 413 sequence also without limitation, can first carry out step 402 to
408, then step 414 and 415 are executed, step 414 and 415 can also be first carried out, then execute step 402 to 408.
416, CPU executes other programs.
Fig. 5 is a kind of structural schematic diagram of CPU provided by the embodiments of the present application, and CPU500 is equipped with last level cache space, should
Tag array and data array are stored in last level cache space, CPU500 includes:
Module 501 is obtained, for obtaining cache access request；
Read module 502, for reading and being visited with the caching when requesting to determine generation cache miss according to the cache access
Ask request corresponding first data；
Judgment module 503 whether there is and consistent second data of first data in the data array for judging；
Module 501 is obtained, is also used to when there are when second data, then acquisition is asked with the cache access in the data array
Seek corresponding first label；
It is inserted into module 504, for when there are when second data, then first label being inserted into this in the data array
The data array is stored in tag array and not by first data.
In a kind of possible implementation, which includes multiple data blocks；It is also stored in the last level cache space
There is Hash table, it includes the call number and cryptographic Hash of the data block in every record which, which includes a plurality of record,
The cryptographic Hash is generated according to the data for including in the data block；
Judgment module 503 is specifically used for:
Generate the first cryptographic Hash corresponding with first data；If existing in the Hash table consistent with first cryptographic Hash
Second cryptographic Hash then obtains the first call number for including in the target record where second cryptographic Hash；From first call number
Third data are read at the storage location of instruction；Under the third data and the first data unanimous circumstances, the data are determined
There are second data in array.
In a kind of possible implementation, which also includes marker bit；The tag array includes multiple labels
Block, each tag block include call number, and the call number for including in each tag block is directed to be somebody's turn to do corresponding with the tag block
The storage location of data,
Judgment module 503 is also used to:
According to the marker bit, judge in the data array with the presence or absence of the 4th data of not yet duplicate checking；If it exists the 4th
Data judge to whether there is and consistent 5th data of the 4th data in the data array；
Module 501 is obtained to be also used to:
5th data if it exists, there are the first labels of mapping relations with the 4th data for acquisition from the tag array
Block；
CPU500 further include:
Modified module 505, the second call number for including by first tag block are revised as the storage of the 5th data
Position；
Removing module 506, for deleting the 4th data.
In a kind of possible implementation, which also includes counter field, and the counter field is for marking
Know the number for the tag block that there are mapping relations with the data block；
Removing module 506 is specifically used for: zero is set by the field value for the counter field that the first data block includes,
In, it include the 4th data in first data block.
In a kind of possible implementation, modified module 505 is also used to: if there are second data in the data array,
The field value of the counter field of the second data block is then added one, wherein include second data in second data block.
It in a kind of possible implementation, obtains module 501 and is also used to: if there is no second numbers in the data array
According to obtaining the smallest third data block of field value of the counter field from the data array；
CPU500 further include:
Memory module 507, for first data to be put into the third data block.
In the present embodiment, CPU500 institute in the process and earlier figures 3 and embodiment illustrated in fig. 4 that each module executes in CPU500
The process of execution is similar, and details are not described herein again.
In the present embodiment, read module 502 is read when determining generation cache miss according to the cache access request received
Take the first data corresponding with cache access request, if in last level cache exist with consistent second data of the first data,
The first label corresponding with cache access request is only inserted into tag array by insertion module 504, without by first data
It is stored in data array, so that the probability that identical data is stored in last level cache is reduced, to realize the promotion of last level cache utilization rate,
And then the performance of last level cache is improved, avoid the increase due to expanding last level cache space bring energy consumption.
A kind of terminal is also provided in the embodiment of the present application, referring to Fig. 6, which can produce because configuration or performance are different
Raw bigger difference, may include one or more processors 601 and memory 602 (such as one or more
Mass memory unit).Wherein, memory 602 can be of short duration storage or persistent storage.The program being stored on memory 602
It may include one or more modules (diagram does not mark), each module may include to a series of in processor 601
Instruction operation.Further, processor 601 can be set to communicate with memory 602, execute memory in terminal 600
Series of instructions operation in 602.
Terminal 600 can also include one or more input/output interfaces 603, one or more power supplys 604,
One or more wired or wireless network interfaces 605.
In some embodiments of the invention, processor 601, memory 602, input/output interface 603,604 and of power supply
Wired or wireless network interface 605 can be connected by bus or other means, in Fig. 6 for being connected by bus.
The instruction of data cached processing described in earlier figures 3 and embodiment illustrated in fig. 4 is stored in the memory；
The processor is used to execute the instruction of the data cached processing stored in memory, executes such as earlier figures 3 and Fig. 4
Described in illustrated embodiment the step of caching data processing method.
A kind of computer readable storage medium is also provided in the embodiment of the present application, is stored in the computer readable storage medium
There is the instruction of data cached processing, when run on a computer, so that computer is executed as shown in earlier figures 3 and Fig. 4 in fact
The step of applying caching data processing method described in example.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
In several embodiments provided herein, it should be understood that disclosed system, device and method can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit
It divides, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components
It can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, it is shown or
The mutual coupling, direct-coupling or communication connection discussed can be through some interfaces, the indirect coupling of device or unit
It closes or communicates to connect, can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, each functional unit in each embodiment of the application can integrate in one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated list
Member both can take the form of hardware realization, can also realize in the form of software functional units.
If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product
When, it can store in a computer readable storage medium.Based on this understanding, the technical solution of the application is substantially
The all or part of the part that contributes to existing technology or the technical solution can be in the form of software products in other words
It embodies, which is stored in a storage medium, including some instructions are used so that a computer
Equipment (can be personal computer, server or the network equipment etc.) executes the complete of each embodiment the method for the application
Portion or part steps.And storage medium above-mentioned includes: USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only
Memory), random access memory (RAM, Random Access Memory), magnetic or disk etc. are various can store journey
The medium of sequence code.
The above, above embodiments are only to illustrate the technical solution of the application, rather than its limitations；Although referring to before
Embodiment is stated the application is described in detail, those skilled in the art should understand that: it still can be to preceding
Technical solution documented by each embodiment is stated to modify or equivalent replacement of some of the technical features；And these
It modifies or replaces, the spirit and scope of each embodiment technical solution of the application that it does not separate the essence of the corresponding technical solution.
Claims (10)
1. a kind of caching data processing method, which is characterized in that be applied to central processing unit CPU, the processing where the CPU
Device chip is equipped with last level cache space, is stored with tag array and data array, the method in the last level cache space
Include:
Obtain cache access request；
When requesting to determine generation cache miss according to the cache access, reading and cache access request corresponding first
Data；
Judge to whether there is and consistent second data of first data in the data array；
If there are second data in the data array, the first label corresponding with cache access request is obtained；
First label is inserted into the tag array and first data are not stored in the data array.
2. the method according to claim 1, wherein the data array includes multiple data blocks；The final stage
Hash table is also stored in spatial cache, it includes described in one in every record that the Hash table, which includes a plurality of record,
The call number and cryptographic Hash of data block, the cryptographic Hash are generated according to the data for including in the data block；
It whether there is and consistent second data of first data in the judgement data array, comprising:
Generate the first cryptographic Hash corresponding with first data；
If in the Hash table exist with consistent second cryptographic Hash of first cryptographic Hash, obtain the second cryptographic Hash institute
Target record in include the first call number；
Third data are read from the storage location that first call number indicates；
Under the third data and the first data unanimous circumstances, determine that there are second numbers in the data array
According to.
3. according to the method described in claim 2, it is characterized in that, each data block also includes marker bit；The label
Array includes multiple tag blocks, and each tag block includes call number, and the call number for including in each tag block is directed to
The storage location of the data corresponding with the tag block, the method also includes:
According to the marker bit, judge in the data array with the presence or absence of the 4th data of not yet duplicate checking；
4th data if it exists judge to count in the data array with the presence or absence of with the 4th data the consistent 5th
According to；
5th data if it exists obtain the first mark with the 4th data there are mapping relations from the tag array
Sign block；
The second call number that first tag block includes is revised as to the storage location of the 5th data；
Delete the 4th data.
4. described according to the method described in claim 3, it is characterized in that, each data block also includes counter field
Counter field is used to identify the number for the tag block for having mapping relations with the data block；
It is described to delete the 4th data and include:
Zero is set by the field value for the counter field that the first data block includes, wherein includes institute in first data block
State the 4th data.
5. according to the method described in claim 4, it is characterized in that, the method also includes:
If the field value of the counter field of the second data block is added one there are second data in the data array,
It wherein, include second data in second data block.
6. according to the method described in claim 4, it is characterized in that, the method also includes:
If second data are not present in the data array, the word of the counter field is obtained from the data array
The smallest third data block of segment value；
First data are put into the third data block.
7. according to method described in claim 3 to 6 any claim, which is characterized in that each data block also includes
First pointer field, there are first marks in multiple tag blocks of mapping relations with the data block for the first pointer field direction
Sign the storage location of block；
The tag array further includes the second tag block and third tag block, also includes the second pointer word in second tag block
Section, second pointer field are directed toward the storage location of the third tag block, second tag block and the third label
The call number for including in block is consistent.
8. a kind of central processing unit CPU, which is characterized in that the CPU is equipped with last level cache space, the last level cache space
In be stored with tag array and data array, the CPU includes:
Module is obtained, for obtaining cache access request；
Read module, for reading and the cache access when requesting to determine generation cache miss according to the cache access
Request corresponding first data；
Judgment module whether there is and consistent second data of first data in the data array for judging；
Module is obtained, for when there are when second data, then obtain and cache access request in the data array
Corresponding first label；
It is inserted into module, for when there are when second data, then first label being inserted into institute in the data array
It states and is stored in the data array in tag array and not by first data.
9. a kind of terminal, which is characterized in that the terminal includes: processor and memory, stores and has the right in the memory
It is required that the instruction of any data cached processing of 1-7；
The processor is used to execute the instruction of the data cached processing stored in memory, executes as claim 1-7 is any
The step of method of the data cached processing.
10. a kind of computer readable storage medium, which is characterized in that be stored with caching number in the computer readable storage medium
According to the instruction of processing, when run on a computer, so that computer executes any side the claims 1-7
Method.
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