CN109165105A - A kind of host and physical machine system - Google Patents
A kind of host and physical machine system Download PDFInfo
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- CN109165105A CN109165105A CN201810942926.0A CN201810942926A CN109165105A CN 109165105 A CN109165105 A CN 109165105A CN 201810942926 A CN201810942926 A CN 201810942926A CN 109165105 A CN109165105 A CN 109165105A
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- Prior art keywords
- order
- nvme
- host
- queue
- control command
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/546—Message passing systems or structures, e.g. queues
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/544—Buffers; Shared memory; Pipes
Abstract
The embodiment of the present application discloses a kind of host and physical machine system, the performance for solving the problems, such as the existing Host by software-driven are lower.The application Host may include: that queue 40 is completed in data cache module 10, order generation processing module 20, order transmit queue 30 and order；Wherein, NVMe order is input to order transmit queue 30, and complete to fetch response message corresponding with NVMe order in queue 40 from order for generating Nonvolatile memory host controller interface specification NVMe order by order production processing module 20；Data to be transmitted for caching to data to be transmitted, and are sent to controller Controller or are sent to client layer by data cache module 10；Order transmit queue 30, for NVMe order to be sent to Controller；Queue 40 is completed in order, for receiving response message that Controller is returned, corresponding with NVMe order.
Description
Technical field
This application involves chip design field more particularly to a kind of host and physical machine systems.
Background technique
Nonvolatile memory host controller interface specification (non-volatile memory express, NVMe) is one
The agreement that kind stores equipment exclusively for flash-type and designs is broadly divided into two parts in NVMe agreement: host (Host) and control
Device (Controller) processed.Wherein, controller be typically found in NVMe storage equipment (such as support NVMe agreement solid-state
Hard disk) it is internal, as the master control of equipment, the main unloading for completing NVMe order and the interaction with the storage unit in equipment；
Host is the key component of NVMe protocol realization, it receives the request instruction that operating system of user issues, internal generation standard
NVMe order, then NVMe order is sent to Controller.
The realization of Host is all to be put Host in an operating system by way of software-driven at present.But this reality
Existing mode is although fairly simple, but is generally difficult to obtain very high performance, especially stores system in present catenetization
In system.
Summary of the invention
The embodiment of the present application provides a kind of host and physical machine system, for solving the existing Host by software-driven
The lower problem of performance.
In order to solve the above technical problems, the embodiment of the present application the following technical schemes are provided:
On the one hand the application provides a kind of host, the Host is realized using hardware logic, comprising:
Data cache module 10, order generate processing module 20, order transmit queue 30 and order and complete queue 40；
Wherein, the order produces processing module 20, for generating Nonvolatile memory host controller interface specification
The NVMe order is input to the order transmit queue 30, and completes to take in queue 40 from the order by NVMe order
Return response message corresponding with the NVMe order；
The data cache module 10 for caching to data to be transmitted, and data to be transmitted is sent to
Controller Controller is sent to client layer；
The order transmit queue 30, for the NVMe order to be sent to the Controller；
Queue 40 is completed in the order, that the Controller is returned, corresponding with the NVMe order for receiving
Response message.
Optionally, the Host further include:
User's request processing module 50 and address conversion module 60；
User's request processing module 50 for receiving read/write I/O request from client layer, and therefrom extracts I/O order
Relevant information, the I/O order relevant information are information needed for generating I/O order；
The address conversion module 60, for receiving the related letter of I/O order that user's request processing module 50 inputs
Breath, row address of going forward side by side conversion.
Optionally, it includes that I/O order generates processing module 21 that the order, which generates processing module 20, and the order sends team
Column include I/O order transmit queue 31, and it includes that queue 41 is completed in order that queue 40 is completed in the order；
Wherein, the I/O order generates processing module 21, the process ground inputted for receiving the address conversion module 60
The I/O order relevant information of location conversion generates NVMe I/O order according to the I/O order relevant information received, will be described
NVMe I/O order is input to I/O order transmit queue 31, and completes to fetch and the NVMe in queue 41 from I/O order
The corresponding response message of I/O order；
The I/O order transmit queue 31, for the NVMe I/O order to be sent to the Controller；
Queue 41 is completed in the I/O order, for receiving the Controller the is returned and NVMe I/O order
Corresponding response message.
Optionally, the I/O order relevant information includes size of data and data address.
Optionally, the Host is deployed between operating system of user and NVMe storage equipment.
Optionally, the Host is applied in networking storage system.
Optionally, the equipment further include:
Control command generates processing module 22, control command transmit queue 32 and control command and completes queue 42；
Wherein, control command generates processing module 22 for generating NVMe control command, and NVMe control command is input to
Control command transmit queue 32, and complete to fetch response message in queue 42 from control command；
Control command transmit queue 32, for sending the Controller for NVMe control command；
Control command completes queue 42, that the Controller is returned, corresponding with NVMe control command for receiving
Response message.
Optionally, the control command includes at least one of management Admin order and tissue Fabric order.
Optionally, the data cache module 10 is also used to:
Data to be transmitted are sent under the control that the control command generates processing module 22 described
Controller。
The application second aspect provides a kind of physical machine system, including host and NVMe store equipment, the NVMe storage
Equipment includes Controller, wherein the host is described in any one possible implementation in above-mentioned first aspect
Equipment.
The application uses the host of hardware logic designing user operating system side, higher performance is help to obtain, big
It is conducive in the acceleration system of type networking integrated.
Detailed description of the invention
Fig. 1 is a kind of possible structural schematic diagram of Host of the present invention；
Fig. 2 is the alternatively possible structural schematic diagram of Host of the present invention；
Fig. 3 is the alternatively possible structural schematic diagram of Host of the present invention；
Fig. 4 is a kind of possible structural schematic diagram of physical machine system of the present invention.
Specific embodiment
The embodiment of the present application provides a kind of host and physical machine system, for improving the property of Host and physical machine system
Energy.
With reference to the accompanying drawing, embodiments herein is described.
The description and claims of this application and term " first " in above-mentioned attached drawing, " second " etc. are for distinguishing
Similar object, without being used to describe a particular order or precedence order.It should be understood that the term used in this way is in appropriate feelings
It can be interchanged under condition, this is only to describe the used differentiation in description to the object of same alike result in embodiments herein
Mode.In addition, term " includes " and " having " and their any deformation, it is intended that cover it is non-exclusive include, so as to
A series of process, method, system, product or equipment comprising units are not necessarily limited to those units, but may include unclear
Other units that ground is listed or intrinsic for these process, methods, product or equipment.
The realization of Host is all to be put Host in an operating system by way of software-driven at present.But this reality
Existing mode is although fairly simple, but is generally difficult to obtain very high performance, especially stores system in present catenetization
In system.The present invention is in order to solve the above technical problems, propose the hardware implementations of Host a kind of.Host is real using hardware logic
It is existing, it can be deployed between operating system of user and storage equipment.
In the networking storage agreement of NVMe, NVMe order mainly includes control command and read/write (input/
Output, I/O) order, wherein I/O order is mainly used for the access of disk, completes data in the read-write of Controller.Control
System order mainly includes management (Admin) order, and Admin order is mainly used for the control and management of equipment, such as I/O queue, IOQ
Creation, deletion etc..Optionally, control command can also include that tissue (Fabric) is ordered, and Host is mainly completed in Fabric order
With the connection of Controller.
Processing of the modular hardware logic design method realization to NVMe order can be used in Host, referring to Fig. 1, this
Inventing Host 100 may include:
Data buffer storage (data buffer) module 10, order generate processing module 20, order transmit queue 30 and order
Complete queue 40；
Wherein, order production processing module 20, for generating Nonvolatile memory host controller interface specification NVMe life
It enables, NVMe order is input to order transmit queue, and complete to fetch sound corresponding with NVMe order in queue from order
Answer message；
Data to be transmitted for caching to data to be transmitted, and are sent to control by data cache module 10
Device Controller is sent to client layer；
Order transmit queue 30, for NVMe order to be sent to Controller；
Queue 40 is completed in order, for receiving response message that Controller is returned, corresponding with NVMe order.
The application uses the Host of hardware logic designing user operating system side, higher performance is help to obtain, big
It is conducive in the acceleration system of type networking integrated.
Host realizes the processing to I/O order using modular hardware logic design method, is based on the corresponding implementation of Fig. 1
Example, in some embodiments of the invention, referring to Fig. 2, Host of the present invention 200 may include:
Data cache module 10, user's request processing (User Req) module 50, address conversion module 60, I/O order life
Queue (CQ) 41 is completed at processing (I/O CMD) module 21, I/O order transmit queue (SQ) 31 and I/O order.
Wherein, user's request processing module 50 is used in reading and writing data, receives I/O request from client layer, and therefrom mention
Take I/O order relevant information, I/O order relevant information is to generate the required information of I/O order, such as size of data and data
The information such as location.
Address conversion module 60 for receiving the I/O order relevant information of the input of user's request processing module 50, and carries out
Address conversion.Address conversion module 60 establishes user and reads and writes storage device address and logical block addresses (logical block
Address, LBA) conversion, NVMe storage equipment in, storage unit be as unit of LBA, therefore from client layer receive
To I/O request in data address to be converted to the address LBA by address conversion module 60, NVMe I/O life could be used for
It enables.
I/O order generates processing module 21, the main generation for completing I/O order, processing, for receiving address conversion module
The I/O order relevant information by address conversion of 60 inputs, generates NVMe I/O order, which generates the NVMe of standard
NVMe I/O order is input to I/O order transmit queue 31 by I/O order；And from I/O order complete queue 41 in fetch with
The corresponding response message of NVMe I/O order, processing returns to response message.
Data cache module 10 for caching to data to be transmitted, and data to be transmitted is sent to
Controller is sent to client layer.
I/O order transmit queue 31, for I/O order to be sent to Controller.
Queue 41 is completed in I/O order, for receiving response that Controller is returned, corresponding with NVMe I/O order
Message.
It should be noted that queue 41 is completed in I/O order transmit queue 31 and I/O order, being substantially two pieces has one
The memory space of depthkeeping degree, for caching NVMe I/O order and response message.Host provided by the invention can be deployed in
Between operating system of user and NVMe storage equipment.
In order to make it easy to understand, the corresponding Host of Fig. 2 is provided below to a kind of possible process flow of I/O order:
201, user's request processing module 50 receives I/O request from client layer, and therefrom extracts I/O order relevant information；
User's request processing module 50 can receive I/O request from client layer, and according to preset rules from the I/O received
I/O order relevant information is extracted in request, I/O order relevant information is information needed for generating I/O order, such as size of data
Believe with data address etc., it later can be by I/O order relevant information input address conversion module 60.
202, address conversion module 60 receives the I/O order relevant information that user's request processing module 50 inputs, and carries out
Address conversion；
Address conversion module 60 can receive the I/O order relevant information of the input of user's request processing module 50, wherein
Including data address.Since NVMe storage is as unit of LBA, from the data in the I/O request that client layer receives
Location will be converted to the address LBA by address conversion module 60, could be used for NVMe I/O order.
203, I/O order generates processing module 21 and receives the I/O life by address conversion that address conversion module 60 inputs
Relevant information is enabled, NVMe I/O order is generated；
I/O order, which generates processing module 21, can receive the I/O life by address conversion of the input of address conversion module 60
Relevant information is enabled, including data address and size of data, can be generated later according to the I/O order relevant information received
NVMe I/O order.
204, data cache module 10 receives data to be transmitted from client layer；
Assuming that the I/O request received in the present embodiment is write request, then data cache module 10 can be from client layer
Data to be transmitted are received, and data to be transmitted are cached.
205, I/O order generates processing module 21 and NVMe I/O order is input to I/O order transmit queue 31, and controls
Data to be transmitted are sent to Controller by data cache module 10；
I/O order, which generates processing module 21, can be input to NVMe I/O order I/O order transmit queue 31, and control
Data to be transmitted are sent to Controller by data cache module 10.Illustratively, I/O order transmit queue 31 can incite somebody to action
NVMe I/O order is sent to Controller, and data to be transmitted are sent to Controller by data cache module 10；Or
Person, I/O order generates processing module 21 can obtain data to be transmitted to data cache module 10, and by data to be transmitted
Be input to I/O order transmit queue 31 with NVMe I/O order, later by I/O order transmit queue 31 by data to be transmitted and
NVMe I/O order is sent to Controller.
206, I/O order completes queue 41 and receives the response message that Controller is returned；
After Controller receives and processes NVMe I/O order, queue can be completed with returning response message to I/O order
41。
207, I/O order generates processing module 21 and completes to fetch response message in queue 41 from I/O order.
I/O order generates processing module 21 and can complete to fetch response message in queue 41 from I/O order, believes according to response
Breath judges whether I/O transmission succeeds.
It should be noted that if user's request processing module 50 receives read request from client layer, then can not execute
Step 304, and in step 305 I/O order generate processing module 21 without control data cache module 10 will be with transmission
Data be sent to Controller, but, I/O order transmit queue 31 by NVMe I/O order be sent to Controller it
Afterwards, data cache module 10 can receive the data corresponding with read request of Controller return, and delay to data
It deposits, is sent to client layer later, complete reading data.
Based on the corresponding embodiment of Fig. 1, Host is realized using modular hardware logic design method to control command
Processing, in some embodiments of the invention, referring to Fig. 3, Host of the present invention 300 may include:
Data cache module 10, user's request processing module 50, address conversion module 60, I/O order generate processing module
21, queue 41, control command generation processing (F/A CMD) module 22, control life are completed in I/O order transmit queue 31, I/O order
Transmit queue (ASQ) 32 and control command is enabled to complete queue (ACQ) 42.
Wherein, control command generates processing module 22 for generating NVMe control command, and NVMe control command is input to
Control command transmit queue 32, and fetch response corresponding with NVMe control command from control command completion queue 42 and disappear
Breath.The main generation for completing Fabric order and Admin order, processing, the module generate the NVMe Fabric/Admin of standard
Order and processing returns to command response.
Control command transmit queue 32, for sending Controller for NVMe control command.
Control command completes queue 42, for receiving sound that Controller is returned, corresponding with NVMe control command
Answer message.
It should be noted that control command transmit queue 32 and control command complete queue 42, being substantially two pieces has
The memory space of certain depth, for caching NVMe control command and response message.
Data cache module 10, user's request processing module 50, address conversion module 60, I/O order generate processing module
21, the particular content that queue 41 is completed in I/O order transmit queue 31 and I/O order please refers to the corresponding embodiment of Fig. 2, herein
It repeats no more.
Optionally, data cache module 10 is also used to, will be to be transmitted under the control that control command generates processing module 22
Data be sent to the Controller.
Wherein, control command may include Fabric order and Admin order, and the two can be put into same queue execution,
Therefore the two can design together.
In order to make it easy to understand, carrying data instance to be transmitted with control command, the corresponding Host of Fig. 3 is provided below to control
Make a kind of possible process flow of order:
301, control command generates processing module 22 and generates NVMe control command according to agreement；
Assuming that control command needs to send the connect data of connection (connect) order and 1KB, control command is generated
Processing module 22 can generate standard connect order according to agreement.
302, data cache module 10 receives data to be transmitted from client layer；
Assuming that control command needs to send the connect data of connection (connect) order and 1KB, data cache module
10 can the connect data to 1KB cache.
303, control command generates processing module 22 and NVMe control command is input to control command transmit queue 32, and controls
Data to be transmitted are sent to Controller by data cache module 10 processed；
Illustratively, NVMe control command can be sent to Controller by control command transmit queue 32, and data are slow
Data to be transmitted are sent to Controller by storing module 10；Alternatively, control command generation processing module 22 can be to data
Cache module 10 obtains data to be transmitted, and data to be transmitted and NVMe control command are input to control command and send team
Data to be transmitted and NVMe control command are sent to by control command transmit queue 32 by column 32 together later
Controller。
304, control command completes queue 42 and receives the response message that Controller is returned；
After Controller receives and processes NVMe control command, queue can be completed with returning response message to control command
42。
305, control command generates processing module 22 and completes to fetch response message in queue 42 from control command.
Control command generates processing module 22 and can complete to fetch and NVMe control command phase in queue 42 from control command
Corresponding response message, for example, response message corresponding with connect order can be fetched, information judges according to response
Whether connect order transmission succeeds.
After NVMe control command is sent to Controller by control command transmit queue 32, if Controller is returned
Data to data cache module 10, then control command generates processing module 22 can obtain from data cache module 10
The data that Controller is returned.
Fabric order, Admin order and data can be regarded as a series of data structure, these data structures
It is fixed, according to NVMe protocol definition.
Optionally, the Host in above-mentioned each embodiment can be applied in networking storage system, be conducive to improve net
The performance of network storage system, alternatively, the Host in above-mentioned each embodiment extend also to using NVMe agreement other
In similar interconnection system.
Referring to Fig. 4, the present invention also provides a kind of physical machine system, including Host and NVMe stores equipment, NVMe storage
Equipment includes Controller, wherein Host is Host described in any one above-mentioned embodiment.
Technical solution provided herein is described in detail above, specific case is applied in the application to this
The principle and embodiment of application is expounded, the present processes that the above embodiments are only used to help understand and
Its core concept；At the same time, for those skilled in the art in specific embodiment and is answered according to the thought of the application
With in range, there will be changes, in conclusion the contents of this specification should not be construed as limiting the present application.
Claims (10)
1. a kind of host, which is characterized in that the host is realized using hardware logic, comprising:
Data cache module 10, order generate processing module 20, order transmit queue 30 and order and complete queue 40；
Wherein, the order produces processing module 20, for generating Nonvolatile memory host controller interface specification NVMe life
It enables, the NVMe order is input to the order transmit queue 30, and fetch from order completion queue 40 and institute
State the corresponding response message of NVMe order；
Data to be transmitted for caching to data to be transmitted, and are sent to control by the data cache module 10
Device Controller is sent to client layer；
The order transmit queue 30, for the NVMe order to be sent to the Controller；
Queue 40 is completed in the order, for receiving sound that the Controller is returned, corresponding with the NVMe order
Answer message.
2. host according to claim 1, which is characterized in that the host further include:
User's request processing module 50 and address conversion module 60；
User's request processing module 50, for receiving read/write I/O request from client layer, and it is related therefrom to extract I/O order
Information, the I/O order relevant information are information needed for generating I/O order；
The address conversion module 60, the I/O order relevant information inputted for receiving user's request processing module 50, and
Carry out address conversion.
3. host according to claim 2, which is characterized in that the order generates processing module 20 and gives birth to including I/O order
At processing module 21, the order transmit queue includes I/O order transmit queue 31, and it includes order that queue 40 is completed in the order
Complete queue 41；
Wherein, the I/O order generates processing module 21, for receiving turning by address for the input of address conversion module 60
The I/O order relevant information changed generates NVMe I/O order according to the I/O order relevant information received, by the NVMe I/
O order is input to I/O order transmit queue 31, and completes to fetch and the NVMe I/O order in queue 41 from I/O order
Corresponding response message；
The I/O order transmit queue 31, for the NVMe I/O order to be sent to the Controller；
Queue 41 is completed in the I/O order, that the Controller is returned, opposite with the NVMe I/O order for receiving
The response message answered.
4. host according to claim 3, which is characterized in that the I/O order relevant information includes size of data sum number
According to address.
5. host according to claim 4, which is characterized in that the host deployments are stored in operating system of user and NVMe
Between equipment.
6. host according to claim 5, which is characterized in that the host is applied in networking storage system.
7. host according to any one of claim 1 to 6, which is characterized in that the host further include:
Control command generates processing module 22, control command transmit queue 32 and control command and completes queue 42；
Wherein, control command generates processing module 22 for generating NVMe control command, and NVMe control command is input to control
Order transmit queue 32, and complete to fetch response message in queue 42 from control command；
Control command transmit queue 32, for sending the Controller for NVMe control command；
Control command completes queue 42, for receiving sound that the Controller is returned, corresponding with NVMe control command
Answer message.
8. host according to claim 7, which is characterized in that the control command includes management Admin order and tissue
At least one of Fabric order.
9. host according to claim 8, which is characterized in that the data cache module 10 is also used to:
Data to be transmitted are sent to the Controller under the control that the control command generates processing module 22.
10. a kind of physical machine system, which is characterized in that store equipment including host and NVMe, the NVMe storage equipment includes
Controller, wherein the host is host described in any one of claim 1 to 9.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109814845A (en) * | 2019-01-30 | 2019-05-28 | 郑州云海信息技术有限公司 | A kind of NVMe model based on OOP programming |
| CN113342590A (en) * | 2021-08-06 | 2021-09-03 | 苏州浪潮智能科技有限公司 | NVMe device debugging function implementation method, device, equipment and storage medium |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103970688A (en) * | 2013-02-04 | 2014-08-06 | Lsi公司 | Method and system for reducing write latency in a data storage system |
| CN104536701A (en) * | 2014-12-23 | 2015-04-22 | 记忆科技(深圳)有限公司 | Realizing method and system for NVME protocol multi-command queues |
| US20170177216A1 (en) * | 2015-12-21 | 2017-06-22 | Intel Corporation | METHOD AND APPARATUS TO ENABLE INDIVIDUAL NON VOLATLE MEMORY EXPRESS (NVMe) INPUT/OUTPUT (IO) QUEUES ON DIFFERING NETWORK ADDRESSES OF AN NVMe CONTROLLER |
| CN107562669A (en) * | 2016-06-30 | 2018-01-09 | 北京忆芯科技有限公司 | A kind of NVMe protocol commands processing method, apparatus and system |
| US20180113615A1 (en) * | 2016-10-24 | 2018-04-26 | Samsung Electronics Co., Ltd. | Storage device generating adaptive interrupt and operating method thereof |
| CN107992436A (en) * | 2016-10-26 | 2018-05-04 | 杭州华为数字技术有限公司 | A kind of NVMe data read-write methods and NVMe equipment |
| CN108369530A (en) * | 2016-12-05 | 2018-08-03 | 华为技术有限公司 | Control method, equipment and the system of reading and writing data order in non-volatile cache transfer bus framework |
-
2018
- 2018-08-17 CN CN201810942926.0A patent/CN109165105A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103970688A (en) * | 2013-02-04 | 2014-08-06 | Lsi公司 | Method and system for reducing write latency in a data storage system |
| CN104536701A (en) * | 2014-12-23 | 2015-04-22 | 记忆科技(深圳)有限公司 | Realizing method and system for NVME protocol multi-command queues |
| US20170177216A1 (en) * | 2015-12-21 | 2017-06-22 | Intel Corporation | METHOD AND APPARATUS TO ENABLE INDIVIDUAL NON VOLATLE MEMORY EXPRESS (NVMe) INPUT/OUTPUT (IO) QUEUES ON DIFFERING NETWORK ADDRESSES OF AN NVMe CONTROLLER |
| CN107562669A (en) * | 2016-06-30 | 2018-01-09 | 北京忆芯科技有限公司 | A kind of NVMe protocol commands processing method, apparatus and system |
| US20180113615A1 (en) * | 2016-10-24 | 2018-04-26 | Samsung Electronics Co., Ltd. | Storage device generating adaptive interrupt and operating method thereof |
| CN107992436A (en) * | 2016-10-26 | 2018-05-04 | 杭州华为数字技术有限公司 | A kind of NVMe data read-write methods and NVMe equipment |
| CN108369530A (en) * | 2016-12-05 | 2018-08-03 | 华为技术有限公司 | Control method, equipment and the system of reading and writing data order in non-volatile cache transfer bus framework |
Non-Patent Citations (1)
| Title |
|---|
| 苏勇等: "一种低开销的面向节点内互连的网络接口控制器", 《苏勇》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109814845A (en) * | 2019-01-30 | 2019-05-28 | 郑州云海信息技术有限公司 | A kind of NVMe model based on OOP programming |
| CN113342590A (en) * | 2021-08-06 | 2021-09-03 | 苏州浪潮智能科技有限公司 | NVMe device debugging function implementation method, device, equipment and storage medium |
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Application publication date: 20190108 |