CN109148416A - Semiconductor device structure and forming method thereof - Google Patents
Semiconductor device structure and forming method thereof Download PDFInfo
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- CN109148416A CN109148416A CN201811011754.1A CN201811011754A CN109148416A CN 109148416 A CN109148416 A CN 109148416A CN 201811011754 A CN201811011754 A CN 201811011754A CN 109148416 A CN109148416 A CN 109148416A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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Abstract
The present invention relates to a kind of semiconductor device structures and forming method thereof, it include: semiconductor base, active area and isolated area are provided on the semiconductor base, it is sequentially overlapped along the semiconductor base and is formed with interlayer dielectric layer and patterned metal layer, the first metal plug and the second metal plug of the interlayer dielectric layer are formed through in the interlayer dielectric layer, first metal plug is located at the active area, second metal plug is located at the isolated area, and second metal plug is alignment mark when forming the patterned metal layer.In the present invention, using the second metal plug as the alignment mark of patterned metal layer, the spacer medium of isolated area can be etched away a part when via etch process, make the available raising of the depth of alignment mark, it can deepen the alignment mark, be conducive to the registration signal for reinforcing forming the alignment mark when patterned metal layer, be aligned the patterned metal layer and the alignment mark.
Description
Technical field
The present invention relates to semiconductor field, in particular to a kind of semiconductor device structure and forming method thereof.
Background technique
At present in integrated circuit fabrication process, a complete chip usually requires the light by number more than ten times
It carves, usually other than first time photoetching, the photoetching of remainder layer is that figure left by the layer with front is aligned.Due to
Semiconductor device structure processing procedure is complicated, and the number of photoetching process is more, so that plurality of layers alignment mark in exposure becomes not
It is clearly difficult to, usually alignment mark is identified using EGA (the global contraposition of enhancing), and alignment mark is required to have
There is preferable signal contrast.
For the integrated circuit technology under different process node, the signal contrast of above-mentioned alignment mark also can be poor
Not.By taking 90 nanometers of embedded flash memory technique as an example, conductive plunger (CT) is formed in inter-level dielectric (ILD) layer and carries out chemical machine
After tool polishes (CMP) technique, due to design thickness reduction and the relationship of load effect, in the register guide identified for EGA
Interlayer dielectric layer thickness at note is lower, when it is subsequent above interlayer dielectric layer by patterning process formed metal layer when, by
It is faint in registration signal, cause metal layer and CT deviation occur when being aligned.
Summary of the invention
The purpose of the present invention is to provide a kind of semiconductor device structure and forming method thereof, with solve in the prior art by
It is faint in registration signal, cause metal layer and CT the problem of deviation occur when being aligned.
In order to solve the problems in the existing technology, the present invention provides a kind of semiconductor device structures, comprising: partly leads
Body substrate is provided with active area and isolated area on the semiconductor base, is sequentially overlapped along the semiconductor base and is formed with layer
Between dielectric layer and patterned metal layer, be formed through in the interlayer dielectric layer interlayer dielectric layer the first metal insert
Plug and the second metal plug, first metal plug are located at the active area, second metal plug be located at described in every
From area, second metal plug is alignment mark when forming the patterned metal layer.
Optionally, in the semiconductor device structure, the depth of second metal plug is greater than first metal
The depth of plug.
Optionally, in the semiconductor device structure, the depth of first metal plug is 3100 angstroms~3200 angstroms；
The depth of second metal plug is 3600 angstroms~3800 angstroms.
Optionally, in the semiconductor device structure, it is provided with isolation structure in the semiconductor base of the isolated area,
Second metal plug is located in the isolation structure.
Optionally, in the semiconductor device structure, the depth of the isolation structure is 4200 angstroms~4800 angstroms.
Optionally, in the semiconductor device structure, the depth of first metal plug and the interlayer dielectric layer
Thickness it is equal.
Optionally, in the semiconductor device structure, the interlayer dielectric layer includes oxide, nitride and nitrogen oxidation
At least one of object.
The present invention also provides a kind of forming methods of semiconductor device structure, comprising the following steps:
Semiconductor base is provided, is provided with active area and isolated area on the semiconductor base；
Interlayer dielectric layer is formed on the semiconductor base；
The first metal plug and the second metal of the interlayer dielectric layer are formed through in the interlayer dielectric layer
Plug, first metal plug are located at the active area, and second metal plug is located at the isolated area；
Metal material layer is formed above the interlayer dielectric layer；
Using second metal plug as alignment mark, the metal material layer is patterned, forms patterned gold
Belong to layer.
Optionally, in the forming method of the semiconductor device structure, described is formed in the interlayer dielectric layer
The step of one metal plug and second metal plug includes:
First through hole and the second through-hole, the first through hole are formed in the interlayer dielectric layer using dry etch process
Positioned at the active area, second through-hole is located at the isolated area, also, the depth of second through-hole is greater than described first
The depth of through-hole；
Conductive material is filled in the first through hole and second through-hole, to form first metal plug and institute
State the second metal plug.
Optionally, in the forming method of the semiconductor device structure, using second metal plug as alignment mark,
The metal material layer is patterned, formed patterned metal layer the step of include:
Second metal plug is identified using the global contraposition of enhancing, and second metal that will identify that is inserted
Plug is used as the alignment mark.
Semiconductor device structure provided by the present invention includes the semiconductor base provided with active area and isolated area, along institute
It states semiconductor base and is sequentially overlapped and be formed with interlayer dielectric layer and patterned metal layer, be formed with position in the interlayer dielectric layer
The first metal plug in the active area and the second metal plug positioned at the isolated area, second metal plug are
Form the alignment mark when patterned metal layer.In the present invention, using the second metal plug formed in isolated area as
The alignment mark of patterned metal layer, since the via etch process of interlayer dielectric layer can be by the spacer medium of the isolated area extremely
Eating away a part after a little while, the available raising of depth of the second metal plug as alignment mark, it can it is described right to deepen
Position label (i.e. the second metal plug), be conducive to reinforce being formed the alignment mark when patterned metal layer to definite message or answer
Number, it is aligned the patterned metal layer and the alignment mark.
Detailed description of the invention
Fig. 1 is the flow chart of the forming method of semiconductor device structure provided in an embodiment of the present invention.
Fig. 2 is that the diagrammatic cross-section after isolated area is formed on semiconductor base provided in an embodiment of the present invention.
Fig. 3 is the diagrammatic cross-section after interlayer dielectric layer provided in an embodiment of the present invention.
Fig. 4 is the diagrammatic cross-section of through-hole provided in an embodiment of the present invention.
Fig. 5 is the diagrammatic cross-section of the first metal plug and the second metal plug provided in an embodiment of the present invention.
Fig. 6 is the diagrammatic cross-section of patterned metal layer provided in an embodiment of the present invention.
Wherein, 10- semiconductor base；11- isolated area；20- interlayer dielectric layer；21- first through hole；The second through-hole of 22-；；
The first metal plug of 31-；The second metal plug of 32-；40- patterned metal layer.
Specific embodiment
A specific embodiment of the invention is described in detail below in conjunction with schematic diagram.According to following description, originally
The advantages of invention and feature will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-accurate
Ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.It should be understood that working as layer (or film), region, figure
Case or structure are referred to as at substrate, layer (or film), region and/or pattern "upper", it can be located immediately at another layer or lining
On bottom, and/or there may also be insert layers.Similar, when layer is referred to as at another layer of "lower", it can be located immediately at another
Under one layer, and/or there may also be one or more insert layers.Furthermore it is possible to be carried out based on attached drawing about in each layer "upper"
With the reference of "lower".
The present invention provides a kind of semiconductor device structures and forming method thereof.Below first to the semiconductor of the present embodiment
The forming method of device architecture is illustrated.
Fig. 1 is the flow chart of the forming method of semiconductor device structure provided in an embodiment of the present invention.The semiconductor device
The forming method of part structure the following steps are included:
S1: semiconductor base is provided, is provided with active area and isolated area on the semiconductor base；
S2: interlayer dielectric layer is formed on the semiconductor base；
S3: the first metal plug and the second metal for running through the interlayer dielectric layer are formed in the interlayer dielectric layer
Plug, first metal plug are located at the active area, and second metal plug is located at the isolated area；
S4: metal material layer is formed above the interlayer dielectric layer；
S5: using second metal plug as alignment mark, patterning the metal material layer, forms patterning
Metal layer.
In the present invention, by forming isolated area in alignment mark region, by etching the spacer medium to deepen
Alignment mark (i.e. the second metal plug) is stated, thus reinforce the registration signal of the patterned metal layer and the alignment mark,
It is aligned the patterned metal layer and the alignment mark.
Common, the material of the semiconductor base can be silicon, germanium, SiGe or silicon carbide etc., be also possible to insulator
On cover silicon (SOI) perhaps germanium on insulator (geoi) (GOI) or can also be III, V races such as other materials, such as GaAs
Close object.In other embodiments, the semiconductor base may include the epitaxial layer of doping, can be injected according to design requirement
Certain doping particle is to change electrical parameter.
It is described further below in conjunction with forming method of the attached drawing to the semiconductor device structure of the embodiment of the present invention.
As shown in Fig. 2, Fig. 2 is the section signal after forming isolated area on semiconductor base provided in an embodiment of the present invention
Figure.The forming method of semiconductor device structure provided by the embodiment of the present invention includes step S1: providing semiconductor base 10, institute
It states and is provided with active area and isolated area 11 on semiconductor base 10.
The isolated area 11 can be formed in fleet plough groove isolation structure (STI) formation process on semiconductor base 10,
Such as photoetching or etching technics form opening in semiconductor base 10, and fill this using one or more spacer mediums and open
Mouthful.Common, the fleet plough groove isolation structure includes silica or other suitable materials as spacer medium, thus semiconductor
The isolated area 11 of substrate 10 can be formed in the body layer (such as silicon) on semiconductor base 10 filled with spacer medium
The isolation structure of (such as silica), the range and shape of isolation structure can be according to the subsequent alignment marks formed above it
Range and shape determine.The range of active area can pass through the fleet plough groove isolation structure and isolated area 11 in semiconductor base 10
It limits.
As shown in figure 3, Fig. 3 is the diagrammatic cross-section after interlayer dielectric layer provided in an embodiment of the present invention.The present invention
The forming method of semiconductor device structure provided by embodiment includes step S2: depositing interlayer on the semiconductor base 10
Dielectric layer 20.
The interlayer dielectric layer 20 may include at least one of oxide, nitride and nitrogen oxides.Usual situation
Under, in different process conditions, the thickness of the interlayer dielectric layer 20 of deposition be can also be different.In the present embodiment, in EF90 (90
Nanometer embedded flash memory technique platform) in, the thickness for generally depositing the interlayer dielectric layer 20 is about 4000 angstroms~5000 angstroms.
Referring to Fig. 4 and Fig. 5, the forming method of semiconductor device structure provided by the embodiment of the present invention includes step S3:
The first metal plug 31 and the second metal that the interlayer dielectric layer 20 is formed through in the interlayer dielectric layer 20 are inserted
Plug 32, first metal plug 31 is located at the active area, and second metal plug 32 is located at the isolated area 11.
Further, first metal plug 31 is formed in the interlayer dielectric layer 20 and second metal is inserted
Plug 32, step include:
Firstly, first through hole 21 and the second through-hole 22 are formed in the interlayer dielectric layer 20 using dry etch process,
The first through hole 21 is located at the active area, and second through-hole 21 is located at the isolated area 11, also, suitable by selection
Dry etch process, the dry etch process complete to the interlayer dielectric layer 20 at first through hole 21 and the second through-hole 22
After etching, can also over etching be generated to the spacer medium of isolated area 11, so that the depth of second through-hole 22 is greater than
The depth of the first through hole 21.
Specifically, referring to FIG. 4, Fig. 4 is through-hole diagrammatic cross-section provided in an embodiment of the present invention.In the inter-level dielectric
Etching forms through-hole in layer 20, and wherein first through hole 21 is located at active area, the first metal plug 31 is used to form, to make upper layer
Patterned metal layer 40 connect with the conductive structure of active area.Second through-hole 22 is located in the isolated area 11, is used to form
Second metal plug 32 using as formed upper layer patterned metal layer 40 when alignment mark.As shown in figure 5, Fig. 5 is this hair
The first metal plug and the second metal plug diagrammatic cross-section that bright embodiment provides.In the first through hole 21 and described second
Conductive material is filled in through-hole 22, to form metal plug (CT).Preferably, the conductive material can use tungsten.
It is common, after first metal plug 31 and second metal plug 32 are formed, by using chemistry
The removal of mechanical lapping (CMP) technique is located at the conductive material on 20 surface of interlayer dielectric layer.Although due to design thickness reduce and
The thickness of the relationship of CMP process load effect, the first metal plug 31 is lower, but utilizes semiconductor device provided by the present embodiment
The forming method of part structure, the lower surface of the second metal plug 32 is lower than the lower surface of the first metal plug 31, thus compared with first
Metal plug 31 is thicker, for example, when the first metal plug 31 is with a thickness of 3100 angstroms to 3200 angstroms, the second metal plug 32
Thickness is about 3600 angstroms to 3800 angstroms.To using the second metal plug 32 as upper layer pattern metal layer 40 (Fig. 6)
When alignment mark, design thickness reduction and the influence of CMP process load effect can be reduced, it is easier to be identified by EGA, favorably
In improving the contraposition accuracy of patterned metal layer 40, to be conducive to improve product yield.
Then, step S4 is executed, forms metal material layer above the interlayer dielectric layer 20；First metal plug
31 and second metal plug 32 be embedded in the interlayer dielectric layer 20, therefore the metal material layer is covered in first gold medal
Belong on plug 31, second metal plug 32 and the interlayer dielectric layer 20.Common, the metal material layer can be adopted
Use metallic aluminium as material.
As shown in fig. 6, Fig. 6 is the diagrammatic cross-section of patterned metal layer provided in an embodiment of the present invention.The present invention is implemented
The forming method of semiconductor device structure provided by example includes step S5: with second metal plug 32 for alignment mark,
The metal material layer is patterned, patterned metal layer 40 is formed.
The metal material layer is patterned, when forming patterned metal layer 40, can use the global contraposition of enhancing
Second metal plug 32 that identifies, and will identify that second metal plug 32 is used as the alignment mark.
It is deposited on the interlayer dielectric layer 20 specifically, being formed by patterned metal layer 40, patterned metal layer 40
It is aligned with second metal plug 32 (CT).By deepening the depth of second metal plug 32 in the present invention, thus plus
The registration signal of the strong patterned metal layer 40 and second metal plug 32 makes the patterned metal layer 40 and described
Second metal plug 32 can be preferably aligned.
The present invention also provides a kind of semiconductor device structures.Referring to Fig. 6, the present invention also provides semiconductor device structure
In, comprising: semiconductor base 10 is provided with active area and isolated area 11 on the semiconductor base 10, along described semiconductor-based
Bottom 10, which is sequentially overlapped, is formed with interlayer dielectric layer 20 and patterned metal layer 40, is formed through in the interlayer dielectric layer 20
The first metal plug 31 and the second metal plug 32 of the interlayer dielectric layer 20, first metal plug 31 are located at described
Active area, second metal plug 32 are located at the isolated area 11, and second metal plug 32 is to form the patterning
Alignment mark when metal layer 40.
In the present invention, isolated area is formed with by the alignment mark region when forming the patterned metal layer 40
11, spacer medium when etching isolated area 11 to form the alignment mark (i.e. the second metal plug 32), in isolated area 11
It can be etched, that is, it is larger to be formed by alignment mark depth, when identifying using EGA to alignment mark, can reinforce institute
The registration signal for stating patterned metal layer 40 and the alignment mark is conducive to the patterned metal layer 40 and the register guide
Note alignment, improves the qualification rate of product.
In the present embodiment, the depth of the isolation structure of isolated area 11 is 4200~4800 angstroms, its specific depth can be
4300 angstroms, 4500 angstroms or 4700 angstroms etc..
It is common, positioned at the depth and the thickness phase of the interlayer dielectric layer 20 of first metal plug 31 of active area
Deng for being electrically connected the patterned metal layer 40 and the conductive structure.The depth of second metal plug 32 is big
In the depth of first metal plug 31, second metal plug 32 is alignment mark, increases the depth of the alignment mark
Degree, can reinforce the registration signal of the patterned metal layer 40 and the alignment mark.
Further, the patterned metal layer 40 is deposited on the interlayer dielectric layer 20, forms patterned metal layer
When 40, it can use second metal plug 32 (CT) and be aligned as alignment mark (EGAalignmentmark).It is logical
Normal, the patterned metal layer 40 may include the metal materials such as aluminium, tungsten, copper.By deepening second gold medal in the present invention
The depth for belonging to plug 32 makes institute to reinforce the registration signal of the patterned metal layer 40 and second metal plug 32
Stating patterned metal layer 40 and second metal plug 32 can preferably be aligned.
To sum up, semiconductor device structure provided by the present invention includes semiconductor-based provided with active area and isolated area
Bottom is sequentially overlapped along the semiconductor base and is formed with interlayer dielectric layer and patterned metal layer, in the interlayer dielectric layer
It is formed with the second metal plug positioned at the first metal plug of the active area and positioned at the isolated area, second gold medal
Belonging to plug is alignment mark when forming the patterned metal layer.In the present invention, the second metal that will be formed in isolated area
Alignment mark of the plug as patterned metal layer, due to interlayer dielectric layer via etch process can by the isolated area every
A part is at least etched away from medium, the available raising of depth of the second metal plug as alignment mark, it can add
The deep alignment mark (i.e. the second metal plug) is conducive to reinforce forming the alignment mark when patterned metal layer
Registration signal is aligned the patterned metal layer and the alignment mark.
Illustrate to being given for example only property of above-described embodiment the principles and effects of invention, and is not intended to limit the present invention.Appoint
What person of ordinary skill in the field, without violating the spirit and scope of the present invention, can to the invention discloses technology
Scheme and technology contents make the variation such as any type of equivalent replacement or modification, and still fall within protection scope of the present invention.
Claims (10)
1. a kind of semiconductor device structure characterized by comprising semiconductor base, being provided on the semiconductor base has
Source region and isolated area are sequentially overlapped along the semiconductor base and are formed with interlayer dielectric layer and patterned metal layer, in the layer
Between the first metal plug and the second metal plug of the interlayer dielectric layer, first metal are formed through in dielectric layer
Plug is located at the active area, and second metal plug is located at the isolated area, and second metal plug is described to be formed
Alignment mark when patterned metal layer.
2. semiconductor device structure as described in claim 1, which is characterized in that the depth of second metal plug is greater than institute
State the depth of the first metal plug.
3. semiconductor device structure as claimed in claim 2, which is characterized in that the depth of first metal plug is 3100
Angstrom~3200 angstroms；The depth of second metal plug is 3600 angstroms~3800 angstroms.
4. semiconductor device structure as claimed in claim 2, which is characterized in that be arranged in the semiconductor base of the isolated area
There is isolation structure, second metal plug is located in the isolation structure.
5. semiconductor device structure as claimed in claim 4, which is characterized in that the depth of the isolation structure be 4200 angstroms~
4800 angstroms.
6. semiconductor device structure as claimed in claim 2, which is characterized in that the depth of first metal plug with it is described
The thickness of interlayer dielectric layer is equal.
7. semiconductor device structure as described in claim 1, which is characterized in that the interlayer dielectric layer includes oxide, nitrogen
At least one of compound and nitrogen oxides.
8. a kind of forming method of semiconductor device structure, which comprises the following steps:
Semiconductor base is provided, is provided with active area and isolated area on the semiconductor base；
Interlayer dielectric layer is formed on the semiconductor base；
The first metal plug and the second metal plug of the interlayer dielectric layer are formed through in the interlayer dielectric layer,
First metal plug is located at the active area, and second metal plug is located at the isolated area；
Metal material layer is formed above the interlayer dielectric layer；
Using second metal plug as alignment mark, the metal material layer is patterned, forms patterned metal layer.
9. the forming method of semiconductor device structure as claimed in claim 8, which is characterized in that in the interlayer dielectric layer
The step of forming first metal plug and second metal plug include:
First through hole and the second through-hole are formed in the interlayer dielectric layer using dry etch process, the first through hole is located at
The active area, second through-hole is located at the isolated area, also, the depth of second through-hole is greater than the first through hole
Depth；
Conductive material is filled in the first through hole and second through-hole, to form first metal plug and described
Two metal plugs.
10. the forming method of semiconductor device structure as claimed in claim 8, which is characterized in that inserted with second metal
Filling in the step of being alignment mark, patterning to the metal material layer, form patterned metal layer includes:
Made using second metal plug that the global contraposition of enhancing identifies second metal plug, and will identify that
For the alignment mark.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113611660A (en) * | 2021-07-30 | 2021-11-05 | 上海华虹宏力半导体制造有限公司 | Method for forming semiconductor device |
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| US20040195586A1 (en) * | 2001-05-25 | 2004-10-07 | Hisamitsu Suzuki | Semiconductor device and method of fabricating same |
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| US6255715B1 (en) * | 1997-09-19 | 2001-07-03 | Taiwan Semiconductor Manufacturing Company | Fuse window guard ring structure for nitride capped self aligned contact processes |
| US20040195586A1 (en) * | 2001-05-25 | 2004-10-07 | Hisamitsu Suzuki | Semiconductor device and method of fabricating same |
| US20090045530A1 (en) * | 2007-08-14 | 2009-02-19 | International Business Machines Corporation | Microelectronic lithographic alignment using high contrast alignment mark |
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| CN113611660A (en) * | 2021-07-30 | 2021-11-05 | 上海华虹宏力半导体制造有限公司 | Method for forming semiconductor device |
| CN113611660B (en) * | 2021-07-30 | 2024-03-22 | 上海华虹宏力半导体制造有限公司 | Method for forming semiconductor device |
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