CN109144914A - Communication means and CPLD between a kind of storage server, mainboard and hard disk - Google Patents
Communication means and CPLD between a kind of storage server, mainboard and hard disk Download PDFInfo
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- CN109144914A CN109144914A CN201810829404.XA CN201810829404A CN109144914A CN 109144914 A CN109144914 A CN 109144914A CN 201810829404 A CN201810829404 A CN 201810829404A CN 109144914 A CN109144914 A CN 109144914A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
This application discloses the communication means and CPLD between a kind of storage server, mainboard and hard disk, the storage server includes: mainboard, complex programmable logic device (CPLD), hard disk backboard, the first hard disk and the second hard disk, mainboard is connect with CPLD by I2C bus, CPLD is connect with the first hard disk and the second hard disk by SMBus bus respectively, on the first hard disk and the inserting to hard disk backboard of the second hard disk；Mainboard is used for after sending the first operational order, sends the second operational order to CPLD by SMBus interface, SMBus interface is configured to I2C mode；CPLD is used for after being sent to the first hard disk, and the second operational order is sent to the second hard disk by the corresponding 2nd SMBus interface of the second hard disk.Using the high advantage of traffic rate between mainboard and CPLD, mainboard may be implemented that simultaneously multiple hard disks are managed or are accessed etc. with operation, so as to improve the communication efficiency between mainboard and multiple hard disks.
Description
Technical field
This application involves fields of communication technology, more particularly to the communication between a kind of storage server, mainboard and hard disk
Method and CPLD.
Background technique
Currently, storage server generally includes mainboard, hard disk backboard and multiple hard disks, wherein multiple hard disks insert
On hard disk backboard, it is connected between mainboard and hard disk backboard by high speed connection.In practical application, mainboard can pass through
SMBus (System Management Bus, System Management Bus) bus is communicated with the hard disk on hard disk backboard, with reality
Now to the management of hard disk, access etc..
Wherein, SMBus is a kind of binary universal serial bus, is typically based on I2C (Inter-Integrated
Circuit, internal integrated circuit) bus specification, it can mainly work in master/slave mode: when main device (such as mainboard) provides
Clock provides a start bit when main device initiates primary transmission, and a stop position is provided when main device terminates primary transmission,
And possessing the slave address of devices of one unique 7 or 10 if device (such as hard disk), main device can be according to from device
Address to the operation such as being managed or access from device.
In storage server, main device of the mainboard as SMBus can hang multiple hard disks below and be used as from device, mainboard
It is usually connected to the SMBus interface of multiple hard disks by the SMBus interface on mainboard, the pipe to multiple hard disks is realized with this
Reason and access.But within the same period, mainboard can only at most be communicated with a hard disk, so that mainboard and hard
When being communicated based on SMBus bus, communication efficiency is lower between disk.
Summary of the invention
The technical problem to be solved in the embodiments of the present application is that providing between a kind of storage server, mainboard and hard disk
Communication means and CPLD, to improve the communication efficiency in storage server between mainboard and hard disk.
In a first aspect, the embodiment of the present application provides a kind of storage server, the storage server includes mainboard, complexity
Programmable logic device (CPLD), hard disk backboard, the first hard disk and the second hard disk, the mainboard and the CPLD pass through internal collection
It being connected at circuit I 2C bus, the CPLD manages bus SMBus bus by first server with first hard disk and connect,
The CPLD and second hard disk manage bus SMBus bus by second server and connect, first hard disk with it is described
In the inserting to the hard disk backboard of second hard disk；
The mainboard, for after sending the first operational order to the CPLD by the SMBus interface on the mainboard,
The second operational order is sent to the CPLD by the SMBus interface, the SMBus interface is configured to I2C mode；
The CPLD, for passing through the corresponding first SMBus interface of first hard disk for first operational order
After being sent to first hard disk, second operational order is sent out by the corresponding 2nd SMBus interface of second hard disk
Give second hard disk.
In some possible embodiments, the first SMBus interface and the 2nd SMBus interface are located at described hard
On disk backboard.
In some possible embodiments, the CPLD is also used in the data for receiving the first hard disk passback
Afterwards, the data of the passback are temporarily stored into corresponding first register of first hard disk, and are determining that the I2C bus is empty
Data in first register are sent to the mainboard by idle.
In some possible embodiments, the CPLD is also used to be directed to institute receive that the mainboard sends
After the third operational order for stating the first hard disk, the third operational order is temporarily stored into corresponding second deposit of first hard disk
In device, and when determining the first SMBus bus free, the third operational order in second register is sent to institute
State the first hard disk.
Second aspect, the embodiment of the present application also provides a kind of method communicated between mainboard and hard disk, the side
Method is applied in storage server described in first aspect, this method comprises:
The mainboard is being referred to by the SMBus interface for being configured to I2C mode to the first operation of CPLD transmission
After order, the second operational order is sent to the CPLD by the SMBus interface；
First operational order received and second operational order are sent respectively to described by the CPLD
First hard disk and second hard disk, it is described in order to which first hard disk executes first operational order received
Second hard disk executes second operational order received.
In some possible embodiments, the method also includes:
The CPLD is temporarily stored into described the after the data for receiving first hard disk passback, by the data of the passback
In corresponding first register of one hard disk；
Whether the CPLD inquires the I2C bus idle；
If it is determined that the I2C bus free, then be sent to the mainboard for the data in first register.
In some possible embodiments, the method also includes:
The third operational order is temporarily stored into institute in the third operational order for receiving the mainboard transmission by the CPLD
It states in corresponding second register of the first hard disk；
Whether the CPLD inquires the first SMBus bus idle；
If it is determined that the third operational order in second register, then be sent to by the first SMBus bus free
First hard disk.
The third aspect, the embodiment of the present application also provides a kind of complex programmable logic device (CPLD), the CPLD includes
From device blocks, the first main device module and the second main device module；
It is described from device blocks, for receiving mainboard by being configured to the server pipe of internal integrated circuit I2C mode
Manage bus SMBus interface send the first operational order and the second operational order, the mainboard and it is described from device blocks it
Between connected by I2C bus；
The first main device module, for passing through inserting to corresponding first SMBus of the first hard disk on hard disk backboard
First operational order is sent to first hard disk by interface, between the first main device module and first hard disk
It is attached by the first SMBus bus；
The second main device module, for passing through inserting to corresponding 2nd SMBus of the second hard disk on hard disk backboard
First operational order is sent to second hard disk by interface, between the second main device module and second hard disk
It is attached by the 2nd SMBus bus.
In some possible embodiments, the CPLD further includes corresponding first register of the first hard disk；
The first main device module, is also used to receive the data of the first hard disk passback, and the data are kept in
In first register；
It is described to be also used to from device blocks when determining the I2C bus free, by the data in first register
It is sent to the mainboard.
In some possible embodiments, the CPLD further includes corresponding second register of the second hard disk；
It is described to be also used to receive the third operational order of the mainboard transmission from device blocks, and the third is operated
Instruction is temporarily stored into second register；
The first main device module, is also used to when determining the first SMBus bus free, and described second is deposited
Third operational order in device is sent to first hard disk.
In the above-mentioned implementation of the embodiment of the present application, since the clock frequency of I2C bus reaches as high as 3.4MKHz,
And the clock frequency of the first SMBus bus is 100KHz, this is much higher than the message transmission rate between mainboard and CPLD
Message transmission rate between CPLD and the first hard disk.Therefore, CPLD sends the first operational order and first to the first hard disk
Hard disk needs longer period of time to CPLD passback inner parameter, and within this time, the I2C between mainboard and CPLD is total
Line is in idle condition always.Based on this, the first operational order and the first hard disk are sent to CPLD to the first hard disk in CPLD
It returns in inner parameter this period, the CPU on mainboard can continue to send to CPLD to the second hard disk by SMBus interface
Second operational order of operations such as it is managed or accesses, second operational order is equally via between mainboard and CPLD
I2C bus transfer is to CPLD.In this way, the advantage high using traffic rate between mainboard and CPLD, mainboard may be implemented right simultaneously
Multiple hard disks such as are managed or access at the operation, so as to improve the communication efficiency between mainboard and multiple hard disks.
Detailed description of the invention
In order to more clearly explain the technical solutions in the embodiments of the present application, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations as described in this application
Example, for those of ordinary skill in the art, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the structural schematic diagram of existing storage server；
Fig. 2 is a kind of structural schematic diagram of storage server of the embodiment of the present application；
Communication means flow diagram of the Fig. 3 between host a kind of in the embodiment of the present application and hard disk；
Fig. 4 is a kind of structural schematic diagram of CPLD in the embodiment of the present application.
Specific embodiment
As shown in Figure 1, hard disk 1021, hard disk in existing storage server, on mainboard 101 and hard disk backboard 102
1022 etc. can be attached by SMBus bus, and the CPU on mainboard 101 is by the way that the SMBus interface on mainboard to be connected to firmly
The SMBus interface of disk 1021 and the SMBus interface of hard disk 1022, come realize management to hard disk 1021 and hard disk 1022 or
Person's access.
But inventor it has been investigated that, the SMBus interface on mainboard can usually be compatible with I2C agreement, as the SMBus
When interfaces are under I2C mode, clock frequency can reach 3.4MKHz, and the clock frequency highest of SMBus bus is only
There is 100KHz, belong to low speed bus, this SMBus interface for allowing for connecting on mainboard with hard disk 1021 and hard disk 1022 cannot
Performance is played completely, and traffic rate is lower, moreover, mainboard can only be with one firmly using the SMBus interface within the same period
Disk is communicated, for example, mainboard can only just can use SMBus interface and hard disk 1022 with after 1021 sign off of hard disk
Start to be communicated, this just further reduced logical when being communicated based on SMBus bus between mainboard and multiple hard disks
Believe efficiency.
For this purpose, the embodiment of the present application provides a kind of storage server, it is logical by increasing by one between mainboard and hard disk
Cross CPLD (Complex Programmable Logic Device, complicated programmable logic device that I2C bus is connect with mainboard
Part), allow mainboard multiple hard disks to be managed or accesss etc. simultaneously and operate, to improve between mainboard and multiple hard disks
Communication efficiency, wherein CPLD is a kind of user according to respective the need and voluntarily digital integrated electronic circuit of constitutive logic function.
Specifically, referring to fig. 2, Fig. 2 shows the structural schematic diagrams of storage server a kind of in the embodiment of the present application, this is deposited
Storage server can specifically include: mainboard, CPLD, hard disk backboard, the first hard disk, the second hard disk.
Wherein, it is attached between mainboard and CPLD by I2C bus, and the first hard disk on CPLD and hard disk backboard is logical
It crosses the first SMBus bus to be attached, be attached with the second hard disk on hard disk backboard by the 2nd SMBus bus, first
Hard disk and the second hard disk are inserted on hard disk backboard.In some instances, the first hard disk all can be supported with the second hard disk
SSD (the Solid State of NVMe (Non-Volatile Memory express, non-volatile memories standard) standard
Drives, solid state hard disk).It should be noted that the first hard disk and the second hard disk herein is only used as example to explain the application
The technical solution of embodiment is not used to limit on hard disk backboard hard disk there are two only configurations, in fact, on the hard disk backboard
More hard disks can also be inserted.
If desired mainboard manages or accesses the first hard disk and the second hard disk, then the CPU on mainboard can be by being located at
The SMBus interface for being configured to I2C mode on mainboard sends to CPLD and the operation such as the first hard disk is managed or is accessed
The first operational order, first operational order is via the I2C bus transfer between mainboard and CPLD to CPLD.
CPLD can use preconfigured the first operational order of SMBus interface for supporting I2C agreement, and according to this
First operational order determines the first SMBus interface configured in advance for the first hard disk, it is then possible to pass through the first SMBus
Interface sends the first operational order to the first hard disk, and first operational order is via first between hard disk backboard and the first hard disk
SMBus bus transfer receives first operational order by corresponding hard-disk interface by the first hard disk to the first hard disk.It is practical
In, the first hard disk starts to execute corresponding operation after receiving the first operational order, and by the ginseng of the first hard drive internal
It counts and CPLD is returned to by SMBus bus after being packaged.
It should be noted that since the clock frequency of I2C bus reaches as high as 3.4MKHz, and the first SMBus bus when
Clock frequency is 100KHz, this makes the message transmission rate between mainboard and CPLD much higher than the number between CPLD and the first hard disk
According to transmission rate.Therefore, CPLD sends the first operational order and the first hard disk to the first hard disk and returns inner parameter to CPLD
Longer period of time is needed, and within this time, the I2C bus between mainboard and CPLD is in idle condition always.
In order to improve the communication efficiency between mainboard and hard disk, in the present embodiment, first is sent to the first hard disk in CPLD
Operational order and the first hard disk return in inner parameter this period to CPLD, and the CPU on mainboard can be connect by SMBus
Mouthful, continue to send the second operational order for the operations such as the second hard disk being managed or being accessed to CPLD, which refers to
It enables equally via the I2C bus transfer between mainboard and CPLD to CPLD.That is, being managed in mainboard to the first hard disk
Or in the operating process such as access, mainboard also starts to carry out corresponding operation to the second hard disk.
CPLD, can be according to second behaviour after using the SMBus interface to the second operational order for supporting I2C agreement
It instructs, determines the 2nd SMBus interface configured in advance for the second hard disk, and hard to second by the 2nd SMBus interface
Disk sends the second operational order, which passes via the 2nd SMBus bus between hard disk backboard and the second hard disk
The second hard disk is transported to, and second operational order is received by corresponding hard-disk interface by the second hard disk, and starts to execute corresponding
Operation.
The technical solution of the present embodiment in order to facilitate understanding, is illustrated below with simple examples:
In application scenes, mainboard needs while reading the parameters such as the temperature of the first hard disk and the second hard drive internal,
Then mainboard can send first to CPLD and read instruction, for reading the parameter of the first hard drive internal, the first reading instruction base
In I2C bus transfer into CPLD；Then, CPLD can read instruction for receive first and be sent to the first hard disk, by the
One hard disk reads after corresponding parameter is packaged by instruction according to first received and returns to CPLD, wherein first reads
The parameter of instruction and passback is based on SMBus bus and is transmitted.Since CPLD sends the first operational order to the first hard disk
And first hard disk to CPLD passback be packaged supplemental characteristic during, the required time far more than between mainboard and CPLD into
The time of row data transmission, moreover, I2C bus is also at idle state, therefore, in the process, mainboard can will read the
The second of two hard drive internal parameters reads instruction and is sent to CPLD, to start to carry out corresponding operation to the second hard disk.In this way, main
Plate also starts to operate the second hard disk during operating the first hard disk.
In the present embodiment, increase the CPLD connecting by I2C bus with mainboard between mainboard and hard disk, then,
Passed through during mainboard carries out corresponding operating to the first hard disk using the high advantage of traffic rate between mainboard and CPLD
Continue to send the second operational order to CPLD, corresponding operation also is carried out to the second hard disk, so that mainboard can be right simultaneously
Multiple hard disks such as are managed or access at the operation, improve the communication efficiency between mainboard and multiple hard disks.
In some scenes of practical application, mainboard may be just to exist after carrying out operation a period of time to the first hard disk
To the demand that the second hard disk is operated, at this point, in order to enable mainboard sends second operated to the second hard disk to CPLD
Operational order will not send the data that the first hard disk returns to mainboard with CPLD and clash, can be by configuring in CPLD
Storage carrys out temporal data, to avoid the generation of this kind of conflict.
Specifically, can configure the first register in CPLD for the first hard disk, which is used for temporal data.
After CPLD receives the data of the first hard disk passback, can by the data it is temporary in the first register, it is then possible to inquire
Whether the I2C bus between present motherboards and CPLD is in idle condition, if I2C bus free, CPLD can be posted first
In storage keep in return data be sent to mainboard, if I2C bus be not be to be in idle condition, show present motherboards with
It carries out carrying out data communication using the I2C bus between CPLD, then the data of the passback can be continued to temporary and the first deposit
In device, until when determining I2C bus free, then send the data to mainboard.In this way, it is avoided that number between CPLD and mainboard
The case where being clashed according to communication.
Further, it is also possible to avoid rushing for the data communication between CPLD and each hard disk by configuring additional register
It is prominent.For example, CPLD receives mainboard when the first hard disk needs to return the data being packaged based on the first operational order to CPLD
The third operational order that the first hard disk is operated sent, at this point, CPLD sends third operational order and the first hard disk
The data being packaged are returned, are required to occupy the first SMBus bus between CPLD and the first hard disk, to generate data communication
Conflict.
It, can in a kind of example herein to avoid being illustrated for generation communication contention aware between CPLD and the first hard disk
To be that the second register is arranged in the first hard disk in CPLD, which is equally used for temporal data.When CPLD is being received
It, can third operational order is temporary and the second register after the third operational order for being directed to the first hard disk sent to mainboard
In, whether the first SMBus bus that then can be inquired between CPLD and the first hard disk is in idle condition, however, it is determined that first
SMBus bus free, then third operational order can be sent to the first hard disk by CPLD, however, it is determined that the first SMBus bus is not
It is in idle condition, is showing the first hard disk currently to CPLD transmission data.At this point, CPLD can be by third control command
Continue to be temporarily stored into the second register, and when determining that the first SMBus bus is in idle condition, then will be in the second register
Third operational order is sent to the first hard disk.
It can be that each hard disk configures corresponding two registers in CPLD, for keeping in mainboard in practical application
The data returned to the CPLD operational order sent and hard disk to CPLD.Certainly, in other embodiments, or
Each hard disk only configures a register, which is both used to keep in the operational order that mainboard is sent to CPLD, is also used for temporarily
It deposits the data that hard disk is returned to CPLD, when specific implementation, can be configured according to the needs of actual conditions, it is not limited here.
In addition, the storage server introduced based on the above embodiment, the embodiment of the present application also provides a kind of mainboard and firmly
The method communicated between disk.It shows in the embodiment of the present application refering to Fig. 3, Fig. 3 and is led between a kind of mainboard and hard disk
The method flow schematic diagram of letter, this method can be applied in storage server shown in Fig. 2, and this method can specifically include:
S301: mainboard leads to after the SMBus interface by being configured to I2C mode sends the first operational order to CPLD
It crosses SMBus and sends the second operational order to CPLD.
In the present embodiment, if desired mainboard manages or accesses the first hard disk and the second hard disk, then the CPU on mainboard can
To send the first operational order for the operations such as the first hard disk being managed or being accessed to CPLD by SMBus interface, and
Second operational order of operations, first operational order and second operational order such as the second hard disk is managed or is accessed
Via the I2C bus transfer between mainboard and CPLD to CPLD.
It should be noted that in the present embodiment when sending the first operational order and the second operational order, on mainboard
CPU is that the first operational order is first sent to CPLD, then determines whether the I2C bus between mainboard and CPLD is in idle shape
State, if it is, the second operational order can be sent to CPLD, if it is not, showing that there are numbers between present motherboards and CPLD
According to communication, then after can waiting I2C bus free, then the second operational order is sent to CPLD.
S302:CPLD by the first operational order received and the second operational order be sent respectively to the first hard disk and
Second hard disk, in order to which the first hard disk executes the first operational order received, the second hard disk executes the second operation received
Instruction.
In the present embodiment, CPLD can use the preconfigured SMBus interface for supporting I2C agreement and receive the first behaviour respectively
Make instruction and the second operational order, and determines in advance to be the first of the configuration of the first hard disk according to first operational order
SMBus interface is determined in advance according to first operational order as the first SMBus interface of the first hard disk configuration.Then, CPLD
The first operational order can be sent to the first hard disk by the first SMBus interface, first operational order is via hard disk backboard
The first SMBus bus transfer to the first hard disk between the first hard disk, and connect by the first hard disk by corresponding hard-disk interface
Receive first operational order；Meanwhile CPLD can send the second operational order to the second hard disk by the 2nd SMBus interface,
Second operational order is via the 2nd SMBus bus transfer to the second hard disk between hard disk backboard and the second hard disk, and by
Two hard disks receive second operational order by corresponding hard-disk interface.
In this way, the first hard disk can execute the first operational order received, start to carry out corresponding operation, for example, can
To be to be packaged the parameters such as the temperature of the first hard drive internal, and return to mainboard etc.；Similar, the second hard disk can execute
The second operational order received starts to carry out corresponding operation.
It is noted that since the clock frequency of I2C bus reaches as high as 3.4MKHz, and the first SMBus bus when
Clock frequency is 100KHz, this makes the message transmission rate between mainboard and CPLD much higher than the number between CPLD and the first hard disk
According to transmission rate.Therefore, CPLD sends the first operational order and the first hard disk to the first hard disk and returns inner parameter to CPLD
Longer period of time is needed, and within this time, the I2C bus between mainboard and CPLD is in idle condition always.Base
In this, in the present embodiment, join inside CPLD is returned to the first hard disk the first operational order of transmission and the first hard disk to CPLD
In number this periods, CPU on mainboard can by SMBus interface, continue to send to CPLD the second hard disk is managed or
Second operational order of the operations such as person's access, second operational order is equally via the I2C bus transfer between mainboard and CPLD
To CPLD.In this way, the advantage high using traffic rate between mainboard and CPLD, mainboard may be implemented simultaneously to carry out multiple hard disks
The operation such as management or access, so as to improve the communication efficiency between mainboard and multiple hard disks.
In practical application, in order to avoid being clashed when carrying out data communication between mainboard and CPLD and CPLD and hard
It is clashed when being communicated between disk, in the present embodiment, can also register be set in CPLD to keep in data.
Specifically, being illustrated by taking the first hard disk as an example, the first register can be configured for the first hard disk in CPLD, first deposit
Device is used for temporal data.It, can the data are temporary and the first register after CPLD receives the data of the first hard disk passback
In, it is then possible to whether the I2C bus inquired between present motherboards and CPLD is in idle condition, if I2C bus free,
The return data kept in first register can be sent to mainboard by CPLD, if it is to be in idle condition that I2C bus, which is not,
Show to carry out carrying out data communication using the I2C bus between present motherboards and CPLD, then can continue the data of the passback
In temporary and the first register, until when determining I2C bus free, then send the data to mainboard.In this way, it is avoided that CPLD
The case where data communication between mainboard clashes.
At the same time it can also be that the second register is arranged in the first hard disk in CPLD, which is equally used for keeping in
Data.When CPLD receive mainboard transmission the third operational order for being directed to the first hard disk after, can by third operate refer to
It enables in temporary and the second register, whether the first SMBus bus that then can be inquired between CPLD and the first hard disk is in empty
Not busy state, however, it is determined that the first SMBus bus free, then third operational order can be sent to the first hard disk by CPLD, however, it is determined that
First SMBus bus is not at idle state, is showing the first hard disk currently to CPLD transmission data.At this point, CPLD
Third control command can be continued to be temporarily stored into the second register, and when determining that the first SMBus bus is in idle condition,
The third operational order in the second register is sent to the first hard disk again.In this manner it is possible to avoid CPLD and the first SMBus total
Line carries out the case where clashing when data communication.
In addition, the embodiment of the present application also provides a kind of complex programmable logic device (CPLD)s.It is shown refering to Fig. 4, Fig. 4
A kind of structural schematic diagram of complex programmable logic device (CPLD), the CPLD can be applied to shown in Fig. 2 in the embodiment of the present application
In storage server, which be can specifically include: from device blocks 401, the first main device module 4021 and the second main device
Part module 4022.
Wherein, from device blocks 401, it can be used for receiving mainboard by being configured to internal integrated circuit I2C mode
The first operational order and the second operational order that SMBus interface is sent, mainboard and are connected between device blocks by I2C bus
It connects；
First main device module 4021 can be used for through inserting to the first hard disk corresponding first on hard disk backboard
First operational order is sent to the first hard disk by SMBus interface, passes through first between the first main device module and the first hard disk
SMBus bus is attached；
Second main device module 4022 can be used for through inserting to the second hard disk corresponding second on hard disk backboard
First operational order is sent to the second hard disk by SMBus interface, passes through second between the second main device module and the second hard disk
SMBus bus is attached.
It should be noted that being to include two hard disks of the first hard disk and the second hard disk on hard disk backboard in the present embodiment
For in the CPLD that is illustrated, therefore is shown in the present embodiment only comprising the first main device module and the second main device mould
Block, still, in practical application, main module can be corresponded with the hard disk on hard disk backboard, it can in CPLD be each
Hard disk configures a main module.
In some possible embodiments, CPLD further includes corresponding first register of the first hard disk；
First main device module 4021, is also used to receive the data of the first hard disk passback, and the data are temporarily stored into first
In register；
It from device blocks 401, is also used to inquire whether I2C bus is in idle condition, and is determining I2C bus free
When, the data in the first register are sent to mainboard.
In some possible embodiments, CPLD further includes corresponding second register of the second hard disk；
It from device blocks 401, is also used to receive the third operational order of mainboard transmission, and third operational order is temporarily stored into
In second register；
First main device module 4021, is also used to inquire whether the first SMBus bus is in idle condition, and is determining
When one SMBus bus free, the third operational order in the second register is sent to the first hard disk.
It should be noted that the CPLD, which can be, to be set on hard disk backboard in practical application, but it is possible at other
Embodiment in, be also possible to be set on mainboard.
In the present embodiment, increase the CPLD connecting by I2C bus with mainboard between mainboard and hard disk, then,
Passed through during mainboard carries out corresponding operating to the first hard disk using the high advantage of traffic rate between mainboard and CPLD
Continue to send the second operational order to CPLD, corresponding operation also is carried out to the second hard disk, so that mainboard can be right simultaneously
Multiple hard disks such as are managed or access at the operation, improve the communication efficiency between mainboard and multiple hard disks.
In the titles such as " the first hard disk " mentioned in the embodiment of the present application, " the first register ", " the first SMBus bus "
" first " is used only to do name mark, does not represent first sequentially.The rule is equally applicable to " second " etc..
As seen through the above description of the embodiments, those skilled in the art can be understood that above-mentioned implementation
All or part of the steps in example method can add the mode of general hardware platform to realize by software.Based on this understanding,
The technical solution of the application can be embodied in the form of software products, which can store is situated between in storage
In matter, such as read-only memory (English: read-only memory, ROM)/RAM, magnetic disk, CD etc., including some instructions to
So that a computer equipment (can be the network communication equipments such as personal computer, server, or router) executes
Method described in certain parts of each embodiment of the application or embodiment.
All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment
Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Especially for method reality
For applying example and apparatus embodiments, since it is substantially similar to storage server embodiment, so describe fairly simple, it is related
Place illustrates referring to the part of storage server embodiment.Embodiments described above is only schematical, wherein
Module may or may not be physically separated as illustrated by the separation member, and the component shown as module can be with
It is or may not be physical module, it can it is in one place, or may be distributed over multiple network units.It can
It is achieved the purpose of the solution of this embodiment with selecting some or all of the modules therein according to the actual needs.This field is common
Technical staff can understand and implement without creative efforts.
The above is only the illustrative embodiment of the application, is not intended to limit the protection scope of the application.
Claims (10)
1. a kind of storage server, which is characterized in that the storage server includes mainboard, Complex Programmable Logic Devices
CPLD, hard disk backboard, the first hard disk and the second hard disk, the mainboard and the CPLD pass through internal integrated circuit I2C bus
Connection, the CPLD and first hard disk are connect by first server management bus SMBus bus, the CPLD with it is described
Second hard disk manages the connection of bus SMBus bus by second server, and first hard disk is arrived with second hard disk inserting
On the hard disk backboard；
The mainboard, for passing through after sending the first operational order to the CPLD by the SMBus interface on the mainboard
The SMBus interface sends the second operational order to the CPLD, and the SMBus interface is configured to I2C mode；
The CPLD, for being sent first operational order by the corresponding first SMBus interface of first hard disk
After first hard disk, second operational order is sent to by the corresponding 2nd SMBus interface of second hard disk
Second hard disk.
2. server according to claim 1, which is characterized in that the first SMBus interface connects with the 2nd SMBus
Mouth is located on the hard disk backboard.
3. server according to claim 1, which is characterized in that
The CPLD is also used to after the data for receiving the first hard disk passback, the data of the passback is temporarily stored into institute
It states in corresponding first register of the first hard disk, and when determining the I2C bus free, by the number in first register
According to being sent to the mainboard.
4. server according to claim 1, which is characterized in that
The CPLD, after being also used to be directed to the third operational order of first hard disk receive that the mainboard sends,
The third operational order is temporarily stored into corresponding second register of first hard disk, and is determining the first SMBus
When bus free, the third operational order in second register is sent to first hard disk.
5. a kind of method communicated between mainboard and hard disk, which is characterized in that the method is applied to claim 1 to power
Benefit requires in 4 described in any item storage servers, which comprises
The mainboard after sending the first operational order to the CPLD by the SMBus interface for being configured to I2C mode,
The second operational order is sent to the CPLD by the SMBus interface；
First operational order received and second operational order are sent respectively to described first by the CPLD
Hard disk and second hard disk, in order to which first hard disk executes first operational order that receives, described second
Hard disk executes second operational order received.
6. according to the method described in claim 5, it is characterized in that, the method also includes:
It is hard that the CPLD is temporarily stored into described first after the data for receiving the first hard disk passback, by the data of the passback
In corresponding first register of disk；
Whether the CPLD inquires the I2C bus idle；
If it is determined that the I2C bus free, then be sent to the mainboard for the data in first register.
7. according to the method described in claim 5, it is characterized in that, the method also includes:
The CPLD is temporarily stored into described the in the third operational order for receiving the mainboard and sending, by the third operational order
In corresponding second register of one hard disk；
Whether the CPLD inquires the first SMBus bus idle；
If it is determined that the third operational order in second register, then be sent to described by the first SMBus bus free
First hard disk.
8. a kind of complex programmable logic device (CPLD), which is characterized in that the CPLD includes from device blocks, the first main device
Module and the second main device module；
It is described from device blocks, it is total by the server admin for being configured to internal integrated circuit I2C mode for receiving mainboard
Line SMBus interface send the first operational order and the second operational order, the mainboard and it is described between device blocks lead to
Cross the connection of I2C bus；
The first main device module, for passing through inserting to the corresponding first SMBus interface of the first hard disk on hard disk backboard
First operational order is sent to first hard disk, is passed through between the first main device module and first hard disk
First SMBus bus is attached；
The second main device module, for passing through inserting to the corresponding 2nd SMBus interface of the second hard disk on hard disk backboard
First operational order is sent to second hard disk, is passed through between the second main device module and second hard disk
2nd SMBus bus is attached.
9. CPLD according to claim 8, which is characterized in that the CPLD further includes corresponding first deposit of the first hard disk
Device；
The first main device module, is also used to receive the data of the first hard disk passback, and the data are temporarily stored into institute
It states in the first register；
It is described to be also used to from device blocks when determining the I2C bus free, the data in first register are sent
To the mainboard.
10. CPLD according to claim 8, which is characterized in that the CPLD further includes that the second hard disk corresponding second is posted
Storage；
It is described to be also used to receive the third operational order that the mainboard is sent from device blocks, and by the third operational order
It is temporarily stored into second register；
The first main device module, is also used to when determining the first SMBus bus free, will be in second register
Third operational order be sent to first hard disk.
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| CN201810829404.XA CN109144914A (en) | 2018-07-25 | 2018-07-25 | Communication means and CPLD between a kind of storage server, mainboard and hard disk |
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| CN201810829404.XA CN109144914A (en) | 2018-07-25 | 2018-07-25 | Communication means and CPLD between a kind of storage server, mainboard and hard disk |
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