CN109144906B

CN109144906B - Electronic equipment and its command dma processing method

Info

Publication number: CN109144906B
Application number: CN201710451238.XA
Authority: CN
Inventors: 黄好城; 王祎磊; 伍德斌; 兰彤
Original assignee: Beijing Yixin Technology Co Ltd
Current assignee: Beijing Yixin Technology Co Ltd
Priority date: 2017-06-15
Filing date: 2017-06-15
Publication date: 2019-11-26
Anticipated expiration: 2037-06-15
Also published as: CN110737614A; CN109144906A; CN110737614B

Abstract

This application discloses electronic equipment and its command dma processing methods.Disclosed electronic equipment includes direct memory access accelerator, and the data packet that direct memory access accelerator provides central processing unit is converted to direct memory access order and memory is written；And obtain the implementing result of the direct memory access order in memory；Direct memory access module initiates direct memory access transmission according to the direct memory access order obtained from memory, and memory is written in the implementing result of direct memory access order；Electronic equipment is by physical layer block with the external device communication of electronic equipment.The DMA accelerator substitution CPU of the application is interacted with memory, is significantly reduced the load of CPU, is accelerated the processing speed of command dma.

Description

Electronic equipment and its command dma processing method

Technical field

This application involves the direct memory access skills in technical field of electronic equipment more particularly to a kind of electronic equipment Art.

Background technique

DMA can be carried out between electronic equipment and external equipment, and (Direct Memory Access, direct memory are visited Ask) transmission.As shown in Figure 1, carrying out DMA transfer between electronic equipment 100 and external equipment 300.Electronic equipment 100 includes physics Layer (PHY) module 110, dma module 120, memory 130 and central processing unit (CPU) 140.

By generating command dma, (or dma descriptor is used to indicate in electronic equipment 100 and external equipment CPU 140 One or many DMA transfers between 300) and memory 130 is written to indicate that dma module 120 carries out DMA transfer.Also, it rings Should be in the completion of DMA transfer, memory 130 is written in the implementing result of command dma by dma module 120, so that CPU 140 be made to know Know command dma processing to complete, and obtains the implementing result of command dma.

External equipment 300 is coupled to electronic equipment 100 by PHY module 110.PHY module 110 can be for handling The PCIe PHY module of PCIe underlying protocol, the FC PHY module for handling FC underlying protocol or for handling Ethernet bottom The ethernet PHY module of agreement.Dma module 120 is tieed up between external equipment 300 and electronic equipment 100 by PHY module 110 Protect DMA transfer.For example, dma module 120 obtains the command dma of instruction DMA transfer from memory 130, then according to command dma Initiate DMA transfer.

Electronic equipment 100 is additionally coupled to memory 400.In DMA transfer, under the control of dma module 120, it will store The data of device 400 are transferred to external equipment 300, or the data that external equipment 300 is provided are stored to memory 400.As Citing, memory 400 is DRAM (dynamic random access memory), and compared with memory 130, memory 400 has bigger Memory capacity.

CPU establishes descriptor table or descriptor chained list in memory 130, includes one group in descriptor table or chained list Descriptor, each descriptor all describe data block moving direction, source address, destination-address and the byte optionally transmitted Number.Therefore, during processing, CPU does not need to be moved to each data block of a certain destination from a certain source to DMA and control Device processed is programmed operation.

But, wherein when CPU exchanges command dma by memory 130 with dma module, CPU is needed by dma module requirement Format and data structure submit command dma, which increase the burdens of CPU.

Summary of the invention

The application's is designed to provide electronic equipment and its direct memory access command handling method, for mitigating The burden of CPU and the processing speed for accelerating command dma.

In order to achieve the above objectives, according to a first aspect of the present application, the first electricity according to the application first aspect is provided Sub- equipment, wherein including physical layer block, direct memory access module, memory, direct memory access accelerator and Central processing unit, physical layer block are coupled with direct memory access module, and memory is coupled to direct memory access module With direct memory access accelerator, direct memory access accelerator is coupled with central processing unit；

Wherein, the data packet that direct memory access accelerator provides central processing unit is converted to direct memory access It orders and memory is written；And obtain the implementing result of the direct memory access order in memory；

Direct memory access module initiates direct memory according to the direct memory access order obtained from memory Access transport, and memory is written into the implementing result of direct memory access order；

Electronic equipment is by physical layer block with the external device communication of electronic equipment.

The first electronic equipment according to a first aspect of the present application provides the second electronics according to the application first aspect Equipment, wherein direct memory access accelerator is equipped with streaming interface or first in, first out interface for central processing unit access.

The first electronic equipment according to a first aspect of the present application provides the third electronics according to the application first aspect Equipment, direct memory access accelerator, which is equipped with, reads interface for the streaming write-in interface and streaming of central processing unit access.

First according to a first aspect of the present application provides one of to third electronic equipment according to the application first aspect The 4th electronic equipment, wherein direct memory access accelerator includes direct memory access order receiving unit and first Processing unit；Wherein:

Direct memory access order receiving unit is coupled to central processing unit and first processing units, and direct memory is visited Ask that order receiving unit receives the data packet that central processing unit provides；And

First processing units are coupled with memory, and first processing units are obtained from direct memory access order receiving unit The data packet that central processing unit provides, is converted to direct memory access order for data packet, and memory is written.

One of first to fourth electronic equipment according to a first aspect of the present application is provided according to the application first aspect The 5th electronic equipment, wherein direct memory access accelerator include direct memory access order complete unit and second Processing unit；Wherein:

The second processing unit is coupled with memory, and the second processing unit obtains direct memory access order from memory and holds Row result；And

Direct memory access order completion unit is coupled to the second processing unit and central processing unit, and direct memory is visited It asks that order completes unit and obtains the implementing result of direct memory access order from the second processing unit, and is mentioned to central processing unit For the implementing result of direct memory access order.

The the 4th to the 5th electronic equipment according to a first aspect of the present application provides according to the application first aspect Six electronic equipments, wherein direct memory access order receiving unit and/or direct memory access order are completed unit and be equipped with Buffer area.

One of first to the 6th electronic equipment according to a first aspect of the present application is provided according to the application first aspect The 7th electronic equipment, wherein multiple direct memory access orders of memory storage are organized as queue, and the first processing is single According to the write pointer of queue memory is written in direct memory access order by member.

The 7th electronic equipment according to a first aspect of the present application provides the 8th electronics according to the application first aspect Equipment, wherein the read pointer of the second processing unit foundation queue obtains the execution knot of direct memory access order from memory Fruit.

The 8th electronic equipment according to a first aspect of the present application provides the 9th electronics according to the application first aspect Equipment, wherein the second processing unit is received by central processing unit according to the implementing result of direct memory access order and updated Run through pointer.

The 9th electronic equipment according to a first aspect of the present application provides the tenth electronics according to the application first aspect Equipment, wherein direct memory access accelerator further includes pointer management device, pointer management device and first processing units and second Processing unit coupling, first processing units obtain write pointer from pointer management device, and the second processing unit is obtained from pointer management device Read pointer and to pointer management device update run through pointer.

The 9th electronic equipment according to a first aspect of the present application provides the 11st electricity according to the application first aspect Sub- equipment, wherein first processing units are coupled with the second processing unit, and first processing units are run through from the second processing unit acquisition At pointer.

The 9th electronic equipment according to a first aspect of the present application provides the 12nd electricity according to the application first aspect Sub- equipment, wherein the second processing unit runs through pointer to memory write-in, and first processing units are obtained from memory and read Complete pointer.

One of first to the 6th electronic equipment according to a first aspect of the present application is provided according to the application first aspect The 13rd electronic equipment, wherein the multiple direct memory access orders stored in memory are organized as chained list, linear list Or array.

One of first to the 13rd electronic equipment according to a first aspect of the present application is provided according to the application first party 14th electronic equipment in face, wherein direct memory access order indicates direct memory access module in multiple data frames The data to be transmitted of middle transmission data packet instruction.

The 14th electronic equipment according to a first aspect of the present application, provides the 15th according to the application first aspect Electronic equipment, wherein the size of data frame is 512 bytes.

The 14th electronic equipment according to a first aspect of the present application, provides the 16th according to the application first aspect Electronic equipment, wherein the size of data frame is the data block size encrypted with Advanced Encryption Standard.

The 14th electronic equipment according to a first aspect of the present application, provides the 17th according to the application first aspect Electronic equipment, wherein the size of data frame is the size of the data block verified with cyclic redundancy check code.

One of first to 17 electronic equipment according to a first aspect of the present application is provided according to the application first aspect The 18th electronic equipment, wherein by multiple mutually independent between direct memory access accelerator and central processing unit Stream carries out data transmission.

One of first to 17 electronic equipment according to a first aspect of the present application is provided according to the application first aspect The 19th electronic equipment, wherein data packet indicator identifiers, direct memory access accelerator determine direct according to identifier The storage address of memory access command in memory.

One of second to 17 electronic equipment according to a first aspect of the present application is provided according to the application first aspect The 20th electronic equipment, wherein direct memory access accelerator includes that one or more streaming interfaces or first in, first out connect Mouthful, streaming interface or first in, first out interface of the direct memory access accelerator according to received data packet determine direct memory The storage address of visit order in memory.

According to a second aspect of the present application, the first direct memory access order according to the application second aspect is provided Processing method includes the following steps:

Received data packet；

Data packet is converted into direct memory access order, and memory is written；

Be updated in response to the implementing result of the direct memory access order in memory, obtain be updated directly deposit The implementing result of reservoir visit order.

The first direct memory access command handling method according to a second aspect of the present application, provides according to the application Second direct memory access command handling method of second aspect, wherein include: to be carried out data transmission by streaming interface.

The second direct memory access command handling method according to a second aspect of the present application, provides according to the application The third direct memory access command handling method of second aspect is wherein, comprising:

The status indication of streaming interface is provided；

If the status indication of streaming interface is available mode label, write from streaming interface data packet or to streaming interface Enter the implementing result of direct memory access order.

The first direct memory access command handling method according to a second aspect of the present application, provides according to the application 4th direct memory access command handling method of second aspect is wherein, comprising: carries out data biography by first in, first out interface It is defeated.

The 4th direct memory access command handling method according to a second aspect of the present application, provides according to the application 5th direct memory access command handling method of second aspect is wherein, comprising:

The state of first in, first out interface is provided；

If the First Input First Output in first in, first out interface is less than, from first in, first out interface data packet.

The 4th direct memory access command handling method according to a second aspect of the present application, provides according to the application 6th direct memory access command handling method of second aspect is wherein, comprising:

The state of first in, first out interface is provided；

If the First Input First Output in first in, first out interface is non-empty, visited to first in, first out interface write-in direct memory Ask the implementing result of order.

One of first to the 6th direct memory access command handling method according to a second aspect of the present application, provides Wherein according to the 7th direct memory access command handling method of the application second aspect, comprising:

Memory is written into direct memory access order according to write pointer；

Write pointer is updated, and memory is written into updated write pointer；

Acquisition runs through pointer；

Wherein, write pointer is directed toward the tail of the queue that the queue of direct memory access order is stored in memory, runs through pointer It is directed toward team's head that the queue of direct memory access order is stored in memory；

Wherein, foundation runs through pointer and lags behind write pointer, determines and stores direct memory access order in memory Queue is less than；When queue only in memory is less than, memory is written into direct memory access order.

The 7th direct memory access command handling method according to a second aspect of the present application, provides according to the application Wherein, direct memory access module is from the team in memory for 8th direct memory access command handling method of second aspect Team's head of column obtains direct memory access order；

It is completed in response to direct memory access order, direct memory access module is by direct memory access order Implementing result be written memory, update storage the read pointer in device.

The 7th direct memory access command handling method according to a second aspect of the present application, provides according to the application 9th direct memory access command handling method of second aspect wherein, is ahead of in response to read pointer and runs through pointer, according to According to run through pointer from memory obtain direct memory access order implementing result；

Update runs through pointer；

Wherein, memory is written into response to the implementing result of direct memory access order and update read pointer.

The 7th direct memory access command handling method according to a second aspect of the present application, provides according to the application Tenth direct memory access command handling method of second aspect is wherein, comprising:

In response to read pointer from run through that pointer is different, the execution knot of direct memory access order is obtained from memory Fruit.

One of the 7th to the tenth direct memory access command handling method according to a second aspect of the present application, provides Wherein according to the 11st direct memory access command processing method of the application second aspect, further includes: pointer will be run through Memory is written.

One of first to the 11st direct memory access command processing method according to a second aspect of the present application, provides Wherein according to the 12nd direct memory access command handling method of the application second aspect, by multiple mutually independent Stream carries out data transmission, and each stream is corresponded with the queue in memory.

The 12nd direct memory access command handling method according to a second aspect of the present application, provides according to this Shen Please second aspect the 13rd direct memory access command handling method wherein, further includes:

The status indication of each stream is provided；

If the status indication of stream is available mode label, by flowing received data packet；

Direct memory access order is written in memory and indicated by data packet according to stream indicated by data packet Flow corresponding queue；

By the corresponding stream of queue where the direct memory access order that is completed, by direct memory access order Implementing result be supplied to central processing unit.

One of direct memory access command processing method of first to 11 according to a second aspect of the present application, provides Wherein according to the 14th direct memory access command handling method of the application second aspect, pass through multiple mutually independent streams Carry out data transmission with multiple streaming interfaces；Stream is corresponded with streaming interface；

Direct memory access command handling method includes:

Stream belonging to streaming interface identification data packet according to received data packet；

It is visited to streaming interface corresponding with the stream where the direct memory access order being completed write-in direct memory Ask the implementing result of order.

The first to 14 direct memory access command handling method according to a second aspect of the present application, provides basis Wherein, direct memory access order instruction is straight for 15th direct memory access command handling method of the application second aspect Connect the data to be transmitted that memory access module transmits data packet instruction in multiple data frames.

The 15th direct memory access command handling method according to a second aspect of the present application, provides according to this Shen Please second aspect the 16th direct memory access command handling method wherein, the size of data frame is to use Advanced Encryption Standard The data block size of encryption.

The 15th direct memory access command handling method according to a second aspect of the present application, provides according to this Shen Please second aspect the 17th direct memory access command handling method wherein, the size of data frame is to use cyclic redundancy check The size of the data block of code check.

According to the third aspect of the application, provides and exchange the first of information by queue according to the application third aspect Method, comprising:

Queue is written in first message by first producer；

First consumer obtains first message from queue；

The first message in queue is written in the processing result of first message by the first consumer；Wherein, the place of first message It manages result and forms second message；

Second consumer obtains second message from queue.

According to the first method for exchanging information by queue of the third aspect of the application, provide according to the application third The second method that information is exchanged by queue of aspect, wherein first producer writes first message according to the write pointer of queue Enqueue；

First consumer obtains first message from queue according to the read pointer of queue；

According to read pointer queue is written in second message by the first consumer.

According to the first method for exchanging information by queue of the third aspect of the application, provide according to the application third The third method that information is exchanged by queue of aspect, wherein first producer writes first message according to the write pointer of queue Enqueue；

First consumer records the position of first message in the queue, and second message is written according to the position recorded Queue.

The first of information is exchanged one of to third method by queue according to the third aspect of the application, provides basis The fourth method that information is exchanged by queue of the application third aspect, wherein the second consumer runs through finger according to queue Needle obtains second message from queue.

The second of information is exchanged one of to fourth method by queue according to the third aspect of the application, provides basis The fourth method that information is exchanged by queue of the application third aspect, wherein include:

It is written into queue in response to first message, updates write pointer；

It is written into queue in response to second message, updates read pointer.

According to the fourth method for exchanging information by queue of the third aspect of the application, provide according to the application third The 6th method that information is exchanged by queue of aspect, wherein include: to obtain second from queue in response to the second consumer to disappear Breath, update run through pointer.

According to the fourth method for exchanging information by queue of the third aspect of the application, provide according to the application third The 7th method that information is exchanged by queue of aspect, wherein include: that will run through pointer write-in memory, first producer Pointer is run through from memory acquisition.

According to the fourth method for exchanging information by queue of the third aspect of the application, provide according to the application third The eighth method that information is exchanged by queue of aspect, wherein include: that the second consumer will run through pointer to be supplied to first raw Production person.

According to second or the third method for exchanging information by queue of the third aspect of the application, provide according to this Shen Please the third aspect by queue exchange information the 9th method, wherein include:

Write pointer is supplied to the first consumer by first producer；

Read pointer is supplied to the second consumer by the first consumer.

According to one of the first to the 9th method for exchanging information by queue of the third aspect of the application, basis is provided The tenth method that information is exchanged by queue of the application third aspect, wherein write pointer includes unrolling label or to unroll Number information.

According to one of the 4th to the 9th method for exchanging information by queue of the third aspect of the application, basis is provided The 11st method that information is exchanged by queue of the application third aspect, wherein refer in response to running through pointer and read pointer To identical address, the second consumer pause obtains second message from queue.

According to one of the 4th to the 11st method for exchanging information by queue of the third aspect of the application, root is provided The 12nd method of information is exchanged by queue according to the application third aspect, wherein be ahead of in response to running through pointer and write Pointer, first producer, which suspends to queue, is written first message.

According to one of the 4th to the 12nd method for exchanging information by queue of the third aspect of the application, root is provided According to the 13rd method for exchanging information by queue of the application third aspect, wherein run through team's head that pointer is directed toward queue； The tail of the queue of write pointer direction queue.

According to one of the first to the 13rd method for exchanging information by queue of the third aspect of the application, root is provided According to the 14th method for exchanging information by queue of the application third aspect, wherein provide queue in memory.

According to one of the first to the 14th method for exchanging information by queue of the third aspect of the application, root is provided The 15th method of information is exchanged by queue according to the application third aspect, wherein first producer with the second consumer is Direct memory access accelerator；

First consumer is direct memory access processing module；

First message is direct memory access order, and second message is the processing result of direct memory access order.

The 14th method for exchanging information by queue according to the third aspect of the application is provided according to the application the The 16th method that information is exchanged by queue of three aspects, wherein memory includes multiple mutually independent queues, and first is raw Production person, the first consumer and the second consumer exchange information by multiple queues.

According to the fourth aspect of the application, the system according to the first of the application fourth aspect the processing queue, packet are provided It includes:

Queue is written in first message by first producer；

First consumer obtains first message from queue；And the in queue is written into the processing result of first message One message；Wherein, the processing result of first message forms second message；

Second consumer obtains second message from queue.

According to the system of the first of the fourth aspect of the application the processing queue, the according to the application fourth aspect is provided The systems of two processing queues, wherein queue includes:

Write pointer indicates the address that message is written to queue；

Read pointer, the first consumer of instruction read the address of message from queue.

According to the system of the second processing queue of the fourth aspect of the application, according to the application fourth aspect is provided The system of three processing queues, wherein according to the write pointer of queue queue is written in first message by first producer；

According to the system of the second processing queue of the fourth aspect of the application, according to the application fourth aspect is provided The system of four processing queues, wherein according to the write pointer of queue queue is written in first message by first producer；

According to one of the system of the first to fourth of the fourth aspect of the application processing queue, provide according to the application the The system of 5th processing queue of four aspects, wherein queue further includes running through pointer, and the second consumer of instruction reads from queue The address of message.

According to the system of the 5th of the fourth aspect of the application the processing queue, the according to the application fourth aspect is provided The system of six processing queues, wherein the second consumer obtains second message from queue according to the pointer that runs through of queue.

According to one of the system of the second to the 6th of the fourth aspect of the application the processing queue, provide according to the application the The system of 7th processing queue of four aspects, wherein be written into queue in response to first message, update write pointer；

It is written into queue in response to second message, updates read pointer.

According to one of the system of the 5th to the 7th of the fourth aspect of the application the processing queue, provide according to the application the The system of 8th processing queue of four aspects, wherein obtain second message from queue in response to the second consumer, update is run through Pointer.

According to the system of the 5th of the fourth aspect of the application the processing queue, the according to the application fourth aspect is provided The systems of nine processing queues, wherein further include memory, run through pointer and be written into memory, first producer is from memory Acquisition runs through pointer.

According to the system of the 5th of the fourth aspect of the application the processing queue, the according to the application fourth aspect is provided The system of ten processing queues, wherein the second consumer will run through pointer and be supplied to first producer.

According to the third of the fourth aspect of the application or the system of fourth process queue, provide according to the application four directions The system of the 11st processing queue in face, wherein write pointer is supplied to the first consumer by first producer；

Read pointer is supplied to the second consumer by the first consumer.

According to the system of the first to the 11st of the fourth aspect of the application the processing queue, provide according to the application the 4th The system of 12nd processing queue of aspect, wherein write pointer includes unroll label or the number information that unrolls.

According to the system of the 5th to the 12nd of the fourth aspect of the application the processing queue, provide according to the application the 4th The system of 13rd processing queue of aspect, wherein be directed toward identical address in response to running through pointer and read pointer, second disappears Expense person's pause obtains second message from queue.

According to the system of the 5th to the 13rd of the fourth aspect of the application the processing queue, provide according to the application the 4th The system of 14th processing queue of aspect, wherein be ahead of write pointer in response to running through pointer, first producer suspend to First message is written in queue.

According to the system of the 5th to the 14th of the fourth aspect of the application the processing queue, provide according to the application the 4th The system of 15th processing queue of aspect, wherein run through team's head that pointer is directed toward queue；The team of write pointer direction queue Tail.

According to the system of the first to the 15th of the fourth aspect of the application the processing queue, provide according to the application the 4th The system of 16th processing queue of aspect, wherein queue is provided in memory.

According to the system of the first to the 16th of the fourth aspect of the application the processing queue, provide according to the application the 4th The system of 17th processing queue of aspect, wherein first producer and the second consumer are direct memory access accelerators；

First consumer is direct memory access processing module；

According to the system of the first to the 17th of the fourth aspect of the application the processing queue, provide according to the application the 4th The system of 18th processing queue of aspect, wherein memory includes multiple mutually independent queues, first producer, first Consumer and the second consumer pass through multiple queues exchange information.

What the technical solution of the application obtained has the beneficial effect that:

(1) the DMA accelerator substitution CPU of the application is interacted with memory, and substitution CPU generation meets dma module institute The command dma of the requirements such as format, the conveying length needed, and the data structure of command dma in CPU maintenance memory is substituted, by DMA Order write-in memory, and the state of command dma updates in supervisory memory, and the implementing result of command dma is supplied to CPU significantly reduces the load of CPU, accelerates the processing speed of command dma.

(2) for the application by using streaming interface, CPU writes data into stream, without be concerned about data storage address and Data structure, to alleviate the load of CPU；When reading data, CPU obtains data by using streaming interface from stream, It need not be concerned about the storage address and data structure of data；Although streaming interface provides accessible address, this may have access to ground Location is single address or specified address, and CPU need not handle the update of address, need not also carry out memory management.

(3) the application is by the maintenance to queue in memory, so that the first processing units of DMA accelerator and DMA mould The second processing unit of a pair of of the producer and consumer of block formation queue, dma module and DMA accelerator forms the another of queue To the producer and consumer, single queue be both used for DMA accelerator to dma module submit command dma, be also used for dma module to DMA accelerator submits the implementing result of command dma, reduces the demand to the memory space of memory.

Detailed description of the invention

In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, will be described below to embodiment Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only some of the application Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these Figure obtains other attached drawings.

Fig. 1 is the system construction drawing of the DMA transfer of the prior art；

Fig. 2 is the system construction drawing according to the DMA transfer of the embodiment of the present application；

Fig. 3 is that the signal of interface is written in the streaming provided according to the direct memory access accelerator of the embodiment of the present application Figure；

Fig. 4 is that the streaming provided according to the direct memory access accelerator of the embodiment of the present application reads the signal of interface Figure；

Fig. 5 is the structure chart for the direct memory access accelerator that the embodiment of the present application one provides；

Fig. 6 to Figure 10 is the pointer schematic diagram of the single queue provided according to the embodiment of the present application one；

Figure 11 is the structure chart for the direct memory access accelerator that the embodiment of the present application two provides；

Figure 12 is the flow chart for the direct memory access command handling method that the embodiment of the present application three provides；And

Figure 13 is that the CPU of the embodiment of the present application executes direct memory access operation by direct memory access accelerator Flow chart.

Specific embodiment

Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete Site preparation description, it is clear that described embodiment is some embodiments of the present application, instead of all the embodiments.Based on this Shen Please in embodiment, every other implementation obtained by those of ordinary skill in the art without making creative efforts Example, shall fall in the protection scope of this application.

Fig. 2 is the system construction drawing according to the DMA transfer of the embodiment of the present application.As shown in Fig. 2, electronic equipment 200 includes Physical layer block (PHY module) 210, direct memory access module (dma module) 220, memory 230, direct memory are visited Ask accelerator (DMA accelerator) 240 and central processing unit (CPU) 250.PHY module 210 is coupled with dma module 220, storage Device 230 is coupled to dma module 220 and DMA accelerator 240, and DMA accelerator 240 is coupled with CPU250.

The data packet that DMA accelerator 240 provides CPU250 is converted to command dma and memory 230 is written, and obtains and deposit The implementing result of command dma in reservoir 230.Wherein, command dma instruction dma module 220 transmits in multiple data frames by counting According to the data to be transmitted of packet instruction.

Specifically, DMA accelerator 240 substitutes format, conveying length needed for the generation of CPU 250 meets dma module 220 etc. It is required that command dma.As one embodiment, the data-bus width of 250 interface of CPU is 32 bits, be to external equipment The data of 300 transmission 4KB, and the size of data frame is the data block size with Advanced Encryption Standard (AES) encryption.DMA mould The command dma that block 220 receives is 16 or 32 bytes, and the data block length that AES encryption is supported is 512 bytes.Therefore, DMA accelerates Device 240 generates command dma according to received multiple 32 bit datas from CPU 250, indicates 8 512 bytes in command dma DMA transfer, to meet the requirement of AES encryption.As another embodiment, the size of data frame is also possible to use cyclic redundancy Verify the size of the data block of code check.

DMA accelerator 240 substitutes the data structure that CPU 250 safeguards the command dma stored in memory 230, and DMA is ordered Write-in memory 230 is enabled, and the state of command dma updates in supervisory memory 230, and the implementing result of command dma is provided To CPU 250.

Dma module 220 safeguards DMA transfer between external equipment 300 and electronic equipment 200 by PHY module 210.Example Such as, dma module 220 obtains the command dma of instruction DMA transfer from memory 230, then according to command dma and external equipment 300 DMA transfer is initiated, and memory 230 is written into the implementing result of command dma.

Electronic equipment 200 carries out DMA biography with the external equipment (such as external equipment 300) of electronic equipment by PHY module 210 It is defeated.PHY module 210 can be the PCIe PHY module for handling PCIe underlying protocol, the FC for handling FC underlying protocol PHY module or ethernet PHY module for handling Ethernet underlying protocol.

Electronic equipment 200 is additionally coupled to memory 400.In DMA transfer, under the control of dma module 220, it will store The data of device 400 are transferred to external equipment 300, or the data that external equipment 300 is provided are stored to memory 400.As One embodiment, memory 400 is DRAM (dynamic random access memory), and compared with memory 230, memory 400 has Bigger memory capacity.

As one embodiment, DMA accelerator is equipped with the streaming interface for CPU access.Fig. 3 is to be implemented according to the application The schematic diagram of the streaming write-in interface of the DMA accelerator of example；Fig. 4 is to be read according to the streaming of the DMA accelerator of the embodiment of the present application The schematic diagram of outgoing interface.

As shown in figure 3, DMA accelerator provides the write-in interface of the streaming with accessible address and instruction streaming interface is No available status indication.CPU by available mode marker recognition go out streaming be written interface it is available when, will be related to command dma Data by specified width, which width (such as 32 bits) write-in streaming be written interface.

As an example, CPU is written interface using the streaming that DMA accelerator provides by following code segment and provides number According to.The state for the streaming write-in interface that variable stream instruction is obtained from the available mode label of streaming write-in interface, refers at it When showing that streaming write-in interface is available, command dma data (being indicated by variable CMD) is written by DMA_Write (CMD) process and is flowed The accessible address of formula interface.If command dma data CMD is larger, CPU is split as multiple 32 bits by executing program Data are supplied to streaming write-in interface.

If(stream！=full)

DMA_Write(CMD)

As shown in figure 4, reading interface is that streaming reads interface.CPU accesses streaming and reads the available mode mark that interface provides Note, when streaming, which reads interface, can be used, there are the data that can be read in instruction.Correspondingly, what CPU was provided from streaming reading interface can Access address reads data (implementing result of instruction command dma).

As an example, CPU reads interface using the streaming that DMA accelerator provides by following code segment and obtains number According to.Variable stream instruction reads the state of interface from the streaming that the available mode label that streaming reads interface obtains, and refers at it When showing that streaming reads interface non-empty, DMA life is obtained from the accessible address that streaming reads interface by DMA_Read (CMD) process The implementing result (being indicated by variable CMD_Status) of order.If the implementing result size of command dma is larger, CPU is by executing journey Sequence reads the implementing result that interface obtains command dma from streaming by reading multiple data according to specified width, which width (such as 32 bits).

If(stream！=empty)

DMA_Read(CMD_Status)

Optionally, DMA accelerator provides interruption to CPU.As the response to interruption, CPU knows that streaming reads interface and deposits Data can be being read, then CPU reads interface from streaming and reads data.

Optionally, streaming write-in interface and streaming read interface and can also mark without using available mode.CPU is directly to stream Formula, which is written the accessible address write-in data that interface provides and directly reads the accessible address that interface provides from streaming, reads number According to.

By using streaming interface, CPU writes data into stream, without be concerned about data storage address and data structure, To alleviate the load of CPU.When reading data, CPU obtains data by using streaming interface from stream, without care number According to storage address and data structure.Although streaming interface provides accessible address, which is solely Location or specified address, even if more parts of data of access, CPU need not also handle the update of address, need not also carry out memory management.

It is to be appreciated that the accessible address is also possible to the identifier of accessed stream, to see in software, pass through Operation to stream addition data, serves data to DMA accelerator or dma module.

As another embodiment, DMA accelerator is equipped with the first in, first out interface (fifo interface) for CPU access.DMA Accelerator provides FIFO to CPU and interface is written.When the fifo queue that DMA accelerator provides is less than, CPU can be to fifo queue Data are written in tail of the queue.DMA accelerator provides FIFO to CPU and reads interface.In fifo queue non-empty, CPU can be from fifo queue Team head read data.

Embodiment one

Fig. 5 is the structure chart of the DMA accelerator 240 (referring also to Fig. 2) provided according to the embodiment of the present application one.Such as Fig. 5 institute Show, DMA accelerator 240 includes command dma receiving unit 501, processing unit 502, command dma completes unit 504 and processing is single Member 503.

As shown in figure 5, command dma receiving unit 501 is respectively coupled to CPU 250 and processing unit 502, command dma is connect It receives unit 501 and receives the data packet that CPU 250 is provided.

Processing unit 502 is coupled with memory 230, and processing unit 502 obtains CPU 250 from command dma receiving unit 501 Data packet is converted to and meets the acceptable format of dma module 220 by the data packet of offer, forms command dma and memory is written 230, and safeguard 220 acceptable data structure (for example, queue) of dma module.

Processing unit 503 is coupled with memory 230, and processing unit 503 obtains command dma implementing result from memory 230. Command dma completes unit 504 and is respectively coupled to processing unit 503 and CPU 250, and command dma completes unit 504 from processing unit 503 obtain the implementing result of command dma, and provide the implementing result of command dma to CPU 250.

As one embodiment, command dma receiving unit 501 and/or command dma complete unit 504 and are equipped with buffer area, with Cache the implementing result of the data packet from CPU 250 and/or the command dma from processing unit 503.

As one embodiment, as shown in figure 5, command dma receiving unit 501, which provides streaming, is written interface, to receive CPU 250 data packets provided.Also, command dma completes the state for the command dma that 504 caching process unit 503 of unit provides, and Interface, which is read, by its streaming indicates that streaming reads that interface is available or streaming reads in interface that there are to be read to CPU 250 Data, CPU 250 read interface by the streaming that command dma completes unit 504 and complete 504 reading DMA of unit life from command dma The implementing result of order.

DMA accelerator 240 is accessed by providing streaming interface to CPU 250, CPU 250 need not maintenance memory 230 The data structure of middle storage command dma, without the format for the command dma for being concerned about the receiving of dma module 220, without to different type The specific format of command dma is adapted to, and the interface that CPU 250 accesses command dma is simplified, and is reduced CPU 250 and is handled DMA Load when order.

The multiple command dmas stored in memory 230 can be organized as queue, chained list, linear list or array etc..

As one embodiment, the multiple command dmas stored in memory 230 are organized as queue.In this embodiment, Carried out data transmission between CPU250 and DMA accelerator 240 by single stream, a queue (single team is equipped in memory 230 Column).According to the write pointer of queue memory 230, reading of the processing unit 503 according to queue is written in command dma by processing unit 502 Pointer from memory 230 obtain command dma implementing result, and according to the implementing result of command dma by CPU 250 receive and more Newly run through pointer.

As shown in figure 5, processing unit 502 safeguards 1. 2. 3. read pointer and write pointer, processing unit 502 are indicated by marking During, memory 230 is written in command dma by the address according to write pointer instruction.Next, processing unit 502 updates certainly The write pointer of body maintenance, makes write pointer be directed toward the tail of the queue of updated queue.It, will more during 4. 5. 6. being indicated by marking Memory 230 is written in write pointer after new, to record the position of tail of the queue in memory 230.Processing unit 502 is also by by marking Remember in the process monitoring memory 230 7. 8. 9. indicated and run through pointer (team's head position of instruction queue), and is single in processing First 502 internal records run through the latest value of pointer.Pointer and write pointer are run through by maintenance, processing unit 502 knows to deposit Whether the queue in reservoir 230 is less than.When queue is less than, processing unit 502 can add command dma to tail of the queue.

With continued reference to Fig. 5, dma module 220 obtains command dma from memory 230.Dma module 220 is according to memory 230 The write pointer and read pointer of middle record are determined with the presence or absence of the command dma being added in queue, and (are referred to from team's head by read pointer Show) obtain command dma.Dma module 220 is initiated DMA according to the command dma of taking-up between external equipment and electronic equipment and is passed It is defeated, and after the corresponding DMA transfer of command dma is completed and memory 230 is written in the implementing result of command dma, it updates storage Read pointer in device 230, to indicate that command dma is completed by the processing of dma module 220.

It is understood that, the queue that processing unit 502 operates indicates tail of the queue by write pointer, by running through pointer instruction team Head.And the queue operated by processing unit 503, tail of the queue is indicated by read pointer, by running through pointer instruction team's head.

Read pointer in 503 supervisory memory 230 of processing unit.It changes in response to the read pointer of memory 230, or What the read pointer of person's memory 230 and processing unit 503 recorded run through, and pointer is different, and processing unit 503 knows the DMA for having new Order is completed by dma module processing.When running through the read pointer difference of pointer and memory 230, processing unit 503 is according to certainly The pointer that runs through of body record obtains the implementing result for the command dma having been processed from memory 230, and is supplied to DMA life It enables and completes unit 504.Processing unit 503 is additionally in response to for the implementing result of command dma to be supplied to command dma completion unit 504, Update self maintained runs through pointer.

As one embodiment, processing unit 503 can will run through pointer write-in memory 230.Processing unit 502 is supervised Depending on the pointer that runs through in memory 230, and pointer will be run through as the position of queue team head.Processing unit 502 is from storage The acquisition of device 230 runs through pointer.

As another embodiment, processing unit 502 is coupled with processing unit 503, and processing unit 502 is directly single from processing Member 503 obtains and runs through pointer, will run through pointer as the position of queue team head, and need not run through from the acquisition of memory 230 At pointer.

As further embodiment, DMA accelerator 240 further includes the pointer management device (pointer management in 1 referring to Figure 1 Device 1105), pointer management device is coupled with processing unit 502 and processing unit 503 respectively, and processing unit 502 is from pointer management device Acquisition run through pointer and to pointer management device update write pointer, processing unit 503 from pointer management device obtain read pointer and Pointer is run through to the update of pointer management device.

As another embodiment, write pointer is supplied directly to dma module 220 by processing unit 502, and dma module 220 will Read pointer is supplied directly to processing unit 503.

Fig. 6 to Figure 10 is the pointer schematic diagram of the single queue provided according to the embodiment of the present application one.With the single queue Relevant pointer includes read pointer, write pointer and runs through pointer.Queue and pointer relevant to queue in memory 230 It can be accessed by DMA accelerator 240 or dma module 220.

Optionally, DMA accelerator 240 can safeguard the copy of pointer relevant with queue to dma module 220.

Fig. 6 illustrates queue and the pointer of original state.Queue includes 16 entries (number is 0-15 respectively), can be accommodated 16 command dmas.Optionally, command dma can have identical or different size.

In original state, any command dma is not written into after electronic equipment 200 is powered on or resetted, in queue, and (queue is It is empty), read pointer, write pointer and to run through pointer be 0 are directed toward the entry 0 of queue.

The processing unit 502 of DMA accelerator 240 adds command dma to queue (write pointer is 0 in Fig. 6) according to write pointer, And after queue is written in command dma, the write pointer in device 230 is updated storage.Referring to Fig. 7, entry quilt that the number of queue is 0 Command dma is written, write pointer is updated to 1 (being directed toward the queue entries that number is 1).And it read pointer and runs through pointer and is still 0。

Dma module 220 lags behind write pointer according to read pointer, and identification dequeue has been written to command dma.Dma module 220 Command dma is obtained from queue according to read pointer (being directed toward the queue entries that number is 0 in Fig. 7) and is handled.

It is to be appreciated that process of the processing unit 502 of DMA accelerator 240 to queue addition command dma, with dma module The process for obtaining command dma from queue can be concurrent, and will not influence other side mutually.

Referring to Fig. 8, the speed that dma module 220 handles command dma is slower than DMA accelerator 240 and adds order into queue Speed, the processing unit 502 of DMA accelerator 240 continue to add command dma to queue, and write pointer has been updated to 10, and (number is 0 to 9 queue entries are written into command dma).Dma module 220 has handled the queue entries that the number in queue is 0 to 3 Command dma, read pointer are updated to 4.Dma module 220 updates the DMA life in queue after completing to the processing of command dma It enables, the implementing result of command dma is recorded in command dma.The execution of command dma is written into the entry of queue for dma module 220 As a result.In fig. 8, the command dma in queue entries that number is 0 to 3 in queue is completed by the processing of dma module 220.

Optionally, in the process, when read pointer indicates implementing result of the dma module 220 to queue write-in command dma Queue entries.Dma module 220 is completed to update storage in device 230 after the implementing result that command dma is written in queue entries Read pointer.

Optionally, dma module 220 has recorded the position of command dma in the queue, and after the command dma is completed in processing Queue is written into the implementing result of command dma according to the position recorded.

The processing unit 503 of DMA accelerator 240 obtains the implementing result of command dma from the entry of queue.DMA accelerates The processing unit 503 of device 240 identifies that read pointer is ahead of and runs through pointer, knows to be written with DMA by dma module 220 in queue The state of order, and according to the implementing result for running through the acquisition command dma of entry indicated by pointer.Processing unit 503 is from team It after column entry obtains the implementing result of command dma, also updates and runs through pointer, it is made to be directed toward next entry of queue.Referring to The processing unit 503 of Fig. 8, DMA accelerator 240 obtains the DMA life for the queue entries that number is 0 and 1 according to pointer is run through The implementing result of order, and the queue entries that number is 2 are updated to point to by pointer is run through.

The processing unit 502 of DMA accelerator 240 continues to add command dma to queue.When the entry that number is 15 is written into After command dma, due to a total of 16 entries of queue, write pointer unrolls, and is directed toward the entry that number is 0 (referring to Fig. 9). Meanwhile dma module 220 continues with the command dma in queue, and command dma is executed state, queue is written, and updated reading and refer to Needle (is directed toward the entry that number is 11) in Fig. 9.The processing unit 503 of DMA accelerator 240 continues to obtain command dma from queue Implementing result, and update and run through pointer (being directed toward the entry that number is 7 in Fig. 9).

Preferably, it is also recorded in write pointer 0 to unroll, identified based on the number of unroll label or generation of unrolling Write pointer is ahead of read pointer.

The processing unit 502 of DMA accelerator 240 identifies whether queue is less than with pointer is run through according to write pointer.If reading Complete pointer be ahead of write pointer, it is meant that be filled in queue be added but be not yet removed command dma (may by The processing of dma module 220 is completed), so that the processing unit 502 of DMA accelerator 240, which suspends to queue, adds command dma, and wait The processing unit 503 of DMA accelerator 240 takes the implementing result of command dma away from queue.

The processing unit 503 of DMA accelerator 240 obtains the process and dma module of the implementing result of command dma from queue 220 can execute parallel to the process of the execution state of queue addition command dma, without interacting.

The processing unit 503 of 0, DMA accelerator 240 obtains the speed of the implementing result of command dma from queue referring to Figure 1 It is faster than the speed that dma module 220 adds the implementing result of command dma to queue, so that running through pointer gradually catch up with read pointer. In Figure 10, relative to Fig. 9, run through pointer and read pointer unroll, and run through pointer and read pointer be directed toward it is identical Position (queue entries that number is 2).In response, the processing unit 503 of DMA accelerator 240 recognizes dma module 220 The command dma implementing result of update is not yet generated, therefore the pause of processing unit 503 of DMA accelerator 240 is obtained from queue Command dma implementing result.

In the use process of the queue, the processing unit 502 and dma module 220 of DMA accelerator are one using queue To the producer and consumer, the processing unit 504 of dma module 220 and DMA accelerator be using queue another pair producer with Consumer.Single queue had both been used for DMA accelerator and has submitted command dma to dma module, is also used for dma module and mentions to DMA accelerator The implementing result for handing over command dma, reduces the demand to the memory space of memory.

Embodiment two

Figure 11 is the structure chart for the direct memory access accelerator that the embodiment of the present application two provides.As shown in figure 11, DMA Accelerator 240 includes command dma receiving unit 1101, processing unit 1102, command dma completion unit 1104 and processing unit 1103。

As shown in figure 11, command dma receiving unit 1101 is respectively coupled to CPU 250 and processing unit 1102, command dma Receiving unit 1101 receives the data packet that CPU 250 is provided.

Processing unit 1102 is coupled with memory 230, and processing unit 1102 obtains CPU from command dma receiving unit 1101 250 data packets provided, data packet is converted to and meets the acceptable format of dma module 220, is formed command dma and is written and deposits Reservoir 230, and safeguard 220 acceptable data structure (for example, queue) of dma module.

Processing unit 1103 is coupled with memory 230, and processing unit 1103 obtains command dma from memory 230 and executes knot Fruit.Command dma completes unit 1104 and is respectively coupled to processing unit 1103 and CPU 250, and command dma completes unit 1104 from The implementing result that unit 1103 obtains command dma is managed, and provides the implementing result of command dma to CPU 250.

The difference of embodiment two and embodiment one is: by multiple mutually only between DMA accelerator 240 and CPU 250 Vertical stream carries out data transmission, and queue corresponding with each stream is equipped in memory 230.Dma module independent process CPU 250 exists The command dma provided in each stream.

As an example, command dma receiving unit 1101 is equipped with port (single-port, as interface is written in streaming).DMA The streaming write-in interface of order receiving unit 1101 is that each stream provides available mode and marks, and CPU 250 can independently or jointly Obtain the available mode label of each stream.The port according to stream available mode and receive the data packet of CPU 250, in data packet Mark the stream to be accessed.Command dma receiving unit 1101 is according to stream belonging to the marker recognition command dma in data packet.Processing Unit 1102 is according to stream belonging to command dma, and (i.e. command dma is in memory 230 for the pointer of acquisition queue corresponding with the stream Storage address), and corresponding with stream queue is written into command dma.

Processing unit 1103 monitors the pointer of the corresponding queue of each stream.Occurs the command dma that processing is completed in the queue Execution state after, processing unit 1103 obtain command dma implementing result, and by command dma complete unit 1104 offer To CPU 250.Specifically, the streaming that command dma completes unit 1104 reads interface and provides available mode label for each stream, CPU 250 can independently or jointly obtain the available mode label of each stream, and read interface by streaming and obtain from each stream The implementing result of command dma.

DMA accelerator 240 ensures stream belonging to the command dma of the submission of CPU 250 and the command dma obtained of CPU 250 Stream belonging to implementing result is identical stream.Even if CPU 250 is simultaneously to multiple streams submission command dma, but CPU 250 is from each The implementing result for the command dma that a stream obtains comes across in stream identical with the command dma that CPU 250 is submitted.For example, DMA adds Fast device 240 provides 4 streams (S0, S1, S2 and S3), and CPU 250 has submitted command dma C1 and C2 to stream S1, and Xiang Liu S2 has submitted Command dma C3 and C4, and CPU 250 correspondingly completes to get command dma C1 in the stream S1 that unit 1104 provides from command dma With the implementing result of C2, and complete to get the execution knot of command dma C3 and C4 in the stream S2 that unit 1104 provides from command dma Fruit.

Optionally, in the same stream, the implementing result of command dma is sequentially presented to CPU by what command dma was submitted to stream 250.Optionally as well, in the same stream, the sequence that the implementing result of command dma is supplied to CPU 250 can be out-of-order.

As another specific embodiment, command dma receiving unit 1101 is equipped with multiple ports and (such as streaming interface or first enters First outgoing interface), the quantity of port and the quantity of stream are identical, and port and stream correspond.Command dma receiving unit 1101 by with Flow the data packet that one-to-one port receives CPU 250.Command dma receiving unit 1101 is known according to the port of received data packet Stream belonging to other command dma.Processing unit 1102 obtains the pointer of queue corresponding with the stream according to stream belonging to command dma (i.e. storage address of the command dma in memory 230), and queue corresponding with the stream is written into command dma.Command dma is complete Command dma implementing result is supplied to CPU from port corresponding with the stream according to stream belonging to command dma at unit 1104 250。

As another embodiment, data packet indicator identifiers (sID, also referred to as flow identifier), flow identifier is indicated Stream belonging to data packet.DMA accelerator 240 determines storage address of the command dma in memory 230 according to identifier.

As one embodiment, DMA accelerator 240 further includes pointer management device 1105.Pointer management device 1105 respectively with Processing unit 1102 and processing unit 1103 couple, read pointer, write pointer and reading for each queue in record storage 230 Complete pointer (for example, the multiple pointers for being used for the multiple pointers for the stream that flow identifier is S0, the stream for being S1 for flow identifier). Processing unit 1102 updates the write pointer of corresponding with each stream queue to pointer management device 1105, and processing unit 1103 is from pointer Manager 1105 is obtained with the read pointer of the corresponding queue of each stream and corresponding with each stream to the update of pointer management device 1105 Queue runs through pointer.Pointer management device is used for processing unit for being managed to multiple queues in memory 1102 and processing unit 1103 exchange pointer.Processing unit 1102 and processing unit 1103 are according to flow identifier from pointer management device 1105 obtain or the corresponding pointer of cocurrent flow are written to pointer management device 1105.

Optionally, memory 230 provides memory space for the corresponding queue of each stream and pointer corresponding with queue.Figure 11 In illustrate read pointer and write pointer that memory 230 accommodates each of two queues and two queues.Stream and memory Queue in 230 corresponds.

Embodiment three

Figure 12 is the flow chart for the command dma processing method that the embodiment of the present application three provides.As shown in figure 12, DMA accelerates Device includes the following steps: the processing method of command dma

Step 1201: receiving the data packet from CPU.

Step 1202: data packet being converted into command dma, and memory is written.

Step 1203: being updated in response to the implementing result of the command dma in memory, obtain the command dma being updated Implementing result.

Step 1204: the implementing result of command dma is supplied to CPU.

As one embodiment, carried out data transmission between CPU and DMA accelerator by streaming interface, DMA accelerator is Each stream provides status indication.

In step 1201, DMA accelerator provides the status indication of streaming interface, and whether which indicates streaming interface It can receive data.If CPU identifies the status indication of streaming interface as available mode label, CPU is sent to streaming interface Data packet.

In step 1204, DMA accelerator provides the status indication of streaming interface, and whether which indicates streaming interface The data exported in the presence of needs.If CPU identifies the status indication of streaming interface as available mode label, CPU connects from streaming Mouth read data packet.

As another embodiment, data are carried out by first in, first out interface (fifo interface) between CPU and DMA accelerator Transmission.

In step 1201, DMA accelerator provides the state of first in, first out interface.If CPU identifies First Input First Output not Full, then CPU sends data packet to first in, first out interface.

In step 1204, DMA accelerator provides the state of first in, first out interface.If CPU identifies First Input First Output and is Non-empty, then CPU is from first in, first out interface read data packet.

Optionally, the multiple command dmas stored in memory are organized as queue.By write pointer, read pointer and run through Queue is safeguarded at pointer.Write pointer is directed toward the tail of the queue that the queue of command dma is stored in memory, runs through pointer and is directed toward storage Team's head of the queue of command dma is stored in device.

DMA accelerator foundation runs through pointer and lags behind write pointer, determines in memory and stores the queue of command dma not It is full.When queue only in memory is less than, according to write pointer memory is written in command dma by DMA accelerator, is then updated and is write Pointer.

Dma module obtains command dma from the queue in memory according to read pointer and is handled.In response to command dma It is completed, memory is written in the implementing result of command dma by dma module, and updates storage the read pointer in device.

In response to read pointer from run through that pointer is different, DMA accelerator obtains the implementing result of command dma from memory. It is ahead of in response to read pointer and runs through pointer, DMA accelerator foundation runs through the execution that pointer obtains command dma from memory As a result, and update run through pointer.

Optionally, DMA accelerator can will run through pointer write-in memory, and run through finger in supervisory memory Needle, and pointer will be run through as the position of queue team head.

As one embodiment, is carried out data transmission between DMA accelerator and CPU by multiple mutually independent streams, deposited It is equipped in reservoir and each one-to-one queue of stream.The command dma that dma module independent process CPU is provided in each stream. DMA accelerator provides status indication for each stream.

Figure 13 is that the CPU of the embodiment of the present application executes direct memory access operation by direct memory access accelerator Flow chart.As shown in figure 13, CPU executes dma operation by DMA accelerator and includes the following steps:

Step 1310:CPU obtains available stream from DMA accelerator.For example, the streaming that CPU access DMA accelerator provides The whether available status indication of interface, to obtain available stream.Whether the corresponding stream of status indication instruction can be written into data Or read data.

If CPU will provide command dma to DMA accelerator, then follow the steps 1320: to available for command dma to be written Stream send data packet.

If CPU will obtain the implementing result of command dma from DMA accelerator, 1330 are thened follow the steps: from available for reading The stream of data obtains the implementing result of command dma out.

(1) the DMA accelerator substitution CPU of the application is interacted with memory, and substitution CPU generation meets dma module institute The command dma of the requirements such as format, the conveying length needed, and the data structure of the command dma in CPU maintenance memory is substituted, it will Memory is written in command dma, and the state of command dma updates in supervisory memory, and finally by the implementing result of command dma It is supplied to CPU, significantly reduces the load of CPU, accelerates the processing speed of command dma.

(2) for the application by using streaming interface, CPU writes data into stream, without be concerned about data storage address and Data structure, the data organization that DMA accelerator provides CPU is command dma, to alleviate the load of CPU；Reading data When, the execution structure organization of command dma is data flow by DMA accelerator, and CPU obtains number by using streaming interface from stream According to without the storage address and data structure for being concerned about data；Although streaming interface provides accessible address, this be may have access to Address is single address or specified address, and CPU need not handle the update of address, need not also carry out memory management.

The above, the only specific embodiment of the application, but the protection scope of the application is not limited thereto, it is any Those familiar with the art within the technical scope of the present application, can easily think of the change or the replacement, and should all contain Lid is within the scope of protection of this application.Therefore, the protection scope of the application should be based on the protection scope of the described claims.

Claims

1. a kind of electronic equipment, which is characterized in that including physical layer block, direct memory access module, memory, directly deposit Reservoir accesses accelerator and central processing unit, and the physical layer block is coupled with the direct memory access module, described Memory is coupled to the direct memory access module and the direct memory access accelerator, and the direct memory is visited Ask that accelerator is coupled with the central processing unit；

Wherein, the data packet that the central processing unit provides is converted to direct memory by the direct memory access accelerator Simultaneously the memory is written in visit order；And obtain the implementing result of the direct memory access order in the memory；

The direct memory access module is directly deposited according to the direct memory access order initiation obtained from the memory Reservoir access transport, and the memory is written into the implementing result of direct memory access order；

The electronic equipment is by the physical layer block with the external device communication of the electronic equipment；

The direct memory access accelerator includes direct memory access order receiving unit and first processing units, and Unit and the second processing unit are completed in direct memory access order；Wherein:

Described the second processing unit is coupled with the memory, and described the second processing unit is obtained from the memory and directly stored Device visit order implementing result；And

The direct memory access order completion unit is coupled to described the second processing unit and the central processing unit, described The implementing result that unit obtains direct memory access order from described the second processing unit is completed in direct memory access order, And the implementing result of direct memory access order is provided to the central processing unit；

The direct memory access accelerator further includes pointer management device, the pointer management device and the first processing units It is coupled with described the second processing unit, the first processing units are at pointer management device acquisition write pointer, described second Reason unit obtains read pointer from the pointer management device and runs through pointer to pointer management device update.

2. electronic equipment according to claim 1, which is characterized in that the direct memory access accelerator is equipped with and is used for The streaming write-in interface and streaming of the central processing unit access read interface.

3. electronic equipment described in any one of -2 according to claim 1, which is characterized in that the direct memory access order Receiving unit is coupled to the central processing unit and the first processing units, the direct memory access order receiving unit Receive the data packet that the central processing unit provides；And

The first processing units are coupled with the memory, and the first processing units are from the direct memory access order Receiving unit obtains the data packet that the central processing unit provides, and the data packet is converted to direct memory access order, And the memory is written.

4. electronic equipment described in any one of -2 according to claim 1, which is characterized in that the memory stores multiple straight It connects memory access command and is organized as queue, the first processing units are directly deposited according to the write pointer of the queue by described The memory is written in reservoir visit order.

5. electronic equipment according to claim 4, which is characterized in that reading of the described the second processing unit according to the queue Pointer obtains the implementing result of the direct memory access order from the memory.

6. a kind of direct memory access command handling method, which comprises the steps of:

Received data packet；

The data packet is converted into direct memory access order, and memory is written；

Be updated in response to the implementing result of the direct memory access order in the memory, obtain be updated directly deposit The implementing result of reservoir visit order；

The memory is written into direct memory access order according to write pointer；

The write pointer is updated, and the memory is written into updated write pointer；

Acquisition runs through pointer；

Wherein, the write pointer is directed toward the tail of the queue that the queue of direct memory access order is stored in the memory, the reading It completes pointer and is directed toward the team's head for storing the queue of direct memory access order in the memory；

Wherein, pointer is run through according to described in and lag behind the write pointer, determine that direct memory is stored in the memory visits Ask that the queue of order is less than；When queue only in the memory is less than, it will be deposited described in direct memory access order write-in Reservoir.

7. direct memory access command handling method according to claim 6 characterized by comprising

The status indication of streaming interface is provided；

If the status indication of the streaming interface is available mode label, from the streaming interface data packet or to the stream The implementing result of formula interface write-in direct memory access order.