CN109144900B - Implementation method of block conversion layer in SSD - Google Patents
Implementation method of block conversion layer in SSD Download PDFInfo
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- CN109144900B CN109144900B CN201811027966.9A CN201811027966A CN109144900B CN 109144900 B CN109144900 B CN 109144900B CN 201811027966 A CN201811027966 A CN 201811027966A CN 109144900 B CN109144900 B CN 109144900B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a method for realizing a block conversion layer in an SSD. The method specifically comprises the following steps: (1) establishing an initial bad block information table BBIT; (2) And establishing a block conversion layer (BTL), wherein a BTL table is a conversion table from a logic block to a physical block, the address generation of the logic block comprises a plurality of types, and the substitution mode of the physical block comprises a plurality of types. The invention has the beneficial effects that: after the Block conversion layer BTL table is established, when other engines of the controller inquire the information of the Block, the other engines directly apply for the Block conversion layer BTL, the Block conversion layer BTL transmits the Block information which shields the bad Block information to each process, and therefore the other processes do not need to process the abnormal condition of the bad Block, and the Block conversion layer (BTL) is introduced to simplify the design of the SSD.
Description
Technical Field
The invention relates to the related technical field of SSD, in particular to a method for realizing a block conversion layer in SSD.
Background
In an existing SSD (Solid State Disk) controller, a count called Flash Transport Layer (FTL) is widely used to solve the correspondence between a logical LBA number and an actual physical address, and the reason for introducing the FTL is that a nand flash error may cause a change of the actual address. However, the granularity on which the FTL is based is that of LBA for management, which is typically 512Byte or 4Kbyte. But the management granularity is not consistent with that of an actual nand flash error.
At the time of actual NAND flash use, erasing is performed in units of physical blocks, and at the time of multi-plane operation, a plurality of blocks are erased together, but the states after erasing are separated for each plane. Due to the existence of the bad block, the influence of the bad block needs to be considered when the SSD controller processes, so that each processing flow of the SSD is relatively complicated.
Disclosure of Invention
The present invention provides a method for simplifying the implementation of a block translation layer in an SSD, in order to overcome the above-mentioned disadvantages in the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
a method for realizing a block conversion layer in an SSD specifically comprises the following steps:
(1) Establishing an initial bad block information table BBIT;
(2) And establishing a block conversion layer BTL, wherein a table of the block conversion layer BTL is a conversion table from a logic block to a physical block, the address generation of the logic block comprises a plurality of types, and the substitution mode of the physical block comprises a plurality of types.
The block conversion layer BTL is used to convert a physical block (or group of physical blocks) visible by the conventional scheme into a logical block — LRB, which may be a single physical block, or a plurality of physical blocks. Compared with the traditional physical block (or group of the physical block), the converted logical block LRB has no influence of bad blocks, namely all the bad blocks are replaced or shielded by the conversion layer. The block translation layer BTL building process refers to a mapping process of building logical blocks and physical blocks. When the NAND flash is manufactured, a certain proportion of original factory bad blocks exist, and meanwhile, in the using process of the flash, new bad blocks can be generated due to various reasons such as erasing, programming and the like. This information needs to be maintained in the Bad Block Information Table (BBIT), and the block translation layer BTL needs to establish a mapping relationship according to BBIT. After the Block conversion layer BTL table is established, when other engines of the controller inquire the information of the Block, the other engines directly apply for the Block conversion layer BTL, the Block conversion layer BTL transmits the Block information which shields the bad Block information to each process, and therefore the other processes do not need to process the abnormal condition of the bad Block, and the Block conversion layer (BTL) is introduced to simplify the design of the SSD.
Preferably, in step (2), the block conversion layer BTL table is a conversion table from logical block to physical block, the number of entries of the table entry is determined by the number of replacements to be supported, and the maximum value is LRB x CH x Die x PL; wherein: the address generation of the logical block includes three types, LRB x CH x Die x PL, LRB x CH, and LRB x CH x Die.
Preferably, the content of the block conversion layer BTL table provides information of a physical block that needs to be replaced, and the replacement manner of the physical block includes five types, namely CH x Die x BLK, CH x Die x PL x BLK, CH x BLK, and PL x BLK.
Preferably, as a special case of the replacement relationship, an entry for replacing with invalid is introduced, and the entry is used for representing that the logical block can not be replaced with a good block, namely can not be replaced, or is still an invalid block after replacement.
Preferably, in the step (2), when the address generation type of the logical block is LRB x CH x Die x PL and the replacement type of the physical block is BLK, all bad blocks in the logical block LRB obtained by the block conversion layer BTL can only be replaced by redundant blocks of the current PL, and a single PL is replaced when replacing.
Preferably, in step (2), when the address generation type of the logical block is LRB x CH x Die and the replacement type of the physical block is CH x Die x BLK, all bad blocks in the logical block LRB obtained by the block conversion layer BTL are replaced by a plurality of PLs of different Die in different channels, and the plurality of PLs may be replaced at the same time during replacement.
Preferably, in step (2), when the address generation type of the logical block is LRB x CH x Die and the replacement type of the physical block is BLK, each logical block in the logical block LRB obtained by the block conversion layer BTL is replaced with a new block, and different CH is bound to different logical blocks by setting invalid block.
The beneficial effects of the invention are: after the Block conversion layer BTL table is established, when other engines of the controller inquire the information of the Block, the other engines directly apply for the Block conversion layer BTL, the Block conversion layer BTL transmits the Block information which shields the bad Block information to each process, and therefore the other processes do not need to process the abnormal condition of the bad Block, and the Block conversion layer (BTL) is introduced to simplify the design of the SSD.
Drawings
FIG. 1 is a schematic diagram of the structure of an SSD disk;
FIG. 2 is a schematic diagram of the structure of a block translation layer BTL table;
FIG. 3 is a schematic diagram of the structure of an invalid entry;
fig. 4, 5 and 6 are schematic views of different alternative modes of the invention.
Detailed Description
The invention is further described with reference to the following figures and detailed description.
In the embodiment shown in fig. 1, a method for implementing a block translation layer in an SSD specifically includes the following steps:
(1) Establishing an initial bad block information table BBIT;
(2) And establishing a block conversion layer BTL, wherein a table of the block conversion layer BTL is a conversion table from a logic block to a physical block, the address generation of the logic block comprises a plurality of types, and the substitution mode of the physical block comprises a plurality of types.
The block conversion layer BTL table is a conversion table from logical block to physical block, the number of entries of the table entry is determined by the number of replacements to be supported, and the maximum value is LRB x CH x Die x PL, such as: 1024 logic blocks LRB are required to be supported, each LRB is composed of 16 CH,4 Die,2 PL, and the number of entries of BTL is 1024 × 16 × 4 × 2; in actual engineering, all PLs (or Die) may be replaced together for simplicity of design, and the number of corresponding entries may be reduced.
As shown in FIG. 2, the address generation of a logical block includes three types, LRB x CH x Die x PL, LRB x CH x Die. The content of the BTL table provides information of the physical block that needs to be replaced, and the replacement mode of the physical block comprises five types, namely CH x Die x BLK, CH x Die x PL x BLK, CH x BLK and PL x BLK. The contents of the BTL table provide information on the physical block that needs to be replaced, and we can constrain whether this replacement can only be done inside the same PL or on any CH/Die/PL. This alternative relationship has a large impact on the bandwidth fluctuation and performance and complexity of the controller.
As a specific example of the replacement relationship, an entry replaced with invalid is introduced, as shown in fig. 3, and this entry is used to characterize that the logical block may not be replaced with a good block, i.e., cannot be replaced, or remains as an invalid block after replacement.
As shown in fig. 4, when the address generation type of the logical block is LRB x CH x Die x PL and the replacement type of the physical block is BLK, all bad blocks in the logical block LRB obtained by the block conversion layer BTL can only be replaced by redundant blocks of the current PL, and a single PL is replaced during replacement. In the figure, the internal part of LRB2 has an error in physical block2 on CH0Die1PL1, and we replace it with physical block1026 under the same PL. Since the replacement only occurs within the same PL, this scheme has the following features: blocks after replacement can also be concurrent with multiple PLs, so the write bandwidth is higher. However, because of the constraint of the replacement relationship, when the bad blocks of the current PL are more, the current PL cannot be replaced by the valid blocks of other PLs, which results in a decrease in the capacity actually used and affects the OP size.
As shown in fig. 5, when the address generation type of the logical block is LRB x CH x Die and the replacement type of the physical block is CH x Die x BLK, all the bad blocks in the logical block LRB obtained by the block conversion layer BTL are replaced by multiple PLs of different Die in different channels, and multiple PLs may be replaced at the same time during replacement. In the figure, physical block2 of the interior of LRB 3 on CH0Die1PL1 is in error, and PL0 and PL1 are replaced simultaneously by using CH1Die0block 1026. Since the replacement can take place between different die, this solution has the following characteristics: blocks after replacement can also be concurrent with multiple PLs, so the write bandwidth is higher. And we do not restrict the replacement within the same PL, so when bad blocks of the current PL are more, the effective blocks of other planes can be used for replacement, and redundant block resources can be used to the maximum extent.
As shown in fig. 6, when the address generation type of the logical block is LRB x CH x Die and the replacement type of the physical block is BLK, each logical block in the logical block LRB obtained by the block conversion layer BTL is replaced with a new block, and different CH is bound to different logical blocks by setting an invalid block. The corresponding contents of the BTL table entry of the block translation layer are as follows:
in this case 'FFFF' is used to mark that Block as invalid. In this example, CH 0-3 belongs to LRB A; and CH 4-7 belongs to LRB. Thereby enabling the division of different CHs into different logical blocks LRB.
The block translation layer is used to convert the physical block (or group of physical blocks) visible by the conventional scheme into a logical block-LRB, which may be a single physical block, or multiple physical blocks. Compared with the traditional physical block (or group of the physical block), the converted logical block LRB has no influence of bad blocks, namely all the bad blocks are replaced or shielded by the conversion layer. The block translation layer BTL building process refers to a mapping process that builds logical blocks and physical blocks. When the NAND flash is manufactured, a certain proportion of original factory bad blocks exist, and meanwhile, in the using process of the flash, new bad blocks can be generated due to various reasons such as erasing, programming and the like. This information needs to be maintained in the Bad Block Information Table (BBIT), and the block translation layer BTL needs to establish a mapping relationship according to BBIT. After the Block conversion layer BTL table is established, when other engines of the controller inquire the information of the Block, the other engines directly apply for the Block conversion layer BTL, the Block conversion layer BTL transmits the Block information which shields the bad Block information to each process, and therefore the other processes do not need to process the abnormal condition of the bad Block, and the design of the SSD is simplified by introducing the Block conversion layer (BTL). By the design of a block conversion layer BTL table, different logic block division and bad block replacement modes are realized to support different binding relations, so that different bandwidth, RAID (redundant array of independent disks) capability and other characteristics are obtained.
Claims (6)
1. A method for realizing a block conversion layer in an SSD is characterized by comprising the following steps:
(1) Establishing an initial bad block information table BBIT;
(2) Establishing a block conversion layer BTL, wherein a table of the block conversion layer BTL is a conversion table from a logic block to a physical block, the address generation of the logic block comprises a plurality of types, and the substitution mode of the physical block comprises a plurality of types; the block conversion layer BTL table is a conversion table from logic block to physical block, the number of entries of the table entry of the conversion table is determined by the number of required support replacements, and the maximum value of the number of entries of the table entry of the conversion table is LRB x CH x Die x PL; wherein: LRB refers to a logical block; CH, channel, refers to a Channel; die, or LUN, refers to a logical unit; PL is Plane, meaning flour; the address generation of the logical block comprises three types, namely LRB x CH x Die x PL, LRB x CH and LRB x CH x Die; wherein: LRB xcCH xcDie xPL refers to an address generated by LRB, CH, die, PL, LRB xcCH refers to an address generated by LRB, CH, LRB xcCH xDie refers to an address generated by LRB, CH, die.
2. The method for implementing the block conversion layer in the SSD as recited in claim 1, wherein the contents of the block conversion layer BTL table provide information of a physical block to be replaced, and the replacement manner of the physical block includes five types, namely CH x Die x BLK, CH x Die x PL x BLK, CH x BLK, PL x BLK; wherein: BLK refers to physical block; CH x Die x BLK is information composed of CH, die, and BLK, CH x Die x PL x BLK is information composed of CH, die, PL, and BLK, BLK is information composed of BLK, CH x BLK is information composed of CH, and BLK, and PL x BLK is information composed of PL and BLK.
3. A method as claimed in claim 1 or 2, wherein as a special case of replacement, an entry is introduced that is replaced with invalid and is used to indicate that the logical block can not be replaced with a good block, i.e. cannot be replaced, or is still an invalid block after replacement.
4. The method as claimed in claim 2, wherein in step (2), when the address generation type of the logical block is LRB x CH x Die x PL and the replacement type of the physical block is BLK, all bad blocks in the logical block LRB obtained by the block conversion layer BTL can only be replaced by redundant blocks of the current PL, and when replacing, a single PL is replaced.
5. The method according to claim 2, wherein in step (2), when the address generation type of the logical block is LRB x CH x Die and the replacement type of the physical block is CH x Die x BLK, all bad blocks in the logical block LRB obtained by the block conversion layer BTL are replaced by a plurality of PLs of different Die of different channels, and when the replacement is performed, the plurality of PLs can be replaced at the same time.
6. The method according to claim 2, wherein in step (2), when the address generation type of the logical block is LRB x CH x Die and the replacement type of the physical block is BLK, each logical block in the logical block LRB obtained by the block translation layer BTL is replaced with a new block, and different CH is bound to different logical blocks by setting invalid block.
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| KR101086876B1 (en) * | 2009-09-30 | 2011-11-25 | 주식회사 하이닉스반도체 | Solid State Storage System For Controlling of Reserved Area Flexibly and Method of Controlling the Same |
| US9983829B2 (en) * | 2016-01-13 | 2018-05-29 | Sandisk Technologies Llc | Physical addressing schemes for non-volatile memory systems employing multi-die interleave schemes |
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