CN109120140A - bias suppressing method and device - Google Patents

bias suppressing method and device Download PDF

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Publication number
CN109120140A
CN109120140A CN201710491124.8A CN201710491124A CN109120140A CN 109120140 A CN109120140 A CN 109120140A CN 201710491124 A CN201710491124 A CN 201710491124A CN 109120140 A CN109120140 A CN 109120140A
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China
Prior art keywords
compensation amount
bridge circuit
converter
side full
transformer
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Granted
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CN201710491124.8A
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Chinese (zh)
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CN109120140B (en
Inventor
胡永辉
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ZTE Corp
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ZTE Corp
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Priority to CN201710491124.8A priority Critical patent/CN109120140B/en
Priority to PCT/CN2018/091429 priority patent/WO2018233555A1/en
Publication of CN109120140A publication Critical patent/CN109120140A/en
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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The present invention provides a kind of bias suppressing methods and device, this method to include；The voltage value U2 of the resistance R2 of full-bridge circuit electric current when in detection converter for detecting the voltage value U1 of the secondary resistance R1 in full-bridge circuit electric current and for detecting secondary；According to U1 and U2, the bias of the transformer in converter is inhibited.Through the invention, it solves and eliminates transformer bias phenomenon mode in circuit by the way that capacitance is added in the circuit of variator in the related technology, big, the at high cost problem of the volume of the complexity height and converter that lead to circuit, reach reduction circuit complexity, reduces converter volume and cost effectiveness.

Description

Bias suppression method and device
Technical Field
The invention relates to the technical field of power electronics, in particular to a magnetic bias suppression method and device.
Background
In the field of power electronics, particularly dc/dc converters, the isolated BUCK-BOOST circuit shown in fig. 1 can maintain higher efficiency in a wider input voltage range than a BUCK + full bridge circuit or a BOOST + full bridge circuit. However, in practical applications, due to the difference in switching speed of the switching tubes, the difference in delay of the driving signals, the difference in pulse width of the driving signals, and the like, the magnetic bias phenomenon of the transformer in the circuit shown in fig. 1 occurs after long-time operation, as shown in fig. 2.
At present, a common technique for eliminating the bias of the transformer is to add a dc blocking capacitor in the topology of the circuit, as shown in fig. 3, to connect the dc blocking capacitor in series with the transformer winding to block the dc component. Although this solution is simple, the addition of the blocking capacitor increases the complexity of the circuit, and the selection of the blocking capacitor in a high-current situation is very difficult, and at the same time, the size and cost of the converter are increased.
Therefore, in the related art, the dc blocking capacitor is added to the circuit of the converter to eliminate the bias phenomenon of the transformer in the circuit, which results in an increase in complexity of the circuit, an increase in size of the converter, and an increase in cost.
Disclosure of Invention
The embodiment of the invention provides a magnetic bias suppression method and device, which are used for at least solving the problems of high circuit complexity, large size and high cost of a converter caused by a mode of eliminating a magnetic bias phenomenon of a transformer in a circuit by adding a blocking capacitor in the circuit of a converter in the related art.
According to an embodiment of the present invention, there is provided a bias suppression method including: detecting the voltage value U1 of a resistor R1 for detecting the current of the secondary side full bridge circuit and the voltage value U2 of a resistor R2 for detecting the current of the secondary side full bridge circuit in the converter; according to the U1 and the U2, magnetic biasing of a transformer in the converter is restrained.
Optionally, according to the U1 and the U2, the suppressing magnetic biasing of a transformer in the converter comprises: according to the U1 and the U2, the compensation amount required by a duty ratio signal of each switching tube of a main side full bridge circuit in the converter is obtained; and inhibiting the magnetic bias of the transformer in the converter in a mode of superposing the acquired compensation quantity of each switching tube and the corresponding duty ratio information of each switching tube.
Optionally, according to the U1 and the U2, the compensation amount required for obtaining the duty cycle signal of each switching tube of the main-side full-bridge circuit in the converter includes: acquiring a voltage difference value between the U1 and the U2; acquiring a first compensation quantity according to the voltage difference value; and acquiring the compensation amount required by the duty ratio signal of each switching tube of the main-side full-bridge circuit in the converter in a mode of judging the first compensation amount.
Optionally, obtaining the first compensation amount according to the voltage difference includes: acquiring the first compensation quantity in a mode of filtering the voltage difference value; or, the first compensation amount is obtained by performing amplitude limiting processing on the voltage difference.
Optionally, obtaining the compensation amount required by the duty cycle signal of each switching tube of the main-side full-bridge circuit in the converter by judging the first compensation amount includes: when the first compensation amount is larger than zero, the compensation amount of the transformer positive excitation direction switching tubes Q1 and Q4 of the primary side full-bridge circuit is the first compensation amount, and the compensation amount of the transformer negative excitation direction switching tubes Q2 and Q3 of the primary side full-bridge circuit is zero; when the first compensation amount is less than zero, the compensation amount of the switching tubes Q1 and Q4 of the main-side full-bridge circuit is zero, and the compensation amount of the switching tubes Q2 and Q3 of the main-side full-bridge circuit is the absolute value of the first compensation amount.
According to another embodiment of the present invention, there is provided a bias suppressing device including: the detection module is used for detecting the voltage value U1 of a resistor R1 used for detecting the current of the secondary side full bridge circuit and the voltage value U2 of a resistor R2 used for detecting the current of the secondary side full bridge circuit in the converter; and the suppression module is used for suppressing the magnetic bias of a transformer in the converter according to the U1 and the U2.
Optionally, the suppression module is further configured to obtain, according to the U1 and the U2, an amount of compensation required for a duty cycle signal of each switching tube of a main-side full-bridge circuit in the converter; and inhibiting the magnetic bias of a transformer in the converter in a mode of superposing the acquired compensation quantity of each switching tube and the corresponding duty ratio information of each switching tube.
Optionally, the suppressing module is further configured to obtain a voltage difference between the U1 and the U2; acquiring a first compensation quantity according to the voltage difference value; and acquiring the compensation amount required by the duty ratio signal of each switching tube of the main-side full-bridge circuit in the converter in a mode of judging the first compensation amount.
Optionally, the suppression module is further configured to obtain the first compensation amount by performing filtering processing on the voltage difference; or, the first compensation amount is obtained by performing amplitude limiting processing on the voltage difference.
Optionally, the suppression module is further configured to, when the first compensation amount is greater than zero, set the compensation amount of the transformer positive excitation direction switching tubes Q1, Q4 of the primary-side full-bridge circuit to be the first compensation amount, and set the compensation amount of the transformer negative excitation direction switching tubes Q2, Q3 of the primary-side full-bridge circuit to be zero; when the first compensation amount is less than zero, the compensation amount of the switching tubes Q1 and Q4 of the main-side full-bridge circuit is zero, and the compensation amount of the switching tubes Q2 and Q3 of the main-side full-bridge circuit is the absolute value of the first compensation amount.
According to yet another embodiment of the present invention, there is also provided a storage medium including a stored program, wherein the program performs any one of the above methods when executed.
According to yet another embodiment of the present invention, there is also provided a processor for executing a program, wherein the program executes to perform the method of any one of the above.
By the invention, the voltage value U1 of a resistor R1 for detecting the current of the secondary side full bridge circuit and the voltage value U2 of a resistor R2 for detecting the current of the secondary side full bridge circuit in the converter are detected; according to U1 and U2, the magnetic biasing of the transformer in the converter is suppressed. Because the magnetic bias of the transformer in the converter can be inhibited according to the voltage value U1 of the resistor R1 for detecting the current of the secondary side full bridge circuit in the original circuit of the transformer and the voltage value U2 of the resistor R2 for detecting the current of the secondary side full bridge circuit in the original circuit of the transformer, the magnetic bias of the transformer in the converter can be effectively inhibited without adding any accessory element, and therefore, the problems of high circuit complexity, large converter volume and high cost caused by the mode that the magnetic bias phenomenon of the transformer in the circuit is eliminated by adding the direct current blocking capacitor in the circuit of the converter in the related technology can be solved, and the effects of reducing the circuit complexity and reducing the converter volume and cost are achieved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a schematic diagram of an isolated BUCK-BOOST circuit in the related art;
FIG. 2a is a schematic diagram illustrating the whole process of biasing the magnetic flux of a transformer in the related art;
FIG. 2b is a diagram illustrating a gradual change of an initial bias of a transformer exciting current in the related art;
FIG. 2c is a schematic diagram illustrating the magnetic biasing stabilization of a transformer according to the related art;
FIG. 3 is a schematic diagram of a related art isolated BUCK-BOOST circuit with an added DC blocking capacitor;
FIG. 4a is a schematic waveform diagram of the voltage U1 of the detection resistor R1 and the voltage U2 of the resistor R2 when the transformer is unbiased in the related art;
FIG. 4b is a schematic diagram showing waveforms of a voltage U1 of the detection resistor R1 and a voltage U2 of the resistor R2 when the transformer is biased in the related art;
fig. 5 is a block diagram of a hardware structure of a mobile terminal according to a bias suppression method in an embodiment of the present invention;
FIG. 6 is a flow chart of a bias suppression method according to an embodiment of the present invention;
FIG. 7 is a flow chart illustrating a method for suppressing magnetic bias of an isolated BUCK-BOOST circuit according to an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of a magnetic bias suppression device of an isolated BUCK-BOOST circuit according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of the connection of the isolated BUCK-BOOST circuit bias suppression device and the BUCK-BOOST circuit according to the embodiment of the invention;
FIG. 10 is a schematic diagram of an isolated BUCK-BOOST circuit transformer excitation current according to an embodiment of the invention;
fig. 11 is a block diagram of a structure of a magnetic bias suppression device according to an embodiment of the present invention.
Detailed Description
The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
FIG. 1 is a schematic diagram of an isolated BUCK-BOOST circuit in the related art. As shown in fig. 1, the detailed circuit embodiment is that Vin is an input voltage source, Q1, Q2, Q3, Q4, Q5 and Q6 are MOSFETs of 100V, L1 is 3uH, the turn ratio of the transformer T1 is 4:1, SR1, SR2, SR3 and SR4 are 25V synchronous rectifiers, the current sampling resistors R1 and R2 are 0.5mR, and Vout is an output voltage. In practical applications, due to differences in switching speeds of the switching tubes Q1, Q2, Q3, and Q4, differences in driving signal delays, differences in driving signal pulse widths, and the like, the transformer T1 in the circuit shown in fig. 1 is biased after long-time operation. When the switching speed difference of the switching tubes Q1, Q2, Q3 and Q4 is 80ns, the exciting current of the transformer T1 is as shown in fig. 2a, 2b and 2 c. Referring to fig. 2a, 2b, 2c, the transformer excitation current is biased unidirectionally. Fig. 2A is a schematic diagram of the whole process of magnetic biasing of a transformer in the related art, and as shown in fig. 2A, the exciting current of the transformer gradually rises from 0 to a maximum amplitude 12A. Fig. 2b is a schematic diagram of a gradual change process of initial bias of transformer exciting current in the related art, wherein the transformer exciting current is biased in a single direction from 0. Fig. 2c is a schematic diagram illustrating the stability of the bias of the transformer in the related art, and as shown in fig. 2c, the bias of the transformer is finally stabilized in the swing of the transformer excitation current at 10-12A.
FIG. 3 is a schematic diagram of a related art isolated BUCK-BOOST circuit with an added DC blocking capacitor. As shown in fig. 3, the circuit is added with a dc blocking capacitor C1 on the basis of the circuit shown in fig. 1, and the implementation of magnetic bias suppression by using the dc blocking capacitor C1 is a well-known technology and will not be described in detail here. Although this solution is simple, the addition of the blocking capacitor increases the complexity of the circuit, and in the case of high current, the selection of the blocking capacitor is very difficult, and the size and cost of the converter are increased.
The voltage U1 of the resistor R1 for detecting the current of the secondary side full bridge circuit and the voltage U2 of the resistor R2 for detecting the current of the secondary side full bridge circuit in the isolated BUCK-BOOST circuit of the blocking capacitor in the related art are schematic diagrams of the voltage U1 of the resistor R1 and the voltage U2 of the resistor R2 based on the isolated BUCK-BOOST circuit in the related art of fig. 1, as shown in fig. 4a and 4 b. FIG. 4a is a schematic diagram showing waveforms of a voltage U1 of a detection resistor R1 and a voltage U2 of a resistor R2 when a transformer is unbiased in the related art, as shown in FIG. 4a, the voltages U1 and U2 have the same amplitude, and are both-75 mV; FIG. 4b is a schematic diagram showing waveforms of the voltage U1 of the detection resistor R1 and the voltage U2 of the resistor R2 when the transformer is biased in the related art, as shown in FIG. 4b, the amplitudes of the voltages U1 and U2 are different, U1 is about-60 mV, and U2 is about-90 mV. As can be seen from a comparison between fig. 4a and 4b, if it is determined from the detected values of U1 and U2 and adjusted so that U1 is equal to U2, the transformer is unbiased.
Example 1
The method provided by embodiment 5 of the present application may be executed in a mobile terminal, a computer terminal, or a similar computing device. Taking the example of being operated on a mobile terminal, fig. 5 is a hardware structure block diagram of the mobile terminal of a magnetic bias suppression method according to an embodiment of the present invention. As shown in fig. 5, the mobile terminal 50 may include one or more (only one shown) processors 502 (the processors 502 may include, but are not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 504 for storing data, and a transmission device 506 for communication functions. It will be understood by those skilled in the art that the structure shown in fig. 5 is only an illustration and is not intended to limit the structure of the electronic device. For example, mobile terminal 50 may also include more or fewer components than shown in FIG. 5, or have a different configuration than shown in FIG. 5.
The memory 504 can be used to store software programs and modules of application software, such as program instructions/modules corresponding to the bias suppression method in the embodiment of the present invention, and the processor 502 executes various functional applications and data processing by running the software programs and modules stored in the memory 504, so as to implement the above-mentioned method. The memory 504 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 504 may further include memory located remotely from the processor 502, which may be connected to the mobile terminal 50 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 506 is used for receiving or transmitting data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal 50. In one example, the transmission device 506 includes a Network adapter (NIC) that can be connected to other Network devices through a base station so as to communicate with the internet. In one example, the transmission device 506 can be a Radio Frequency (RF) module, which is used for communicating with the internet in a wireless manner.
In this embodiment, a bias suppression method operating in the mobile terminal is provided, and fig. 6 is a flowchart of the bias suppression method according to an embodiment of the present invention, as shown in fig. 6, where the flowchart includes the following steps:
step S602, detecting the voltage value U1 of a resistor R1 for detecting the current of the secondary side full bridge circuit and the voltage value U2 of a resistor R2 for detecting the current of the secondary side full bridge circuit in the converter;
step S604, according to U1 and U2, the magnetic bias of the transformer in the converter is restrained;
through the steps, the magnetic bias of the transformer in the converter can be restrained according to the voltage value U1 of the resistor R1 for detecting the current of the secondary full bridge circuit in the original circuit of the transformer and the voltage value U2 of the resistor R2 for detecting the current of the secondary full bridge circuit in the original circuit of the transformer, so that the magnetic bias of the transformer in the converter can be restrained effectively without adding any accessory elements, therefore, the problems of high circuit complexity, large converter volume and high cost caused by the mode that the magnetic bias phenomenon of the transformer in the circuit is eliminated by adding the DC blocking capacitor in the circuit of the converter in the related technology can be solved, and the effects of reducing the circuit complexity and reducing the converter volume and cost are achieved.
Optionally, according to U1 and U2, suppressing magnetic biasing of a transformer in the converter comprises: according to U1 and U2, acquiring the compensation amount required by the duty ratio signal of each switching tube of the main-side full-bridge circuit in the converter; and inhibiting the magnetic bias of the transformer in the converter in a mode of superposing the acquired compensation quantity of each switching tube and the corresponding duty ratio information of each switching tube.
Optionally, according to U1 and U2, the compensation amount required for obtaining the duty cycle signal of each switching tube of the main-side full-bridge circuit in the converter includes: acquiring a voltage difference value between U1 and U2; acquiring a first compensation quantity according to the voltage difference; and acquiring the compensation amount required by the duty ratio signal of each switching tube of the main-side full-bridge circuit in the converter by judging the first compensation amount.
Optionally, obtaining the first compensation amount according to the voltage difference includes: acquiring a first compensation quantity in a mode of filtering the voltage difference; or, the first compensation amount is obtained by performing amplitude limiting processing on the voltage difference.
Optionally, obtaining the compensation amount required by the duty cycle signal of each switching tube of the main-side full-bridge circuit in the converter by judging the first compensation amount includes: when the first compensation amount is larger than zero, the compensation amount of the transformer positive excitation direction switching tubes Q1 and Q4 of the main-side full-bridge circuit is the first compensation amount, and the compensation amount of the transformer negative excitation direction switching tubes Q2 and Q3 of the main-side full-bridge circuit is zero; when the first compensation amount is less than zero, the compensation amounts of the switching tubes Q1 and Q4 of the main-side full-bridge circuit are zero, and the compensation amounts of the switching tubes Q2 and Q3 of the main-side full-bridge circuit are absolute values of the first compensation amount.
For the convenience of understanding the above embodiments, the isolated BUCK-BOOST circuit is taken as an example for explanation.
The embodiment provides a method for effectively inhibiting the magnetic bias of the transformer of the isolation BUCK-BOOST circuit under the conditions of not adding an additional element and not increasing the volume of a converter.
FIG. 7 is a flowchart illustrating a method for suppressing magnetic bias of an isolated BUCK-BOOST circuit according to an embodiment of the present invention. As shown in fig. 7, the method comprises the following steps:
the first step is as follows: the voltage value U1 of a resistor R1 for detecting the current of the secondary side full bridge circuit of the transformer in the converter and the voltage value U2 of a resistor R2 for detecting the current of the secondary side full bridge circuit of the transformer are sampled.
The second step is that: the voltage difference Δ U between R1 and R2 is calculated, and the voltage difference Δ U is processed to obtain the compensation amount Δ d (equivalent to the first compensation amount described above). The processing comprises the following steps: and filtering the voltage difference value delta U or carrying out amplitude limiting processing on the voltage difference value delta U. The filtering comprises the step of carrying out average value processing on the delta U obtained by multiple times of calculation; the clipping process includes Δ U maximum or minimum value limiting, for example, selecting a multiple calculated Δ U maximum or minimum value.
The third step: and carrying out logic judgment according to the obtained compensation quantity delta d, and determining the compensation quantity required by the duty ratio signal of each switching tube in the transformer main side full-bridge circuit. When Δ D is larger than 0, the compensation amount of D (Q1, Q4) is Δ D, and the compensation amount of D2(Q2, Q3) is 0; when Δ D is smaller than 0, the compensation amount of D1 is 0, and the compensation amount of D2 is the absolute value of Δ D.
The fourth step: and superposing the obtained compensation quantity and a duty ratio signal of a corresponding switching tube to inhibit the direct current magnetic bias of the transformer. For example, D1(Q1, Q4) after compensation is D (Q1, Q4) + Δ D, the compensation amount of D (Q2, Q3) is 0, D2(Q2, Q3) after compensation is D (Q2, Q3) +0,
fig. 8 is a schematic structural diagram of an isolated BUCK-BOOST circuit magnetic bias suppression device according to an embodiment of the present invention, and as shown in fig. 8, the device includes: a voltage acquisition unit; a calculation unit; a logic processing unit; a bias suppression unit.
The voltage acquisition unit: the voltage U1 of a resistor R1 used for detecting the current of the secondary side full bridge circuit in the converter and the voltage U2 of a resistor R2 used for detecting the current of the secondary side full bridge circuit in the converter are obtained.
The calculating unit: and calculating a voltage difference value delta U of the resistors R1 and R2, and processing the voltage difference value delta U to obtain a compensation amount delta d. The processing comprises the following steps: and filtering the voltage difference value delta U or carrying out amplitude limiting processing on the voltage difference value delta U. The filtering comprises the step of carrying out average value processing on the delta U obtained by multiple times of calculation; the clipping process includes Δ U maximum or minimum value limiting, for example, selecting a multiple calculated Δ U maximum or minimum value.
The logic processing unit: the compensation quantity required by the duty cycle signal of each switching tube in the main-side full-bridge circuit is determined. When Δ D is larger than 0, the compensation amount of D (Q1, Q4) is Δ D, and the compensation amount of D2(Q2, Q3) is 0; when Δ D is smaller than 0, the compensation amount of D1 is 0, and the compensation amount of D2 is the absolute value of Δ D.
The bias suppression means: and the circuit is used for superposing the compensation quantity and a duty ratio signal D output by each switching tube loop in the main-side full-bridge circuit so as to inhibit the direct current magnetic bias of the transformer.
FIG. 9 is a schematic diagram of the connection between the isolated BUCK-BOOST circuit bias suppression device and the BUCK-BOOST circuit according to the embodiment of the invention. As shown in fig. 9, the main power circuit adopts the circuit shown in fig. 1, and the device parameters of the circuit shown in fig. 1 have been described previously and are not repeated; the magnetic bias suppression device shown in fig. 9 is the magnetic bias suppression device shown in fig. 8, and the magnetic bias suppression device shown in fig. 8 is described above and will not be described again. The voltage sampling units have inputs of R1 and R2 sampled voltages U1 and U2.
FIG. 10 is a schematic diagram of an isolated BUCK-BOOST circuit transformer field current according to an embodiment of the invention. At this time, the difference of the switching speeds of the switching tubes Q1, Q2, Q3 and Q4 is 80ns, as shown in FIG. 10, the exciting current of the transformer is symmetric based on the positive and negative amplitudes of 0 point, the amplitude is positive and negative 1A, compared with the exciting current of the transformer which is not adopted in the invention in the figures 2A, 2b and 2c, the exciting current of the transformer is between 10 and 12A, and the exciting current of the transformer is effectively restrained by adopting the method of the invention.
In summary, with the above technical solution, compared with the prior art, the technical solution provided by the present invention has the following advantages: the problem of long-time work magnetic biasing of the conventional BUCK-BOOST circuit is solved, any device is not required to be added, and the increase of the volume and the cost is avoided.
Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
Example 2
In this embodiment, a magnetic bias suppression device is further provided, and the device is used to implement the foregoing embodiments and preferred embodiments, and the description of the device that has been already made is omitted. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
Fig. 11 is a block diagram of a structure of a magnetic bias suppression apparatus according to an embodiment of the present invention, as shown in fig. 11, the apparatus including:
a detection module 112 (corresponding to the voltage acquisition unit) for detecting a voltage value U1 of a resistor R1 for detecting the current of the secondary-side full-bridge circuit and a voltage value U2 of a resistor R2 for detecting the current of the secondary-side full-bridge circuit in the inverter;
and a suppression module 114 connected to the detection module 112 and configured to suppress magnetic biasing of the transformer in the converter according to U1 and U2.
Optionally, the suppression module 114 is further configured to obtain, according to U1 and U2, an amount of compensation required for the duty cycle signal of each switching tube of the main-side full-bridge circuit in the converter; and inhibiting the magnetic bias of the transformer in the converter in a mode of superposing the acquired compensation quantity of each switching tube and the corresponding duty ratio information of each switching tube.
Optionally, the suppression module 114 is further configured to obtain a voltage difference between U1 and U2; acquiring a first compensation quantity according to the voltage difference; and acquiring the compensation amount required by the duty ratio signal of each switching tube of the main-side full-bridge circuit in the converter by judging the first compensation amount.
Optionally, the suppression module 114 is further configured to obtain a first compensation amount by performing filtering processing on the voltage difference; or, the first compensation amount is obtained by performing amplitude limiting processing on the voltage difference.
Optionally, the suppressing module 114 is further configured to, in a case that the first compensation amount is greater than zero, set the compensation amount of the transformer positive excitation direction switching tubes Q1, Q4 of the primary-side full-bridge circuit to be the first compensation amount, and set the compensation amount of the transformer negative excitation direction switching tubes Q2, Q3 of the primary-side full-bridge circuit to be zero; when the first compensation amount is less than zero, the compensation amounts of the switching tubes Q1 and Q4 of the main-side full-bridge circuit are zero, and the compensation amounts of the switching tubes Q2 and Q3 of the main-side full-bridge circuit are absolute values of the first compensation amount.
It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in different processors in any combination.
Example 3
An embodiment of the present invention further provides a storage medium including a stored program, where the program executes any one of the methods described above.
Alternatively, in the present embodiment, the storage medium may be configured to store program codes for performing the following steps:
s1, detecting the voltage value U1 of the resistor R1 for detecting the current of the secondary side full bridge circuit and the voltage value U2 of the resistor R2 for detecting the current of the secondary side full bridge circuit in the converter;
and S2, according to the U1 and the U2, the magnetic bias of the transformer in the converter is restrained.
Optionally, the storage medium is further arranged to store program code for performing the steps of: according to U1 and U2, suppressing magnetic biasing of a transformer in a converter comprises:
s1, acquiring the compensation quantity required by the duty ratio signal of each switching tube of the main side full bridge circuit in the converter according to U1 and U2;
and S2, suppressing the magnetic bias of the transformer in the converter by superposing the acquired compensation amount of each switching tube and the duty ratio information of each corresponding switching tube.
Optionally, the storage medium is further arranged to store program code for performing the steps of: according to U1 and U2, the compensation amount required for acquiring the duty ratio signal of each switching tube of the main-side full-bridge circuit in the converter comprises the following steps:
s1, acquiring a voltage difference value between U1 and U2;
s2, acquiring a first compensation amount according to the voltage difference;
and S3, acquiring the compensation amount required by the duty ratio signal of each switching tube of the main-side full-bridge circuit in the converter by judging the first compensation amount.
Optionally, the storage medium is further arranged to store program code for performing the steps of: obtaining the first compensation amount according to the voltage difference comprises:
s1, obtaining a first compensation amount by filtering the voltage difference; or,
s2, obtaining a first compensation amount by performing amplitude limiting on the voltage difference.
Optionally, the storage medium is further arranged to store program code for performing the steps of: the method for acquiring the compensation quantity required by the duty ratio signal of each switching tube of the main-side full-bridge circuit in the converter in a mode of judging the first compensation quantity comprises the following steps:
s1, when the first compensation amount is larger than zero, the compensation amount of the transformer positive excitation direction switch tubes Q1 and Q4 of the main-side full-bridge circuit is the first compensation amount, and the compensation amount of the transformer negative excitation direction switch tubes Q2 and Q3 of the main-side full-bridge circuit is zero;
when the first compensation amount is less than zero, S2 shows that the compensation amount of the switching tubes Q1 and Q4 of the main-side full-bridge circuit is zero, and the compensation amount of the switching tubes Q2 and Q3 of the main-side full-bridge circuit is the absolute value of the first compensation amount.
Optionally, in this embodiment, the storage medium may include, but is not limited to: various media capable of storing program codes, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
Embodiments of the present invention also provide a processor configured to execute a program, where the program executes to perform any of the steps in the method.
Optionally, in this embodiment, the program is configured to perform the following steps:
optionally, in this embodiment, the program is configured to perform the following steps:
s1, detecting the voltage value U1 of the resistor R1 for detecting the current of the secondary side full bridge circuit and the voltage value U2 of the resistor R2 for detecting the current of the secondary side full bridge circuit in the converter;
and S2, according to the U1 and the U2, the magnetic bias of the transformer in the converter is restrained.
Optionally, in this embodiment, the program is configured to perform the following steps: according to U1 and U2, suppressing magnetic biasing of a transformer in a converter comprises:
s1, acquiring the compensation quantity required by the duty ratio signal of each switching tube of the main side full bridge circuit in the converter according to U1 and U2;
and S2, suppressing the magnetic bias of the transformer in the converter by superposing the acquired compensation amount of each switching tube and the duty ratio information of each corresponding switching tube.
Optionally, in this embodiment, the program is configured to perform the following steps: according to U1 and U2, the compensation amount required for acquiring the duty ratio signal of each switching tube of the main-side full-bridge circuit in the converter comprises the following steps:
s1, acquiring a voltage difference value between U1 and U2;
s2, acquiring a first compensation amount according to the voltage difference;
and S3, acquiring the compensation amount required by the duty ratio signal of each switching tube of the main-side full-bridge circuit in the converter by judging the first compensation amount.
Optionally, in this embodiment, the program is configured to perform the following steps: obtaining the first compensation amount according to the voltage difference comprises:
s1, obtaining a first compensation amount by filtering the voltage difference; or,
s2, obtaining a first compensation amount by performing amplitude limiting on the voltage difference.
Optionally, in this embodiment, the program is configured to perform the following steps: the method for acquiring the compensation quantity required by the duty ratio signal of each switching tube of the main-side full-bridge circuit in the converter in a mode of judging the first compensation quantity comprises the following steps:
s1, when the first compensation amount is larger than zero, the compensation amount of the transformer positive excitation direction switch tubes Q1 and Q4 of the main-side full-bridge circuit is the first compensation amount, and the compensation amount of the transformer negative excitation direction switch tubes Q2 and Q3 of the main-side full-bridge circuit is zero;
when the first compensation amount is less than zero, S2 shows that the compensation amount of the switching tubes Q1 and Q4 of the main-side full-bridge circuit is zero, and the compensation amount of the switching tubes Q2 and Q3 of the main-side full-bridge circuit is the absolute value of the first compensation amount.
Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation manners, and this embodiment is not described herein again.
It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the principle of the present invention should be included in the protection scope of the present invention.

Claims (12)

1. A bias suppression method, comprising:
detecting the voltage value U1 of a resistor R1 for detecting the current of the secondary side full bridge circuit and the voltage value U2 of a resistor R2 for detecting the current of the secondary side full bridge circuit in the converter;
according to the U1 and the U2, magnetic biasing of a transformer in the converter is restrained.
2. The method of claim 1, wherein suppressing the magnetic biasing of a transformer in the converter from the U1 and the U2 comprises:
according to the U1 and the U2, the compensation amount required by a duty ratio signal of each switching tube of a main side full bridge circuit in the converter is obtained;
and inhibiting the magnetic bias of the transformer in the converter in a mode of superposing the acquired compensation quantity of each switching tube and the corresponding duty ratio information of each switching tube.
3. The method of claim 2, wherein the obtaining the compensation amount required for the duty cycle signal of each switching tube of the main-side full-bridge circuit in the converter according to the U1 and the U2 comprises:
acquiring a voltage difference value between the U1 and the U2;
acquiring a first compensation quantity according to the voltage difference value;
and acquiring the compensation amount required by the duty ratio signal of each switching tube of the main-side full-bridge circuit in the converter in a mode of judging the first compensation amount.
4. The method of claim 3, wherein obtaining a first compensation amount based on the voltage difference comprises:
acquiring the first compensation quantity in a mode of filtering the voltage difference value; or,
and acquiring the first compensation amount in a mode of carrying out amplitude limiting processing on the voltage difference value.
5. The method of claim 3, wherein obtaining the compensation amount required by the duty cycle signal of each switching tube of the main-side full-bridge circuit in the converter by judging the first compensation amount comprises:
when the first compensation amount is larger than zero, the compensation amount of the transformer positive excitation direction switching tubes Q1 and Q4 of the primary side full-bridge circuit is the first compensation amount, and the compensation amount of the transformer negative excitation direction switching tubes Q2 and Q3 of the primary side full-bridge circuit is zero;
when the first compensation amount is less than zero, the compensation amount of the switching tubes Q1 and Q4 of the main-side full-bridge circuit is zero, and the compensation amount of the switching tubes Q2 and Q3 of the main-side full-bridge circuit is the absolute value of the first compensation amount.
6. A magnetic bias suppression device, comprising:
the detection module is used for detecting the voltage value U1 of a resistor R1 used for detecting the current of the secondary side full bridge circuit and the voltage value U2 of a resistor R2 used for detecting the current of the secondary side full bridge circuit in the converter;
and the suppression module is used for suppressing the magnetic bias of a transformer in the converter according to the U1 and the U2.
7. The apparatus of claim 6, wherein the suppression module is further configured to obtain, according to the U1 and the U2, an amount of compensation required for the duty cycle signal of each switching tube of the main-side full-bridge circuit in the converter; and inhibiting the magnetic bias of a transformer in the converter in a mode of superposing the acquired compensation quantity of each switching tube and the corresponding duty ratio information of each switching tube.
8. The apparatus of claim 7, wherein the suppression module is further configured to obtain a voltage difference between the U1 and the U2; acquiring a first compensation quantity according to the voltage difference value; and acquiring the compensation amount required by the duty ratio signal of each switching tube of the main-side full-bridge circuit in the converter in a mode of judging the first compensation amount.
9. The apparatus of claim 8, wherein the suppressing module is further configured to obtain the first compensation amount by performing a filtering process on the voltage difference; or, the first compensation amount is obtained by performing amplitude limiting processing on the voltage difference.
10. The apparatus of claim 8, wherein the suppression module is further configured to: when the first compensation amount is larger than zero, the compensation amount of the transformer positive excitation direction switching tubes Q1 and Q4 of the primary side full-bridge circuit is the first compensation amount, and the compensation amount of the transformer negative excitation direction switching tubes Q2 and Q3 of the primary side full-bridge circuit is zero; when the first compensation amount is less than zero, the compensation amount of the switching tubes Q1 and Q4 of the main-side full-bridge circuit is zero, and the compensation amount of the switching tubes Q2 and Q3 of the main-side full-bridge circuit is the absolute value of the first compensation amount.
11. A storage medium, comprising a stored program, wherein the program when executed performs the method of any one of claims 1 to 5.
12. A processor, characterized in that the processor is configured to run a program, wherein the program when running performs the method of any of claims 1 to 5.
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