CN109117188A - A kind of restructural butterfly computation device of multichannel hybrid base FFT - Google Patents
A kind of restructural butterfly computation device of multichannel hybrid base FFT Download PDFInfo
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Abstract
The invention discloses a kind of restructural butterfly computation device of multichannel hybrid base FFT, which includes: control unit, first choice switch unit and arithmetic element；Control unit is used to generate operational order to operational data according to receiving, wherein to operational data includes digital signal to be processed, twiddle factor and default twiddle factor coefficient；First choice switch unit is used to select corresponding conduction mode according to operational order；Arithmetic element is used to treat operational data according to conduction mode and carry out butterfly computation.Technical solution in through the invention is conducive to the utilization efficiency for improving electronic component in butterfly computation device, reduces circuit hardware resource and power consumption, is conducive to improve the accuracy and real-time for calculating data.
Description
Technical field
Design chips technical field of the present invention, in particular to a kind of restructural butterfly computation of multichannel hybrid base FFT
Device.
Background technique
In digital signal processing, especially for having long sequence, discrete Fourier transform (Discrete Fourier
Transform, DTF) be a kind of particularly important mathematic(al) manipulation, its essence is the finite point of finite length sequence Fourier transformation from
Sampling is dissipated, Digital Signal Processing is carried out in frequency domain sample with the method for digital operation, considerably increases digital letter
Number processing flexibility.It for generally several DFT algorithms, is transported by the DFT that the DFT to count greatly is converted into small point
It calculates, to realize the purpose for reducing computational complexity, industry is usually to use Fast Fourier Transform (FFT) (Fast Fourier
Transform, FFT) realize DFT transform, the algorithms most in use for calculating FFT is base 2FFT and base 4FFT, and points are limited in 2 power
Power or 4 power side, which limit topic points selectable range.For certain application such as synthetic aperture radar
In (Synthetic Aperture Radar, SAR) signal processing, especially under beam bunching mode, due to processing time and face
The points of each processing data cannot be extended to and meet base 2 or base 4FFT algorithm, particularly with big points by long-pending limitation
Otherwise FFT can extend and calculate time and the more memory headrooms of consumption.
And in the prior art, Non-2-power points FFT transform is usually subjected to bit sequence zero padding, the sequence after making zero padding
Length meets the process range of FFT/IFFT processor；FFT/IFFT is carried out to the sequence after zero padding using FFT/IFFT processor
It calculates, but this way introduces noise, reduces precision, it is possible to cause damages to the calculated performance of chip.Especially exist
Fixed point FFT and IFFT in the prior art, data are overflowed in order to prevent, and the input of every grade of butterfly computation is needed divided by input data
Number, for radix be greater than 2 FFT or IFFT, will cause so every grade of input data loss bit it is excessive, computational accuracy
Error is larger, affects the performance of communication system.
Summary of the invention
It is an object of the invention to: a kind of restructural butterfly computation device of multichannel hybrid base FFT is provided, is conducive to improve butterfly
The utilization efficiency of electronic component in shape arithmetic unit, reduces circuit hardware resource and power consumption, is conducive to improve the standard for calculating data
True property and real-time.
The technical scheme is that providing a kind of restructural butterfly computation device of multichannel hybrid base FFT, the butterfly computation
Device includes: control unit, first choice switch unit and arithmetic element；Control unit is used for according to receiving to operand
According to generating operational order, wherein to operational data include digital signal to be processed, twiddle factor and default twiddle factor system
Number；First choice switch unit is used to select corresponding conduction mode according to operational order；Arithmetic element is used for according to conducting mould
Formula treats operational data and carries out butterfly computation.
In any of the above-described technical solution, further, arithmetic element includes: two bases, 2 butterfly computation device, the first plural number
Adder and the second complex adder；2 butterfly computation device of base is used for according to corresponding to operational data and first choice switch unit
Conduction mode, carry out 2 butterfly computation of base；Two 2 butterfly computation devices of base are also used to corresponding according to first choice switch unit
Conduction mode forms a 3 butterfly computation device of base, 3 butterfly computation device of base with the first complex adder and the second complex adder
3 butterfly computation of base is carried out for treating operational data.
In any of the above-described technical solution, further, 2 butterfly computation device of base includes: the first complex multiplier, and third is multiple
Number adder and complex subtraction device；The first input end of 2 butterfly computation device of base is connected to the first of third complex adder
Input terminal and the first input end that complex subtraction device is connected to by first choice switch unit, third complex adder it is defeated
Outlet is connected to the first output end of 2 butterfly computation device of base by first choice switch, and the output end of complex subtraction device passes through the
One selection switch unit is connected to the second output terminal of 2 butterfly computation device of base；Second input terminal of 2 butterfly computation device of base and rotation
The factor is connected to the input terminal of the first complex multiplier, and the output end of the first complex multiplier is connected to third plural number
Second input terminal of adder and the second input terminal of complex subtraction device.
In any of the above-described technical solution, further, further includes: displacement computing unit；Computing unit is shifted to be used for
It when carrying out 3 butterfly computation of base, according to operational order, treats operational data and is shifted, and will be sent out after displacement to operational data
It send to arithmetic element, wherein to operational data include digital signal to be processed, twiddle factor and default twiddle factor system
Number；Arithmetic element is also used to: according to conduction mode, 3 butterfly computation device of a base is formed, to carrying out after displacement to operational data
3 butterfly computation of base.
In any of the above-described technical solution, further, 3 butterfly computation device of base includes: that the second complex multiplier, third are multiple
Number multiplier, complex adder group, the first complex adder and the second complex adder；First input of 3 butterfly computation device of base
End is connected to the first output end of shown 3 butterfly computation device of base, 3 butterfly of base by complex adder group and first choice switch unit
The first input end of shape arithmetic unit is also attached to the first input end of the first complex adder, the output end of the first complex adder
The second output terminal of 3 butterfly computation device of base, the first input end of 3 butterfly computation device of base are connected to by first choice switch unit
It is also attached to the first input end of the second complex adder, the output end of the second complex adder passes through first choice switch unit
It is connected to the third output end of 3 butterfly computation device of base；Second input terminal of 3 butterfly computation device of base is connected to the second complex multiplier
Input terminal, the first output end of the second complex multiplier is connected to base by complex adder group and first choice switch unit
The second output terminal of first output end of 3 butterfly computation devices, the second complex multiplier is opened by displacement computing unit, first choice
It closes unit and complex adder group is connected to the second input terminal of the first complex adder, the third output of the second complex multiplier
End is by shifting computing unit, first choice switch unit and complex adder group are connected to the second defeated of the second complex adder
Enter end；The third input terminal of 3 butterfly computation device of base is connected to the input terminal of third complex multiplier, and the of third complex multiplier
One output end is connected to the first output end of 3 butterfly computation device of base by complex adder group and first choice switch unit, the
The second output terminal of three complex multipliers is connected to the first complex adder by displacement computing unit and complex adder group
The third output end of second input terminal, the second complex multiplier passes through displacement computing unit, first choice switch unit and plural number
Adder group is connected to the second input terminal of the second complex adder, wherein the second complex multiplier is 2 butterfly computation of base
First complex multiplier of device, third complex multiplier are the first complex multiplier of another 2 butterfly computation device of base, and plural number adds
Musical instruments used in a Buddhist or Taoist mass group includes the third complex adder and complex subtraction device of two bases, 2 butterfly computation device.
In any of the above-described technical solution, further, displacement computing unit includes: that the 4th complex multiplier and first move
Bit register；4th complex multiplier is for calculating multiplying between digital signal, twiddle factor and default twiddle factor coefficient
Product；First shift register is connected to the 4th complex multiplier, and the first shift register is used to carry out shifting function to product, and
Product after displacement is sent to arithmetic element, wherein default twiddle factor coefficient is the product of twiddle factor coefficient and 2, is moved
Bit manipulation is that data exponent moves right one.
In any of the above-described technical solution, further, computing unit is shifted further include: selection switch；Selection switch is used
According to conduction mode, the conducting and shutdown of the output of the 4th complex multiplier are controlled.
In any of the above-described technical solution, further, further includes: the second selection switch unit, third selection switch are single
Member and the second shift register；Second selection switch unit is set to the output end of control unit, and the second selection switch unit is used
According to operational order Selecting operation mode, wherein operation mode includes FFT operation mode and IFFT operation mode；Third choosing
The input terminal that switch unit is set to twiddle factor is selected, third selection switch unit is connected to the input of the first complex multiplier
End, third select switch unit to be used to select twiddle factor type according to operation mode, and twiddle factor type includes the first rotation
Factor pattern and the second twiddle factor type, the first twiddle factor type correspond to FFT operation mode, the second twiddle factor type
Corresponding to IFFT operation mode；Second shift register is used to carry out to operational data when operation mode is IFFT mode
Shifting function.
In any of the above-described technical solution, further, third selects switch unit further include: phase inverter；Phase inverter is set
It is placed between the first complex multiplier and third selection switch, phase inverter is used for when carrying out IFFT operation, treats operational data
The highest order of imaginary part executes inversion operation.
The beneficial effects of the present invention are: corresponding to the conducting mould to operational data by the selection of first choice switch unit
Formula constitutes restructural 2/3 butterfly of base using the complex adder of multiplexing, complex multiplier according to the points of data to be calculated
Arithmetic unit improves the utilization efficiency of electronic component, is conducive to the volume for reducing chip, is transported using 3 butterfly computation device of base
It calculates, is conducive to reduce in calculating process a possibility that introducing noise, be conducive to the computational accuracy for improving butterfly computation device, reduce
Delay in calculating process.
Technical solution in the present invention selects operation mode by the second selection switch unit, and is selected by third
It selects switch unit and the second shift register carries out pending data to negate processing, so that butterfly computation device is able to carry out FFT/
IFFT operation optimizes the arithmetic type of butterfly computation device, expands the operating range of butterfly computation device, is conducive to improve chip
The utilization rate of internal electronic element resource.
Detailed description of the invention
Above-mentioned and/or additional aspect of the invention and advantage will become from the description of the embodiment in conjunction with the following figures
Obviously and it is readily appreciated that, in which:
Fig. 1 is the schematic block diagram of the restructural butterfly computation device of multichannel hybrid base FFT according to an embodiment of the invention；
Fig. 2 is the circuit diagram of the restructural butterfly computation device of multichannel hybrid base FFT according to an embodiment of the invention；
Fig. 3 is the circuit diagram of the restructural butterfly computation device of base 2 according to an embodiment of the invention；
Fig. 4 is the circuit diagram of the restructural butterfly computation device of base 3 according to an embodiment of the invention；
Fig. 5 is that the operation result of existing Non-2-power zero padding calculating FFT method according to an embodiment of the invention is imitative
True figure；
Fig. 6 is the operation result analogous diagram of restructural butterfly computation device according to an embodiment of the invention.
Specific embodiment
To better understand the objects, features and advantages of the present invention, with reference to the accompanying drawing and specific real
Applying mode, the present invention is further described in detail.It should be noted that in the absence of conflict, the implementation of the application
Feature in example and embodiment can be combined with each other.
In the following description, many details are elaborated to facilitate a thorough understanding of the present invention, still, the present invention may be used also
To be implemented using other than the one described here other modes, therefore, protection scope of the present invention is not by described below
Specific embodiment limitation.
Embodiment:
Hereinafter with reference to Fig. 1-6, embodiments of the present invention will be described.
As shown in Figure 1, the restructural butterfly computation device 100 of one of present invention multichannel hybrid base FFT, comprising: control is single
Member 101, first choice switch unit 102 and arithmetic element 104；Control unit 101 is used for according to receiving to operand
According to generation operational order；
Specifically, restructural butterfly computation device 100 receives after operational data, control unit 101 will be to operational data
It is decomposed, 2 will be decomposed into operational datam×3n, wherein m, n are the calculating points for corresponding to base 2 and base 3 to operational data
Index part, the generation of control unit 101 first carries out 3 operation of n times base, then executes the operational order of 2 operation of m base.
Include three bit registers in control unit 101, the input terminal operation of three bit registers is matched
It sets, realizes the configuration of restructural butterfly computation device 100, when operation [0]=1, mixed base 2/3FFT operation butterfly computation
Device 100 is dynamically configured as IFFT mode, when operation [0]=0,100 quilt of mixed base 2/3FFT operation butterfly computation device
It is dynamically configured as FFT mode, as operation [2:1]=2 ' b01, mixed base 2/3FFT operation butterfly computation device 100 is passive
State is configured to base 2FFT mode, as operation [2:1]=2 ' b10,100 quilt of mixed base 2/3FFT operation butterfly computation device
It is dynamically configured as base 3FFT mode.Wherein, operation is three [2:0], first [0] control FFT/IFFT operation mode
Selection, second and third position [3:2] controls restructural butterfly computation device and is converted between 2/3 mode of base.
In the present embodiment, first choice switch unit 102 is used to select corresponding conduction mode according to operational order；
Specifically, as shown in Fig. 2, first choice switch unit 102 is made of the selector of 7 alternatives, including selection
Device 14, selector 16, selector 17, selector 18, selector 19, selector 20 and selector 21, by taking selector 14 as an example, when
When the instruction that operational order inputs selector 14 is " 01 ", corresponding is 2 butterfly computation device of base, the conducting mould of selector 14
Formula is by the input terminal A of 2 butterfly computation device of the second base2Input be sent to complex adder 8.When operational order is to selector 14
When the instruction of input is " 10 ", corresponding is 3 butterfly computation device of base, and the conduction mode of selector 14 is by complex adder 7
The operation result of (the third complex adder of 2 butterfly computation device of the first base) is sent to complex adder 8.
In the present embodiment, arithmetic element 104 be used for according to conduction mode and displacement twiddle factor, treat operational data into
Row butterfly computation.
Further, arithmetic element 104 includes: that two bases, 2 butterfly computation device, the first complex adder and the second plural number add
Musical instruments used in a Buddhist or Taoist mass；2 butterfly computation device of base is used to carry out according to operational data and the corresponding conduction mode of first choice switch unit 102
2 butterfly computation of base；
Wherein, 2 butterfly computation device of base includes: the first complex multiplier, third complex adder and complex subtraction device；Base 2
The first input end of butterfly computation device is connected to the first input end of third complex adder and is opened by first choice
The first input end that unit 102 is connected to complex subtraction device is closed, the output end of third complex adder is switched by first choice
102 are connected to the first output end of 2 butterfly computation device of base, and the output end of complex subtraction device is connected by first choice switch 102
In the second output terminal of 2 butterfly computation device of base；The second input terminal and twiddle factor of 2 butterfly computation device of base are connected to first
The input terminal of complex multiplier, the output end of the first complex multiplier are connected to the second input terminal of third complex adder
With the second input terminal of complex subtraction device.
Specifically, as shown in figure 3, the input terminal A of 2 butterfly computation device of base (2 butterfly computation device of the first base)1(2 butterfly of base fortune
Calculate the first input end of device) it is connected to complex adder 7 (third complex adder) and selector 17, it will by selector 17
It is corresponding to be transferred to complex subtraction device 10 to operational data, wherein complex adder 10 is the plural number for executing complex subtraction and calculating
Adder, the output end of complex adder 7 are connected to the first output end X of 2 butterfly computation device of base by selector 181, plural number
The output end of subtracter 10 is connected to the second output terminal X of 2 butterfly computation device of base by selector 192；2 butterfly computation device of base
Second input terminal B and twiddle factor input terminal W1It is connected to complex multiplier 1 (the first complex multiplier), complex multiplier 1 will
The product being calculated is respectively sent to complex adder 7 and complex subtraction device 10.Set input terminal A1It is corresponding to operation
Digital signal is A'=(ar1+ai1* j), the corresponding digital signal to operation of input terminal B is B'=(br+bi* j), twiddle factor
For W1' then corresponding output result are as follows:
X1=A1’+B’*W1’
=[ar1+(br*wr1-bi*wi1)]+j*[ai1+(bi*wr1+br*wi1)]
X2=A1-B*W1’
=[ar1-(br*wr1-bi*wi1)]+j*[ai1-(bi*wr1+br*wi1)]
In formula, W1'=wr1+j*wi1, W2'=wr2+j*wi2。
Wherein, complex adder 9 is to execute the complex adder of complex subtraction operation.Second base, 2 butterfly computation device it is defeated
Enter to hold A2Connection type and input terminal A1Connection type it is similar, the connection of the second input terminal C of 2 butterfly computation device of the second base
Mode is similar to the connection type of the second input terminal B, and details are not described herein again.
Preferably, complex subtraction device is the 4th complex adder for executing complex subtraction operation, can be divided into the first plural number
Subtracter and the second complex subtraction device.
In the present embodiment, restructural butterfly computation device 100, further includes: displacement computing unit 103 shifts computing unit
103 for according to operational order, treating operational data and being shifted, and will be to be shipped after displacement when carrying out 3 butterfly computation of base
It counts according to being sent to arithmetic element 104, wherein to operational data include digital signal to be processed, twiddle factor and default
Twiddle factor coefficient；Arithmetic element 104 is also used to: according to conduction mode, 3 butterfly computation device of a base is formed, after displacement
3 butterfly computation of base is carried out to operational data.
Further, displacement computing unit 103 includes: the 4th complex multiplier and the first shift register；4th plural number
Multiplier is used to calculate the product between digital signal, twiddle factor and default twiddle factor coefficient；First shift register
It is connected to the 4th complex multiplier, the first shift register is used to carry out product shifting function, and the product after displacement is sent out
It send to arithmetic element 104, wherein default twiddle factor coefficient is the product of twiddle factor coefficient and 2, and shifting function is to move right
It is one dynamic.
Further, computing unit 103 is shifted further include: selection switch；Selection switch is for according to conduction mode, control
Make the conducting and shutdown of the output of the 4th complex multiplier.
Specifically, as shown in Fig. 2, the 4th complex multiplier includes complex multiplier 3, complex multiplier 4, complex multiplier
5 and complex multiplier 6, corresponding, the first shift register is shift register 22, shift register 23, shift register
24 and shift register 25, in order to reduce the calculation amount of restructural butterfly computation device 100, with complex multiplier 3 and shift LD
It for device 22, during carrying out 3 operation of base, will be multiplied to the twiddle factor coefficient in operational data with 2, be denoted as default rotation
Transposon coefficient, for example, when twiddle factor coefficient is W3 1When, presetting twiddle factor coefficient is 2*W3 1, it is input to complex multiplier
3, digital signal and twiddle factor W with input terminal B input1Product do multiplication, then the output result of complex multiplier 3 is passed
Send to shift register 22, by shift register 22 carry out shifting function, i.e., by the exponent of the output result of complex multiplier 3 to
One is moved right, the product of digital signal, twiddle factor and twiddle factor coefficient is obtained.
Shift register 22 and 25 sends out the product of digital signal, twiddle factor and twiddle factor coefficient after displacement respectively
It send to selector 16 and selector 17, input 9 He of complex adder is selected according to conduction mode by selector 16 and selector 17
The data of complex adder 10.
Second input terminal of complex multiplier 4 and complex multiplier 5 is default twiddle factor coefficient, 4 He of complex multiplier
The product of digital signal, twiddle factor and default twiddle factor coefficient is passed through selection switch 13 and choosing by complex multiplier 5 respectively
It selects switch 15 and is sent to corresponding displaced register 23 and shift register 24, select switch 13 and selection switch 15 according to conducting mould
Formula chooses whether corresponding product being sent to shift register 23 and shift register 24, when selection switch 13 and selection switch
15 when being sent to shift register 23 and shift register 24 for product, and shift register carries out the exponent of result of product data
A bit manipulation is moved to right, and the product after displacement is respectively sent to complex adder 10 and complex adder 9.
Further, two 2 butterfly computation devices of base are also used to according to the corresponding conducting mould of first choice switch unit 102
Formula forms a 3 butterfly computation device of base, base 3 with displacement computing unit 103, the first complex adder and the second complex adder
Butterfly computation device carries out 3 butterfly computation of base for treating operational data.
Wherein, 3 butterfly computation device of base includes: the second complex multiplier, third complex multiplier, complex adder group,
One complex adder and the second complex adder, wherein the second complex multiplier is first plural number of a 2 butterfly computation device of base
Multiplier, third complex multiplier are the first complex multiplier of another 2 butterfly computation device of base, and complex adder group includes two
The third complex adder and complex subtraction device of a 2 butterfly computation device of base.
Specifically, as shown in figure 4, the second complex multiplier is complex multiplier 1, third complex multiplier is complex multiplication
Device 2, the first complex adder are complex adder 11, and the 4th complex multiplier is complex multiplier 12, complex adder group packet
Include complex adder 7, complex adder 8, complex adder 9 and complex adder 10.
The first input end of 3 butterfly computation device of base is connected to by complex adder group and first choice switch unit 102
First output end of shown 3 butterfly computation device of base, the first input end of 3 butterfly computation device of base are also attached to the first complex adder
First input end, the output end of the first complex adder is connected to 3 butterfly computation device of base by first choice switch unit 102
Second output terminal, the first input end of 3 butterfly computation device of base is also attached to the first input end of the second complex adder, second
The output end of complex adder is connected to the third output end of 3 butterfly computation device of base by first choice switch unit 102；
Specifically, as shown in figure 4, input terminal A1(first input end of 3 butterfly computation device of base) is connected to complex adder 7
First input end, complex adder 11 (the first complex adder) first input end and complex adder 12 (second is multiple
Number adders) first input end, the output end of complex adder 7 is connected to the first of complex adder 8 by selector 14
The output end of input terminal, complex adder 8 is connected to output end X by selector 181(the first output of 3 butterfly computation device of base
End).The output end of complex adder 11 is connected to output end X by selector 192(the second output of 3 butterfly computation device of base
End), the output end of complex adder 12 is connected to output end X by selector 203(third of 3 butterfly computation device of base exports
End).
Second input terminal of 3 butterfly computation device of base is connected to the input terminal of the second complex multiplier, the second complex multiplier
The first output end by complex adder group and first choice switch unit 102 be connected to 3 butterfly computation device of base it is first defeated
The second output terminal of outlet, the second complex multiplier passes through displacement computing unit 103, first choice switch unit 102 and plural number
Adder group is connected to the second input terminal of the first complex adder, and the third output end of the second complex multiplier passes through displacement meter
Calculate the second input terminal that unit 103, first choice switch unit 102 and complex adder group are connected to the second complex adder；
Specifically, as shown in figure 4, input terminal B (the second input terminal of 3 butterfly computation device of base) is connected to complex multiplier 1,
First output end of complex multiplier 1 is connected to the second input terminal of complex adder 7.The second output terminal of complex multiplier 1
The input terminal of selector 16 is connected to by complex multiplier 3 and shift register 22, the output end of selector 16 is connected to multiple
The first input end of number adder 9, the output end of complex adder 9 are connected to the second input terminal of complex adder 11.Plural number
The third output end of multiplier 1 is connected to the first input of complex adder 10 by complex multiplier 4 and shift register 23
End, the output end of complex adder 10 are connected to the second input terminal of complex adder 12.
The third input terminal of 3 butterfly computation device of base is connected to the input terminal of third complex multiplier, third complex multiplier
The first output end by complex adder group and first choice switch unit 102 be connected to 3 butterfly computation device of base it is first defeated
Outlet, the second output terminal of third complex multiplier are connected to first by displacement computing unit 103 and complex adder group and answer
The third output end of second input terminal of number adder, the second complex multiplier is opened by displacement computing unit 103, first choice
It closes unit 102 and complex adder group is connected to the second input terminal of the second complex adder；
Specifically, as shown in figure 4, input terminal C (the third input terminal of 3 butterfly computation device of base) is connected to complex multiplier 2,
First output end of complex multiplier 2 is connected to the second input terminal of complex adder 8, the second output terminal of complex multiplier 2
The second input terminal of complex adder 9, the third of complex multiplier 2 are connected to by complex multiplier 5 and shift register 24
Output end is connected to selector 17 by complex multiplier 6 and shift register 25, and the output end of selector 17 is connected to plural number
Second input terminal of adder 10.
Set input terminal A at this time1It is corresponding to operational data be A "1=(ar1+ai1* j), input terminal B is corresponding to operation
Data are B "=(br+bi* j), input terminal C it is corresponding to operational data be C "=(cr+ci* j), then corresponding output result are as follows:
In formula, W1"=wr1+j*wi1, W2"=wr2+j*wi2,
The restructural butterfly computation device 100 of the present embodiment, further includes: the second selection switch unit 105, third selection switch
Unit 106 and the second shift register 107；Second selection switch unit 105 is set to the output end of control unit 101, and second
Select switch unit 105 be used for according to operational order Selecting operation mode, wherein operation mode include FFT operation mode and
IFFT operation mode；Third selection switch unit 106 is set to the input terminal of twiddle factor, and third selects switch unit 106 to connect
Be connected to the input terminal of the first complex multiplier, third select switch unit 106 be used to being selected according to operation mode rotation because
Subtype, twiddle factor type include the first twiddle factor type and the second twiddle factor type, the first twiddle factor type pair
IFFT operation mode should be corresponded in FFT operation mode, the second twiddle factor type；Second shift register 107 is used for when fortune
When calculation mode is IFFT mode, shifting function will be carried out to operational data.
Further, third selects switch unit 106 further include: phase inverter；Phase inverter is set to the first complex multiplier
Between third selection switch 106, phase inverter is used for when carrying out IFFT operation, and the highest order for treating operational data imaginary part executes
Inversion operation.
Specifically, as shown in Fig. 2, the second shift register 107 includes shift register 28, shift register 29, displacement
Register 30 and shift register 31, the second selection switch unit 105 includes selector 34, selector 35,36 and of selector
Selector 37, a corresponding input terminal are connected to input terminal A1, input terminal B, input terminal C and input terminal A2, another is defeated
Enter end and is connected to shift register 28, shift register 29, shift register 30 and shift register 31.Referred to by operation
The conducting for enabling control the second selection switch unit 105, handles the data of input terminal, when needing to carry out FFT operation, control
Unit 101 will directly be inputted by operational order to operational data, and when needing to carry out IFFT operation, control unit 101 passes through fortune
The second shift register 107 will be transmitted to operational data by calculating instruction, and the exponent to operational data is moved right one, be carried out
Shifting function.
It includes selector 26 and selector 27 that third, which selects switch unit 106, and one of third selection switch unit 106 is defeated
Enter the input terminal that end is set to twiddle factor, another input terminal of third selection switch unit 106 is connected to by phase inverter
The input terminal of twiddle factor, corresponding, phase inverter includes that phase inverter 32 and phase inverter 33 pass through control when carrying out FFT operation
Instruction, the conducting of control selections device 26 and selector 27, directly by twiddle factor W1And W2It directly inputs complex multiplier 1 and answers
Number multipliers 2, when carrying out IFFT operation, by control instruction, using phase inverter by the highest order of the imaginary part in twiddle factor
It is negated, then is transmitted to complex multiplier 1 and complex multiplier 2.
The present invention has carried out Method at Register Transfer Level to the restructural butterfly computation device in the present embodiment with Verilog language
The description of (Register Transfer Level, RTL), and with Virtex-7 series xc7v2000tflg1925-1 development board,
Synthesis, layout, wiring, realization have been carried out on Vivado2016.3 platform, obtained resource occupation table, as shown in table 1.
Table 1
Technical solution in the present invention is compared into a kind of (such as " high-performance single precision with existing 3 butterfly computation device of base
The design and realization of floating-point basis -3 butterfly computation member " in 3 butterfly computation device of base), the corresponding resource of existing 3 butterfly computation device of base
Table is occupied, as shown in table 2.
Table 2
| Resource name | Resource occupation amount (a) | Resource occupation ratio (%) |
| Slices | 12484 | 49 |
| SlicesFlipFlop | 7166 | 14 |
| LUTs | 20154 | 40 |
Wherein, the LUTs in table 1 is 17213.
By Tables 1 and 2 it is found that restructural butterfly computation device resource occupation amount and resource occupation ratio in the present invention are bright
It is aobvious to reduce, be conducive to the overall performance for improving computing chip.Under 100MHz clock, the entirety of existing 3 butterfly computation device of base
Operation pipelining-stage is divided into 31 grades, and operation result transmission delay is 310ns, and the entirety of the restructural butterfly computation device in the present invention
Operation pipelining-stage is 25 grades, and the transmission delay of operation result is 250ns.Therefore, the restructural butterfly computation device in the present invention has
Conducive to the delay reduced in calculating process.
Operation is carried out for 972 operational data to operation points by simulation software, existing Non-2-power zero padding calculates
The corresponding simulation result of FFT method is as shown in figure 5, the corresponding simulation result of the present invention is as shown in Figure 6, wherein phase of the invention
It is -148.7721dB to error mean, maximum relative error is -140.6137dB.By comparing it is found that weighing in the present invention
The relative error of the operation result of structure butterfly computation device is better than existing Non-2-power zero padding and calculates FFT method, is conducive to improve
The computational accuracy of butterfly computation device.
Step in the present invention can be sequentially adjusted, combined, and deleted according to actual needs.
Unit in apparatus of the present invention can be combined, divided and deleted according to actual needs.
Although disclosing the present invention in detail with reference to attached drawing, it will be appreciated that, these descriptions are only exemplary, not
For limiting application of the invention.Protection scope of the present invention may include not departing from this hair by appended claims
For various modifications made by invention, remodeling and equivalent scheme in the case where bright protection scope and spirit.
Claims (9)
1. a kind of restructural butterfly computation device of multichannel hybrid base FFT, which is characterized in that the butterfly computation device includes: control unit
(101), first choice switch unit (102) and arithmetic element (104)；
Described control unit (101) is used to generate operational order to operational data according to what is received, wherein described to operand
According to including digital signal to be processed, twiddle factor and default twiddle factor coefficient；
The first choice switch unit (102) is used to select corresponding conduction mode according to the operational order；
The arithmetic element (104) is used for according to the conduction mode, carries out butterfly computation to operational data to described.
2. the restructural butterfly computation device of multichannel hybrid base FFT as described in claim 1, which is characterized in that the arithmetic element
It (104) include: two bases, 2 butterfly computation device, the first complex adder and the second complex adder；
The 2 butterfly computation device of base is used for according to described corresponding to operational data and the first choice switch unit (102)
The conduction mode carries out 2 butterfly computation of base；
Two 2 butterfly computation devices of base are also used to according to the corresponding conducting mould of the first choice switch unit (102)
Formula forms a 3 butterfly computation device of base, 3 butterfly of base with first complex adder and second complex adder
Arithmetic unit is used to carry out 3 butterfly computation of base to operational data to described.
3. the restructural butterfly computation device of multichannel hybrid base FFT as claimed in claim 2, which is characterized in that 2 butterfly of the base fortune
Calculating device includes: the first complex multiplier, third complex adder and complex subtraction device；
The first input end of the 2 butterfly computation device of base be connected to the third complex adder first input end and
The first input end of the complex subtraction device is connected to by the first choice switch unit (102), the third plural number adds
The output end of musical instruments used in a Buddhist or Taoist mass switchs the first output end that (102) are connected to the 2 butterfly computation device of base by the first choice, described
The output end of complex subtraction device is connected to the second of the 2 butterfly computation device of base by the first choice switch unit (102)
Output end；
The second input terminal and the twiddle factor of the 2 butterfly computation device of base are connected to first complex multiplier
Input terminal, the output end of first complex multiplier are connected to the second input terminal and the institute of the third complex adder
State the second input terminal of complex subtraction device.
4. the restructural butterfly computation device of multichannel hybrid base FFT as claimed in claim 3, which is characterized in that further include: displacement meter
It calculates unit (103)；
The displacement computing unit (103) is used for when carrying out 3 butterfly computation of base, according to the operational order, to described to be shipped
Count according to being shifted, and the arithmetic element (104) will be sent to operational data described in after displacement, wherein it is described to
Operational data includes digital signal to be processed, twiddle factor and default twiddle factor coefficient；
The arithmetic element (104) is also used to: according to the conduction mode, a 3 butterfly computation device of base is formed, to displacement
Afterwards it is described to operational data carry out 3 butterfly computation of base.
5. the restructural butterfly computation device of multichannel hybrid base FFT as claimed in claim 4, which is characterized in that 3 butterfly of the base fortune
Calculating device includes: the second complex multiplier, third complex multiplier, complex adder group, first complex adder and described
Second complex adder；
The first input end of the 3 butterfly computation device of base passes through the complex adder group and the first choice switch unit
(102) it is connected to the first output end of shown 3 butterfly computation device of base, the first input end of the 3 butterfly computation device of base is also
It is connected to the first input end of first complex adder, the output end of first complex adder is selected by described first
Select the second output terminal that switch unit (102) is connected to the 3 butterfly computation device of base, described the of the 3 butterfly computation device of base
One input terminal is also attached to the first input end of second complex adder, and the output end of second complex adder passes through
The first choice switch unit (102) is connected to the third output end of the 3 butterfly computation device of base；
Second input terminal of the 3 butterfly computation device of base is connected to the input terminal of second complex multiplier, and described second is multiple
First output end of number multiplier is connected to described by the complex adder group and the first choice switch unit (102)
The second output terminal of first output end of 3 butterfly computation device of base, second complex multiplier is calculated by the displacement
Unit (103), the first choice switch unit (102) and the complex adder group are connected to first complex adder
The second input terminal, the third output end of second complex multiplier passes through the displacement computing unit (103), described first
Selection switch unit (102) and the complex adder group are connected to the second input terminal of second complex adder；
The third input terminal of the 3 butterfly computation device of base is connected to the input terminal of the third complex multiplier, and the third is multiple
First output end of number multiplier is connected to described by the complex adder group and the first choice switch unit (102)
The second output terminal of first output end of 3 butterfly computation device of base, the third complex multiplier is calculated by the displacement
Unit (103) and the complex adder group are connected to second input terminal of first complex adder, and described second
The third output end of complex multiplier passes through the displacement computing unit (103), the first choice switch unit (102) and institute
Second input terminal that complex adder group is connected to second complex adder is stated,
Wherein, second complex multiplier is first complex multiplier of a 2 butterfly computation device of base, described the
Three complex multipliers are first complex multiplier of another 2 butterfly computation device of base, and complex adder group includes two
The third complex adder of a 2 butterfly computation device of the base and the complex subtraction device.
6. the restructural butterfly computation device of multichannel hybrid base FFT as claimed in claim 4, which is characterized in that the displacement calculates
Unit (103) includes: the 4th complex multiplier and the first shift register；
4th complex multiplier is for calculating the digital signal, the twiddle factor and the default twiddle factor system
Product between number；
First shift register is connected to the 4th complex multiplier, and first shift register to described for multiplying
Product carries out shifting function, and the product after displacement is sent to the arithmetic element (104),
Wherein, the default twiddle factor coefficient be twiddle factor coefficient with 2 product, the shifting function for data exponent to
Move right one.
7. the restructural butterfly computation device of multichannel hybrid base FFT as claimed in claim 6, which is characterized in that the displacement calculates
Unit (103) further include: selection switch；
The selection switch is for controlling the conducting and shutdown of the 4th complex multiplier output according to the conduction mode.
8. the restructural butterfly computation device of multichannel hybrid base FFT as claimed in claim 3, which is characterized in that further include: the second choosing
Select switch unit (105), third selection switch unit (106) and the second shift register (107)；
Second selection switch unit (105) is set to the output end of described control unit (101), the second selection switch
Unit (105) be used for according to the operational order Selecting operation mode, wherein the operation mode include FFT operation mode and
IFFT operation mode；
Third selection switch unit (106) is set to the input terminal of the twiddle factor, and the third selects switch unit
(106) it is connected to the input terminal of first complex multiplier, third selection switch unit (106) is used for according to institute
Operation mode selection twiddle factor type is stated, the twiddle factor type includes the first twiddle factor type and the second twiddle factor
Type, the first twiddle factor type correspond to the FFT operation mode, and the second twiddle factor type corresponds to described
IFFT operation mode；
Second shift register (107) is used for when the operation mode is the IFFT mode, will be described to operand
According to progress shifting function.
9. the restructural butterfly computation device of multichannel hybrid base FFT as claimed in claim 8, which is characterized in that the third selection
Switch unit (106) further include: phase inverter；
The phase inverter is set between first complex multiplier and third selection switch (106), the phase inverter
For executing inversion operation to the highest order to operational data imaginary part when carrying out IFFT operation.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111027013A (en) * | 2019-12-10 | 2020-04-17 | 重庆邮电大学 | Multi-mode configurable FFT processor and method supporting DAB and CDR |
| CN111445017A (en) * | 2020-03-23 | 2020-07-24 | 天津芯海创科技有限公司 | Operation method and device |
| CN111538945A (en) * | 2020-04-24 | 2020-08-14 | 合肥工业大学 | Operation result quick checking system based on reconfigurable dish calculation unit |
| CN111782581A (en) * | 2020-07-30 | 2020-10-16 | 中国电子科技集团公司第十四研究所 | Reconfigurable signal processing arithmetic unit and recombination unit based on same |
| CN112231626A (en) * | 2020-10-19 | 2021-01-15 | 南京宁麒智能计算芯片研究院有限公司 | FFT processor |
| CN113010147A (en) * | 2021-02-24 | 2021-06-22 | 歌尔微电子股份有限公司 | FFT arithmetic device and microphone |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050015420A1 (en) * | 2003-07-18 | 2005-01-20 | Gibb Sean G. | Recoded radix-2 pipeline FFT processor |
| US20080155003A1 (en) * | 2006-12-21 | 2008-06-26 | National Chiao Tung University | Pipeline-based reconfigurable mixed-radix FFT processor |
| CN102012800A (en) * | 2010-12-01 | 2011-04-13 | 华东师范大学 | Mixed base 2/4 butterfly processing core |
| CN102073621A (en) * | 2011-01-19 | 2011-05-25 | 东南大学 | Butterfly-shaped radix-4 unit circuit applied in FFT/IFFT (Fast Fourier Transform Algorithm/Inverse Fast Fourier Transform) and processing method thereof |
| CN201993753U (en) * | 2011-01-19 | 2011-09-28 | 东南大学 | Radix-4 butterfly unit circuit applied to FFT/IFFT |
| CN103493039A (en) * | 2012-04-28 | 2014-01-01 | 华为技术有限公司 | Data processing method and related device |
| CN104657334A (en) * | 2014-12-29 | 2015-05-27 | 南京大学 | FFT (Fast Fourier Transform) radix-2-4-8 mixed-radix butterfly operator and application thereof |
| CN107133194A (en) * | 2017-04-11 | 2017-09-05 | 西安电子科技大学 | Configurable FFT/IFFT coprocessors based on hybrid radix |
| CN107391439A (en) * | 2017-07-11 | 2017-11-24 | 创达特（苏州）科技有限责任公司 | A kind of processing method of configurable Fast Fourier Transform (FFT) |
-
2018
- 2018-08-06 CN CN201810886891.3A patent/CN109117188B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050015420A1 (en) * | 2003-07-18 | 2005-01-20 | Gibb Sean G. | Recoded radix-2 pipeline FFT processor |
| US20080155003A1 (en) * | 2006-12-21 | 2008-06-26 | National Chiao Tung University | Pipeline-based reconfigurable mixed-radix FFT processor |
| CN102012800A (en) * | 2010-12-01 | 2011-04-13 | 华东师范大学 | Mixed base 2/4 butterfly processing core |
| CN102073621A (en) * | 2011-01-19 | 2011-05-25 | 东南大学 | Butterfly-shaped radix-4 unit circuit applied in FFT/IFFT (Fast Fourier Transform Algorithm/Inverse Fast Fourier Transform) and processing method thereof |
| CN201993753U (en) * | 2011-01-19 | 2011-09-28 | 东南大学 | Radix-4 butterfly unit circuit applied to FFT/IFFT |
| CN103493039A (en) * | 2012-04-28 | 2014-01-01 | 华为技术有限公司 | Data processing method and related device |
| CN104657334A (en) * | 2014-12-29 | 2015-05-27 | 南京大学 | FFT (Fast Fourier Transform) radix-2-4-8 mixed-radix butterfly operator and application thereof |
| CN107133194A (en) * | 2017-04-11 | 2017-09-05 | 西安电子科技大学 | Configurable FFT/IFFT coprocessors based on hybrid radix |
| CN107391439A (en) * | 2017-07-11 | 2017-11-24 | 创达特（苏州）科技有限责任公司 | A kind of processing method of configurable Fast Fourier Transform (FFT) |
Non-Patent Citations (4)
| Title |
|---|
| X.SHIH 等: "48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-32 and Radix-23 Design Approaches", 《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS》 * |
| 刘德福: "通用高速FFT/IFFT处理器的设计与实现", 《中国优秀硕士学位论文全文数据库-信息科技辑》 * |
| 马翠梅: "低复杂度混合基FFT研究与设计", 《中国优秀硕士学位论文全文数据库-信息科技辑》 * |
| 马翠梅等: "一种小面积的基-3蝶形单元设计", 《北京理工大学学报》 * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111027013A (en) * | 2019-12-10 | 2020-04-17 | 重庆邮电大学 | Multi-mode configurable FFT processor and method supporting DAB and CDR |
| CN111027013B (en) * | 2019-12-10 | 2023-05-26 | 重庆邮电大学 | Multimode configurable FFT processor and method supporting DAB and CDR |
| CN111445017A (en) * | 2020-03-23 | 2020-07-24 | 天津芯海创科技有限公司 | Operation method and device |
| CN111538945A (en) * | 2020-04-24 | 2020-08-14 | 合肥工业大学 | Operation result quick checking system based on reconfigurable dish calculation unit |
| CN111538945B (en) * | 2020-04-24 | 2023-03-14 | 合肥工业大学 | Operation result quick checking system based on reconfigurable dish calculation unit |
| CN111782581A (en) * | 2020-07-30 | 2020-10-16 | 中国电子科技集团公司第十四研究所 | Reconfigurable signal processing arithmetic unit and recombination unit based on same |
| CN111782581B (en) * | 2020-07-30 | 2024-01-12 | 中国电子科技集团公司第十四研究所 | Reconfigurable signal processing operation unit and recombination unit based on same |
| CN112231626A (en) * | 2020-10-19 | 2021-01-15 | 南京宁麒智能计算芯片研究院有限公司 | FFT processor |
| CN113010147A (en) * | 2021-02-24 | 2021-06-22 | 歌尔微电子股份有限公司 | FFT arithmetic device and microphone |
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