CN109104072B - Compensation circuit for input voltage sampling - Google Patents
Compensation circuit for input voltage sampling Download PDFInfo
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- CN109104072B CN109104072B CN201811072499.1A CN201811072499A CN109104072B CN 109104072 B CN109104072 B CN 109104072B CN 201811072499 A CN201811072499 A CN 201811072499A CN 109104072 B CN109104072 B CN 109104072B
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- 238000004088 simulation Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 1
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- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
- H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0016—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters
- H02M1/0022—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters the disturbance parameters being input voltage fluctuations
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
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Abstract
The invention provides a compensation circuit for sampling input voltage, which comprises a preset voltage V1, a pin UVP, a pin GT, a current mirror and a clamping module.
Description
Technical Field
The invention relates to the technical field of switching power supplies, in particular to a compensation circuit for sampling input voltage.
Background
With the rapid development of electronic technology, besides a main power control circuit necessary for a complete-function switching power supply control process, other functions such as undervoltage protection and feedforward compensation are often required to be included. In patent No. ZL201710678498.0 and publication No. CN107302214A, an input undervoltage protection circuit is proposed, the simplified block diagram of the whole application circuit is shown in fig. 1, and the main power topology is a known technology and comprises devices such as an input voltage Vin, an output voltage Vout, a capacitor C VIN, voltage divider resistors Rs1 and Rs2, a controller, a main power transformer, a main power tube M1, a diode Dout, a capacitor C2, an inductor L1, a capacitor C3 and the like. The block diagrams of the clamping module and the current mirror module are shown in fig. 2, and the clamping module and the current mirror module comprise a pin UVP, a pin CS, a current mirror and a clamping module, and the functions of the clamping module and the current mirror module in the UVP pin are utilized to realize the feedforward compensation function of the input voltage. The basic principle of the feedforward compensation function is as follows:
If V in≥V1(1+Rs1/Rs2 is satisfied), the clamping module clamps the voltage of the pin UVP to V1, and discharges the redundant current I LC on the voltage divider, where the following relation is given:
the current mirror module generates the current I LC into I1 according to the mirror proportion K, namely
I1 flows through resistor R LC via pin CS to generate compensation voltage V RLC＝I1·RLC, implementing the feed-forward compensation function.
In the prior art shown in fig. 1 and 2, the feedforward compensation function is fully time-efficient, i.e. feedforward compensation is introduced during both the on and off phases of the power tube M1, and the voltage on the pin CS is equal to the feedforward compensation voltage V RLC instead of zero due to the zero voltage on the sampling resistor Rcs during the off phase of the power tube M1; in the stage of starting the power tube M1, the voltage on the pin CS is the voltage superposition feedforward compensation voltage V RLC on the sampling resistor Rcs. As shown in fig. 3, a basic schematic block diagram of a known PWM mode control is shown: the non-inverting input end of the PWM comparator CMP_PWM is a voltage signal VFB_CS generated by the output voltage sampling optocoupler feedback pin FB of the controller through the PWM input gain module, and the inverting input end of the PWM comparator CMP_PWM is a voltage signal VCS on the controller pin CS. Under the wide-range direct current input voltage, in order to meet the consistency of high-low voltage overpower points, when the high-voltage is input, the added feedforward compensation voltage V RLC is larger, during the turn-off period of a power tube, if the voltage V RLC on a pin CS is larger than VFB_CS, a signal of a PWM comparator CMP_PWM output toff_L is always at a low level and is sent to a clear end Clr_L of a D trigger DFF, an output end Q of the D trigger is at a low level, a GT pin is at a low level, the power tube is not always turned on, so that a power tube driving signal is lost, and the problem caused by the driving signal loss is that: the primary side is not transferred to the secondary side, so that the output of the system is powered down, the output ripple is large, an output loop is unstable, and the requirement of the output index of the system is not met.
The waveforms simulating the flyback system in the prior art are shown in fig. 4, namely waveforms of CS, vfb_cs, toff_l, CLK, GT and output VOUT sequentially from top to bottom, during the period of GT turn-off, the voltage of the CS pin is 164.8mV due to the feedforward compensation introduced, the value of the voltage is greater than that of vfb_cs, it can be seen from two vertical lines in the middle that GT should be turned to a high level on the rising edge of CLK, however, the voltage of the pin CS is greater than vfb_cs, and toff_l is always zero, so that GT is always a low level, the driving signal GT is caused to be lack, no energy is transferred from the primary side to the secondary side, and the output VOUT of the system is further caused to be powered down, until the voltage of the CS pin is less than vfb_cs, GT becomes a high level, the power tube M1 is turned on, the voltage of the CS pin rises, when the voltage of the CS pin rises to be higher than vfb_cs, the energy stored on the primary side is transferred to the secondary side, the output voltage of the system rises, and thus the ripple of the output VOUT is caused to be large, and the simulated ripple value of VOUT is not meeting the requirement 300.
Disclosure of Invention
Accordingly, the technical problem to be solved by the invention is to provide a compensation circuit for sampling input voltage, which is used for providing feedforward compensation current only in the power tube starting stage, realizing the compensation function of sampling input voltage, and avoiding the problems that the power tube is not started, the system output ripple wave is large and the system output index is not met due to the fact that feedforward compensation is introduced too much during the power tube turning-off period, especially under high-voltage input.
The technical scheme for solving the technical problems is as follows:
the compensation circuit 100 for sampling input voltage comprises a preset voltage V1, a pin UVP, a pin GT, a current mirror 101 and a clamping module;
one end of the current mirror 101 is connected with the clamping module to form a node ILC for receiving an input voltage sampling signal; the other end of the current mirror 101 outputs feedforward compensation current, so that feedforward compensation voltage is generated on an external feedforward compensation resistor, and a feedforward compensation function is realized;
The clamping module is connected with a preset voltage V1, and the preset voltage V1 is a clamping reference of the clamping module; the clamping module is also connected with the pin GT and the pin UVP, and clamps the voltage of the UVP pin to a preset voltage V1 when the partial pressure of an external voltage divider of the pin UVP is greater than or equal to V1, namely V UVP = V1 at the moment.
Preferably, as an implementation manner of the clamping module, the clamping module 102 includes a PMOS tube PM1, a PMOS tube PM2, an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, and an NMOS tube NM4, where a source of the PMOS tube PM1 is connected to a preset voltage V1, and a gate of the PMOS tube PM1 and a drain of the PMOS tube PM1 are connected to a gate of the PMOS tube PM2 and a drain of the NMOS tube NM 1; the source electrode of the PMOS tube PM2 is connected with the pin UVP, the drain electrode of the PMOS tube PM2 is connected with the grid electrode of the NMOS tube NM1, the grid electrode and the drain electrode of the NMOS tube NM2 and the grid electrode of the NMOS tube NM3, the drain electrode of the NMOS tube NM3 is connected with the source electrode of the NMOS tube NM4, the grid electrode of the NMOS tube NM4 is connected with the pin GT, and the drain electrode of the NMOS tube NM4 is used as the output of the clamping module 102 to form a node ILC; the sources of the PMOS tube NM1, the PMOS tube NM2 and the NMOS tube NM3 are connected with the reference ground.
Preferably, as another embodiment of the clamping module, the clamping module 202 includes a PMOS tube PM1, a PMOS tube PM2, an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, and an NMOS tube NM4, wherein a source of the PMOS tube PM1 is connected to a preset voltage V1, and a gate of the PMOS tube PM1 and a drain of the PMOS tube PM1 are connected to a gate of the PMOS tube PM2 and a drain of the NMOS tube NM 1; the source electrode of the PMOS tube PM2 is connected with the pin UVP, the drain electrode of the PMOS tube PM2 is connected with the drain electrode of the NMOS tube NM4, the grid electrode of the NMOS tube NM4 is connected with the pin GT, the source electrode of the NMOS tube NM4 is connected with the grid electrode of the NMOS tube NM1, the grid electrode and the drain electrode of the NMOS tube, and the grid electrode of the NMOS tube NM3, and the drain electrode of the NMOS tube NM3 is used as the output of the clamping module 202 to form a node ILC; the sources of the NMOS tube NM1, the NMOS tube NM2 and the NMOS tube NM3 are connected with the reference ground.
The principle of clamping and generating ILC by the circuit is described in detail in patent document with patent number ZL 201710678498.0, publication number CN107302214A, and patent name of an input undervoltage protection circuit, and the invention is not repeated.
In the clamping module 102, the gate of the NMOS transistor NM4 is connected with the pin GT, and the NMOS transistor NM4 is turned on only when the pin GT is at a high level, so that the feedforward current ILC is generated. The feedforward compensation current I1 is only available during the power transistor turn-on phase, i.e. the pin GT is high, and the circuit structure is simple. The feedforward compensation current is set as I 1, the resistance value of the external feedforward compensation resistor of the circuit is set as R LC, and the generated feedforward compensation voltage value is set as V RLC＝I1·RLC.
The feed-forward compensation current I 1 is calculated as follows:
Where K is the current mirror ratio of the current mirror 101, V in is the input voltage, and R s1、Rs2 is the divider resistance of the external voltage divider.
Fig. 7 is a simulation waveform of the input voltage sampling compensation circuit in the application scenario of the optocoupler feedback flyback switching power supply of the present invention, and comparing fig. 4, it can be seen that only during the period that GT is high level, there is feedforward compensation, the driving GT is normally turned on and off, no missing phenomenon, the loop is stable, the ripple of the output voltage VOUT is small, only 70mV, and the requirement of the system output ripple index is met.
Preferably, as another embodiment of the clamping module, the NMOS transistor NM4 of the clamping module 202 is connected to the drain of the PMOS transistor PM2, the gate of the NMOS transistor NM4 is connected to the pin GT, and the source of the NMOS transistor NM4 is connected to the gate of the NMOS transistor NM1, the gate and drain of the NMOS transistor NM2, and the gate of the NMOS transistor NM 3. The drain of NMOS transistor NM3 is used as the output of clamp block 202 to form node ILC. Compared with the clamp module 102, the NMOS transistor NM4 has different circuit positions, and the same function is realized, i.e. only when the pin GT is at a high level, the NMOS transistor NM4 is turned on, the NMOS transistor NM3 is turned on, and the feedforward current ILC is generated.
The circuit principle, the action and the like of the invention are analyzed, and the beneficial effects of the invention are summarized as follows:
1. Compared with the prior art, as the NMOS tube NM4 is additionally arranged, the gate electrode of the NMOS tube NM4 is connected with the pin GT, and the feedforward compensation current can be introduced only in the power tube starting stage, so that the circuit is few in implementation mode, small in area, low in cost and reliable in function.
2. The feedforward compensation current is only introduced in the power tube starting stage, so that the compensation function of input voltage sampling can be normally realized, and the problems that the power tube is not started, the system output ripple is large and the system output index requirement is not met due to the fact that the feedforward compensation is excessively introduced during the power tube turning-off period, particularly under high-voltage input, can be avoided.
Drawings
FIG. 1 is a simplified diagram of a prior art application circuit for a switching power supply with an external feedforward compensation circuit;
FIG. 2 is a circuit block diagram of a prior art current mirror and clamp module;
FIG. 3 is a schematic block diagram of a basic circuit of a prior art PWM mode control;
FIG. 4 is a simulation waveform of an optocoupler feedback flyback switching power supply of an external feedforward compensation circuit in the prior art;
FIG. 5 is a simplified circuit diagram of the present invention in an optocoupler feedback flyback switching power supply application scenario;
FIG. 6 is a circuit diagram of the input voltage sampling compensation circuit 100 of the present invention;
FIG. 7 is a simulation waveform of the compensation circuit for sampling input voltage in the application scenario of the optical coupling feedback flyback switching power supply;
FIG. 8 is a schematic circuit diagram of a clamping module 102 according to an embodiment of the invention;
Fig. 9 is a schematic circuit diagram of the second clamp module 202 according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent.
Example 1
Fig. 5 is a simplified circuit diagram of the present invention in an application scenario of the optical coupler feedback flyback power supply, omitting the secondary optical coupler and TL431 and the loop compensation portion. The compensation circuit for input voltage sampling according to the present invention is a circuit in the controller 10, and other circuits in the controller 10 are not related to the present invention and are not described herein. The main power topology in fig. 5 is a known technology, and includes an input voltage V in, an output voltage V out, a capacitor C VIN, voltage divider resistors R s1 and R s2, a controller 10, a main power transformer, a main power tube M1, a diode D OUT, a capacitor C 2, an inductor L 1, and a capacitor C 3. The GT pin is a driving output of the controller 10 and is used for controlling the on and off of the power tube M1; the FB pin is an optocoupler feedback pin, when the output voltage Vout rises, the optocoupler current is increased, the voltage of the FB pin is reduced, and conversely, when the output voltage Vout falls, the optocoupler current is reduced, and the voltage of the FB pin is increased; the CS pin is a current sampling pin, and the peak current flowing through the power tube M1 is determined by detecting the voltage of the current sampling resistor R CS; the UVP pin detects the input voltage V in through voltage divider resistors R s1 and R s2, the feedforward compensation function is realized by dividing the voltage into voltage segments, feedforward compensation current flows out from the CS pin, and compensation voltage V RLC is generated on resistor R LC. Other pin connections and functions of the controller shown in fig. 5 are not relevant to the present invention, and are not shown in fig. 5.
Fig. 6 is a circuit block diagram of a compensation circuit 100 for input voltage sampling according to the present invention, which includes a preset voltage V1, a pin GT, a pin UVP, a current mirror 101, and a clamp module 102.
One end of the current mirror 101 is connected with the clamping module 102 to form a node ILC for receiving an input voltage sampling signal; the other end of the current mirror 101 is connected to the pin CS for outputting the feedforward compensation current I1.
The clamp module 102 is connected to a preset voltage V1, and the preset voltage V1 is a clamp reference of the clamp module 102. The clamping module 102 is further connected to the pin GT and the pin UVP, and clamps the voltage of the UVP pin to a preset voltage V1 when the partial voltage of the external voltage divider of the pin UVP is greater than or equal to V1.
Fig. 8 is a schematic circuit diagram of the clamp module 102, which includes PMOS transistors PM1, PM2, and NMOS transistors NM1, NM2, NM3, NM4. The source electrode of PM1 is connected with a preset voltage V1, and the grid electrode of PM1 and the drain electrode of PM1 are connected with the grid electrode of PM2 and the drain electrode of NM 1; the source of PM2 is connected with pin UVP, the drain of PM2 is connected with the grid of NM1, the grid and drain of NM2 and the grid of NM3, the drain of NM3 is connected with the source of NM4, the grid of NM4 is connected with pin GT, the drain of NM4 is used as the output of clamp module 102, forming node ILC; the sources of NM1, NM2, NM3 are connected to a reference ground. All PMOS and NMOS substrates are connected to their respective sources.
It should be noted that the principle of the circuit for clamping and generating ILC is described in detail in patent document with patent number ZL 201710678498.0 and publication number CN107302214A, and the patent name is an input undervoltage protection circuit, and the disclosure is not repeated. The operation of the compensation circuit for input voltage sampling is described below with reference to the accompanying drawings.
After the controller 10 is started, if V in≥V1(1+Rs1/Rs2 is satisfied), the controller 10 outputs a PWM modulation signal, the clamp module 102 clamps the voltage of the pin UVP to the reference voltage V1, the redundant current I UVP on the voltage divider is discharged, the NMOS transistor NM4 is additionally arranged at the drain electrode of the NM3, the gate electrode of the NM4 is connected with the pin GT, the NM4 is turned on only when the pin GT is at a high level, that is, the power transistor M1 is turned on, the discharged current I UVP can generate the current I LC according to a certain proportion through a current mirror image, that is, the control output ILC is generated in the stage of turning on the power transistor M1, and in order to facilitate description principles, in embodiment 1, the following relation is given by I LC＝IUVP:
the current mirror 101 generates I1 from the output current I LC in the mirror proportion K, i.e
I1 flows through an external feedforward compensation resistor R LC through a pin CS to generate a compensation voltage V RLC＝I1·RLC, so that a feedforward compensation function is realized. Because the NMOS tube NM4 is additionally arranged for controlling, the circuit only introduces feedforward compensation current in the power tube starting stage, the compensation function of input voltage sampling can be normally realized, and the problems that the power tube is not started, the system output ripple is large and the system output index requirement is not met due to the fact that feedforward compensation is excessively introduced during the power tube turn-off period, particularly under high-voltage input, can be avoided.
The specific circuit structure of the current mirror 101 in fig. 6 is implemented in many ways in the prior art, and the working principle is simple, and the present invention is not described in detail.
Example two
As shown in fig. 9, a schematic circuit diagram of the clamp module 202 of the present embodiment is different from that of embodiment 1 in that the NMOS transistor NM4 in the clamp module 202 of embodiment 2 is connected to the drain of the PMOS transistor PM2, the gate of NM4 is connected to the pin GT, and the source of NM4 is connected to the gate of NM1, the gate and drain of NM2, and the gate of NM 3. The drain of NM3 serves as the output of clamp block 102, forming node ILC. Compared with the embodiment 1, the NM4 tube is positioned at a different circuit position, controls the inflow time of the discharged current I UVP, enables NM3 to be conducted only when the pin GT is at a high level, and the discharged current I UVP generates I LC according to a certain proportion through current mirror image, so that the final feedforward current ILC is generated.
Although the implementation is different, the final objective is to generate the feedforward current ILC only during the on-phase of the power transistor M1, and the ILC is output to the current mirror module 101 to generate the final feedforward compensation current I1. I1 flows through resistor R LC via pin CS to generate compensation voltage V RLC＝I1·RLC, implementing the feed-forward compensation function.
In addition to the above, there are many ways of controlling the feedforward compensation current timing, whether the bleed-off current I UVP, the feedforward current I LC or the final feedforward compensation current I1, so long as the final purpose is to add the feedforward compensation function during the power-on phase, it should be noted that, for those skilled in the art, several modifications and adaptations made without departing from the principles of the present invention should be considered as the protection scope of the present invention.
Claims (2)
1. A compensation circuit for input voltage sampling, characterized by: the device comprises a preset voltage V1, a pin UVP, a pin GT, a current mirror and a clamping module;
One end of the current mirror is connected with the clamping module to form a node ILC for receiving an input voltage sampling signal; the other end of the current mirror outputs feedforward compensation current, so that feedforward compensation voltage is generated on an external feedforward compensation resistor, and a feedforward compensation function is realized;
The clamping module is connected with a preset voltage V1, and the preset voltage V1 is a clamping reference of the clamping module; the clamping module is also connected with the pin GT and the pin UVP, and clamps the voltage of the UVP pin to a preset voltage V1 when the divided voltage of the external voltage divider of the pin UVP is greater than or equal to the preset voltage V1;
The clamping module comprises a PMOS tube PM1, a PMOS tube PM2, an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3 and an NMOS tube NM4, wherein the source electrode of the PMOS tube PM1 is connected with a preset voltage V1, and the grid electrode of the PMOS tube PM1 and the drain electrode of the PMOS tube PM1 are connected with the grid electrode of the PMOS tube PM2 and the drain electrode of the NMOS tube NM 1; the source electrode of the PMOS tube PM2 is connected with the pin UVP, the drain electrode of the PMOS tube PM2 is connected with the grid electrode of the NMOS tube NM1, the grid electrode and the drain electrode of the NMOS tube NM2 and the grid electrode of the NMOS tube NM3, the drain electrode of the NMOS tube NM3 is connected with the source electrode of the NMOS tube NM4, the grid electrode of the NMOS tube NM4 is connected with the pin GT, and the drain electrode of the NMOS tube NM4 is used as the output of the clamping module to form a node ILC; the sources of the PMOS tube NM1, the PMOS tube NM2 and the NMOS tube NM3 are connected with the reference ground.
2. A compensation circuit for input voltage sampling, characterized by: the device comprises a preset voltage V1, a pin UVP, a pin GT, a current mirror and a clamping module;
One end of the current mirror is connected with the clamping module to form a node ILC for receiving an input voltage sampling signal; the other end of the current mirror outputs feedforward compensation current, so that feedforward compensation voltage is generated on an external feedforward compensation resistor, and a feedforward compensation function is realized;
The clamping module is connected with a preset voltage V1, and the preset voltage V1 is a clamping reference of the clamping module; the clamping module is also connected with the pin GT and the pin UVP, and clamps the voltage of the UVP pin to a preset voltage V1 when the divided voltage of the external voltage divider of the pin UVP is greater than or equal to the preset voltage V1;
The clamping module comprises a PMOS tube PM1, a PMOS tube PM2, an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3 and an NMOS tube NM4, wherein the source electrode of the PMOS tube PM1 is connected with a preset voltage V1, and the grid electrode of the PMOS tube PM1 and the drain electrode of the PMOS tube PM1 are connected with the grid electrode of the PMOS tube PM2 and the drain electrode of the NMOS tube NM 1; the source electrode of the PMOS tube PM2 is connected with the pin UVP, the drain electrode of the PMOS tube PM2 is connected with the drain electrode of the NMOS tube NM4, the grid electrode of the NMOS tube NM4 is connected with the pin GT, the source electrode of the NMOS tube NM4 is connected with the grid electrode of the NMOS tube NM1, the grid electrode and the drain electrode of the NMOS tube NM2 and the grid electrode of the NMOS tube NM3, and the drain electrode of the NMOS tube NM3 is used as the output of the clamping module to form a node ILC; the sources of the NMOS tube NM1, the NMOS tube NM2 and the NMOS tube NM3 are connected with the reference ground.
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| CN201811072499.1A CN109104072B (en) | 2018-09-14 | 2018-09-14 | Compensation circuit for input voltage sampling |
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| CN201811072499.1A CN109104072B (en) | 2018-09-14 | 2018-09-14 | Compensation circuit for input voltage sampling |
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| CN109104072B true CN109104072B (en) | 2024-05-17 |
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| US8143812B2 (en) * | 2009-06-25 | 2012-03-27 | Texas Instruments Incorporated | Clamp to enable low voltage switching for high voltage terminal applications |
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| CN102545162A (en) * | 2010-12-09 | 2012-07-04 | 无锡华润上华半导体有限公司 | Lithium battery protection circuit |
| CN103001490A (en) * | 2012-12-20 | 2013-03-27 | 西安电子科技大学 | Direct current (DC)-DC conversion controller with overload protection function |
| CN105610306A (en) * | 2016-03-01 | 2016-05-25 | 深圳南云微电子有限公司 | Secondary feedback control method and secondary feedback control circuit |
| CN107302214A (en) * | 2017-08-10 | 2017-10-27 | 广州金升阳科技有限公司 | A kind of input undervoltage protection circuit |
| CN208904873U (en) * | 2018-09-14 | 2019-05-24 | 深圳南云微电子有限公司 | A kind of compensation circuit of input voltage sampling |
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| CN109104072A (en) | 2018-12-28 |
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