CN109103204A - A kind of array substrate and preparation method thereof - Google Patents
A kind of array substrate and preparation method thereof Download PDFInfo
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- CN109103204A CN109103204A CN201810863399.4A CN201810863399A CN109103204A CN 109103204 A CN109103204 A CN 109103204A CN 201810863399 A CN201810863399 A CN 201810863399A CN 109103204 A CN109103204 A CN 109103204A
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- metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The present invention provides a kind of array substrate and preparation method thereof, array substrate includes: substrate；Thin film transistor (TFT) square on the substrate is set；The first square on the substrate heavily doped region is set；The first metal layer above first heavily doped region is set；Second metal layer above the first metal layer is set；Third metal layer above the second metal layer is set；Wherein, at least three in first heavily doped region, the first metal layer, the second metal layer and the third metal layer forms shunt capacitance.The present invention spatially separates thin film transistor (TFT) with storage capacitance, to form storage capacitance using at least three in heavily doped region, the first metal layer, second metal layer and third metal layer, to reduce the area of single pixel, and then promote the pixel density of screen.
Description
Technical field
The present invention relates to display fields, and in particular to a kind of array substrate and preparation method thereof.
Background technique
Organic light emitting diode display (Organic Light-Emitting Diode, abbreviation OLED) has spontaneous
The features such as light, contrast are high, thickness is thin, visual angle is wide, reaction speed is fast, construction and processing procedure are simple, it is considered to be next generation's display
The emerging technology of device.OLED is divided into passive matrix (abbreviation PMLOED) and active array type (AMOLED) according to driving method,
Wherein, AMOLED has the pixel in array arrangement, belongs to active display type, and luminous efficacy is high, has excellent performance.
The array substrate circuit of AMOLED is since wiring is complicated, so that the circuit area that each pixel needs is larger, limitation
The promotion of screen pixels density (PPI).For array substrate circuit, the occupied area of storage capacitance is maximum.Storage
Capacitor is usually to be made of for two layers metal gate layers GE1 and GE2, and in order to obtain sufficiently large capacitor, it is necessary to larger area
GE1 and GE2.Therefore, in order to further increase the PPI of array substrate, if reducing screen display area storage capacitance area
The problem of at urgent need to resolve.
Summary of the invention
The present invention provides a kind of array substrate and preparation method thereof, with solve in existing array substrate storage capacitance compared with
Greatly, the problem of causing each pixel circuit area larger, and then screen pixels density can not be promoted.
According to an aspect of the invention, there is provided a kind of array substrate, comprising:
Substrate；
Thin film transistor (TFT) square on the substrate is set；
The first square on the substrate heavily doped region is set；
The first metal layer above first heavily doped region and with first heavily doped region insulation is set；
Second metal layer above the first metal layer and with the first metal layer insulation is set；
Third metal layer above the second metal layer and with second metal layer insulation is set；
Wherein, first heavily doped region, the first metal layer, the second metal layer and the third metal layer are equal
It is ipsilateral outside the thin film transistor (TFT), first heavily doped region, the first metal layer, the second metal layer and institute
At least three stated in third metal layer forms shunt capacitance.
According to one preferred embodiment of the present invention, the thin film transistor (TFT) includes:
Polysilicon layer on the substrate is set, and the polysilicon layer includes the second heavily doped region, third heavily doped region
And the channel region between second heavily doped region and the third heavily doped region is set；
First grid insulating layer on the polysilicon layer is set；
First grid on the first grid insulating layer is set；
Second grid insulating layer on the first grid is set；
Source electrode and drain electrode on the second grid insulating layer is set, and the source electrode passes through the first via hole and described second
Heavily doped region connection, the drain electrode are connect by second via hole with the third heavily doped region；
It is arranged on the second grid insulating layer and covers the interlayer dielectric layer of the source electrode and the drain electrode.
According to one preferred embodiment of the present invention, first heavily doped region and the polysilicon layer same layer are arranged.
According to one preferred embodiment of the present invention, the first metal layer and the first grid same layer are arranged.
According to one preferred embodiment of the present invention, described is provided between the first metal layer and the second metal layer
Two gate insulating layers.
According to one preferred embodiment of the present invention, the third metal layer and the source electrode, the drain electrode same layer are arranged.
According to one preferred embodiment of the present invention, under the conditions of vertical view, first heavily doped region, the first metal layer,
The second metal layer and the third metal layer are oppositely arranged.
According to another aspect of the present invention, a kind of production method of array substrate is additionally provided, comprising the following steps:
Step S10, a substrate is provided；
Step S20, patterned polysilicon layer and the first heavily doped region are formed on the substrate；
Step S30, first grid insulating layer is formed on the polysilicon layer and first heavily doped region, and described
First grid and the first metal layer are formed on first grid insulating layer；
Step S40, second grid insulating layer is formed on the first grid and the first metal layer, and described the
Second metal layer is formed on two gate insulating layers；
Step S50, the third metal layer with second metal layer insulation is formed in the top of the second metal layer；
Wherein, thin film transistor (TFT) includes the polysilicon layer, the first grid, source electrode and drain electrode, and described first is heavily doped
Miscellaneous area, the first metal layer, the second metal layer and the third metal layer are respectively positioned on same outside the thin film transistor (TFT)
Side, at least three in first heavily doped region, the first metal layer, the second metal layer and the third metal layer
Form shunt capacitance.
According to one preferred embodiment of the present invention, the third metal layer and the source electrode, the drain electrode same layer are arranged.
According to one preferred embodiment of the present invention, under the conditions of vertical view, first heavily doped region, the first metal layer,
The second metal layer and the third metal layer are oppositely arranged.
It is an advantage of the invention that provide a kind of array substrate and preparation method thereof, spatially by thin film transistor (TFT) with
Storage capacitance separation, to utilize at least three shape in heavily doped region, the first metal layer, second metal layer and third metal layer
At storage capacitance, to reduce the area of single pixel, and then the pixel density of screen is promoted.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution in the prior art
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only some of invention
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is the structural schematic diagram of array substrate provided in an embodiment of the present invention；
Fig. 2 is the flow diagram of the production method of array substrate provided in an embodiment of the present invention；
Fig. 3 a-3e is the structural schematic diagram of the production method of array substrate provided in an embodiment of the present invention.
Specific embodiment
The explanation of following embodiment is referred to the additional illustration, the particular implementation that can be used to implement to illustrate the present invention
Example.The direction term that the present invention is previously mentioned, such as [on], [under], [preceding], [rear], [left side], [right side], [interior], [outer], [side]
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand the present invention, rather than to
The limitation present invention.The similar unit of structure is with being given the same reference numerals in the figure.
The present invention provides a kind of array substrate and preparation method thereof, storage capacitance is larger in existing array substrate, causes
Each pixel circuit area is larger, and then the problem of can not promote screen pixels density, the present embodiment can improve the defect.
The present invention is described further for connection with figures and specific embodiment below:
As shown in Figure 1, the present invention provides a kind of array substrates and preparation method thereof, comprising:
Substrate 11, including substrate and buffer layer, the making material of the substrate include polyimides, the system of the buffer layer
It include at least one of silica and silicon nitride as material, for preventing array substrate described in external environmental and will play
Buffer the effect of stress.
The thin film transistor (TFT) of 11 top of substrate is set, comprising:
Polysilicon layer on the substrate 11 is set, and the polysilicon layer is heavily doped including the second heavily doped region 122, third
Miscellaneous area 123 and the channel region 124 being arranged between second heavily doped region and the third heavily doped region；
First grid insulating layer 15 on the polysilicon layer, the making material of the first grid insulating layer 15 are set
Including at least one of silica and silicon nitride, for first grid 141 to be kept apart with polysilicon layer；
First grid 141 on the first grid insulating layer 15 is set；
Second grid insulating layer 15 on the first grid 141 is set；
Source electrode 181 on the second grid insulating layer 15 and drain electrode 182 are set, and the source electrode 181 passes through the first mistake
Hole is connect with second heavily doped region 122, and the drain electrode 182 passes through second via hole and the third heavily doped region 123
Connection；
It is arranged on the second grid insulating layer 15 and covers the inter-level dielectric of the source electrode 181 and the drain electrode 182
Layer 17.
First heavily doped region 121 of 11 top of substrate is set.
Preferably, first heavily doped region 121 is located at outside the thin film transistor (TFT), and in the polysilicon layer same layer
Setting, first heavily doped region 121, the second heavily doped region 122, third heavily doped region 123 can be prepared in technique with along with,
And then additional processing procedure is not needed.
First heavily doped region, 121 top and the first metal layer 142 with first heavily doped region insulation are set,
The first metal layer 142 is arranged with 141 same layer of first grid, and it is identical to prepare material, therefore can be in the light shield with along with
It is prepared in technique.
Specifically, it is exhausted to be provided with the first grid between first heavily doped region 121 and the first metal layer 142
Edge layer 13, for playing buffer action, the first metal layer is oppositely arranged with first heavily doped region 142.
142 top of the first metal layer and the second metal layer 16 with the first metal layer 142 insulation are set.
Preferably, the making material of the first metal layer 142 it is identical as the making material of the second metal layer 16 or
Person is different.
16 top of second metal layer and the third metal layer 183 with the second metal layer 16 insulation, institute are set
It states and is provided with layer 15 between second metal layer 16 and the third metal layer 183.
Preferably, the third metal layer 183 is arranged with the source electrode 181,182 same layers of the drain electrode, therefore the third
Metal layer 183 can be prepared in light shield technique with the source electrode 181, the drain electrode 182 with along with, it is only necessary to the third be arranged
It is prepared by the identical material of metal layer 183 and the source electrode 181,182 uses of the drain electrode.
Wherein, first heavily doped region 121, the first metal layer 142, the second metal layer 16 and the third
Metal layer 183 be respectively positioned on it is ipsilateral outside the thin film transistor (TFT), first heavily doped region 121, the first metal layer 142,
At least three in the second metal layer 16 and the third metal layer 183 forms shunt capacitance.
It is understood that first heavily doped region 121, the first metal layer 142, the second metal layer 16 and
The third metal layer 183 is capable of forming storage capacitance, in the case where no supernumerary structure limits, is deposited using the parallel connection that four electrodes form
Storage is held, can be under the premise of holding capacitor total amount is constant relative to storage capacitance in original thin film transistor (TFT), and reduction is deposited
Storage holds occupied area, and then reduces each pixel occupied area, improves the density of screen pixels.
Preferably, in order to reach the optimal design of storage capacitance, under the conditions of vertical view, first heavily doped region 121, institute
State being oppositely arranged for the first metal layer 142, the second metal layer 16 and the third metal layer 183.
As shown in Fig. 2 and 3a-3e, additionally provide a kind of production method of array substrate the following steps are included:
As shown in Figure 3a, step S10, a substrate 11, including substrate and buffer layer, the making material packet of the substrate are provided
Polyimides is included, the making material of the buffer layer includes at least one of silica and silicon nitride, for preventing extraneous ring
It pollutes the array substrate and will play the role of buffering stress in border.；
As shown in Figure 3b, (including the second heavy doping of patterned polysilicon layer step S20, is formed on the substrate 11
Channel region 124 between area 122, third heavily doped region 123 and the second heavily doped region 122, third heavily doped region 123) and the
One heavily doped region 121.
The step S20 is specifically included: forming polycrystalline silicon membrane on the substrate 11, the polycrystalline silicon membrane is carried out
Patterning, and polycrystalline silicon membrane after patterning formulates region implanting ions to form first heavily doped region 121, second
Heavily doped region 122, third heavily doped region 123 and channel region 124.
As shown in Figure 3c, first grid step S30, is formed on the polysilicon layer and first heavily doped region 121
Insulating layer 13, and first grid 141 and the first metal layer 142, first gold medal are formed on the first grid insulating layer 13
Belong to layer to be oppositely arranged with first heavily doped region 142；
Specifically, the first grid 141 is prepared in light shield technique with the first metal layer 142 with along with.
As shown in Figure 3d, second grid step S40, is formed on the first grid 141 and the first metal layer 142
Insulating layer 15, and second metal layer 16 is formed on the second grid insulating layer 15, the second metal layer 16 and described the
One metal layer is oppositely arranged；
As described in Fig. 3 e, step S50, is formed in the top of the second metal layer 16 and insulated with the second metal layer 16
Third metal layer 183；
Specifically, the step 50 includes: to form interlayer dielectric layer 17, and shape in the top of the second metal layer 16
At penetrating through the first grid insulating layer 13, the second grid insulating layer 15, the interlayer dielectric layer 17 respectively with described the
The first via hole and the second via hole of two heavily doped regions 122 and the third heavily doped region 123 contact, form and cover first mistake
The drain electrode 182 of the source electrode 181, covering second via hole in hole and third metal layer 183, the source electrode, the drain electrode 182 and institute
The setting of 183 same layer of third metal layer is stated, and is formed in light shield technique with along with.
Wherein, thin film transistor (TFT) include the polysilicon layer, the first grid 141, source electrode 181 and drain electrode 182, it is described
First heavily doped region 121, the first metal layer 13, the second metal layer 16 and the third metal layer 183 are respectively positioned on institute
State it is ipsilateral outside thin film transistor (TFT), first heavily doped region 121, the first metal layer 13, the second metal layer 16 and
At least three in the third metal layer 183 forms shunt capacitance.
Preferably, the third metal layer 183 is arranged with the source electrode 181,182 same layers of the drain electrode.
Preferably, first heavily doped region 121, the first metal layer 13, second metal under the conditions of vertical view
Layer 16 and the third metal layer 183 are oppositely arranged.
It is an advantage of the invention that provide a kind of array substrate and preparation method thereof, spatially by thin film transistor (TFT) with
Storage capacitance separation, to utilize at least three shape in heavily doped region, the first metal layer, second metal layer and third metal layer
At storage capacitance, to reduce the area of single pixel, and then the pixel density of screen is promoted.
In conclusion although the present invention has been disclosed above in the preferred embodiment, but above preferred embodiment is not to limit
The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention subjects to the scope of the claims.
Claims (10)
1. a kind of array substrate characterized by comprising
Substrate；
Thin film transistor (TFT) square on the substrate is set；
The first square on the substrate heavily doped region is set；
The first metal layer above first heavily doped region and with first heavily doped region insulation is set；
Second metal layer above the first metal layer and with the first metal layer insulation is set；
Third metal layer above the second metal layer and with second metal layer insulation is set；
Wherein, first heavily doped region, the first metal layer, the second metal layer and the third metal layer are respectively positioned on
It is ipsilateral outside the thin film transistor (TFT), first heavily doped region, the first metal layer, the second metal layer and described
At least three in three metal layers forms shunt capacitance.
2. array substrate according to claim 1, which is characterized in that the thin film transistor (TFT) includes:
Polysilicon layer on the substrate is set, the polysilicon layer include the second heavily doped region, third heavily doped region and
Channel region between second heavily doped region and the third heavily doped region is set；
First grid insulating layer on the polysilicon layer is set；
First grid on the first grid insulating layer is set；
Second grid insulating layer on the first grid is set；
Source electrode and drain electrode on the second grid insulating layer is set, and the source electrode is heavily doped by the first via hole and described second
Miscellaneous area's connection, the drain electrode are connect by the second via hole with the third heavily doped region；
It is arranged on the second grid insulating layer and covers the interlayer dielectric layer of the source electrode and the drain electrode.
3. array substrate according to claim 2, which is characterized in that first heavily doped region and the polysilicon layer are same
Layer setting.
4. array substrate according to claim 2, which is characterized in that the first metal layer and the first grid same layer
Setting.
5. array substrate according to claim 2, which is characterized in that the first metal layer and the second metal layer it
Between be provided with the second grid insulating layer.
6. array substrate according to claim 2, which is characterized in that the third metal layer and the source electrode, the leakage
The setting of pole same layer.
7. array substrate according to claim 1, which is characterized in that under the conditions of vertical view, first heavily doped region, institute
State being oppositely arranged for the first metal layer, the second metal layer and the third metal layer.
8. a kind of production method of array substrate, which comprises the following steps:
Step S10, a substrate is provided；
Step S20, patterned polysilicon layer and the first heavily doped region are formed on the substrate；
Step S30, first grid insulating layer is formed on the polysilicon layer and first heavily doped region, and described first
First grid and the first metal layer are formed on gate insulating layer；
Step S40, second grid insulating layer is formed on the first grid and the first metal layer, and in the second gate
Second metal layer is formed on the insulating layer of pole；
Step S50, the third metal layer with second metal layer insulation is formed in the top of the second metal layer；
Wherein, thin film transistor (TFT) includes the polysilicon layer, the first grid, source electrode and drain electrode, first heavily doped region,
The first metal layer, the second metal layer and the third metal layer are respectively positioned on ipsilateral outside the thin film transistor (TFT), institute
State at least three composition in the first heavily doped region, the first metal layer, the second metal layer and the third metal layer
Shunt capacitance.
9. the production method of array substrate according to claim 8, which is characterized in that the third metal layer and the source
Pole, drain electrode same layer setting.
10. the production method of array substrate according to claim 8, which is characterized in that under the conditions of vertical view, described first
Heavily doped region, the first metal layer, the second metal layer and the third metal layer are oppositely arranged.
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| CN201810863399.4A CN109103204A (en) | 2018-08-01 | 2018-08-01 | A kind of array substrate and preparation method thereof |
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| CN201810863399.4A CN109103204A (en) | 2018-08-01 | 2018-08-01 | A kind of array substrate and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113724635A (en) * | 2021-08-18 | 2021-11-30 | 惠科股份有限公司 | Array substrate row driving circuit, array substrate and display panel |
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