CN109102833A - SRAM memory cell - Google Patents
SRAM memory cell Download PDFInfo
- Publication number
- CN109102833A CN109102833A CN201810952092.1A CN201810952092A CN109102833A CN 109102833 A CN109102833 A CN 109102833A CN 201810952092 A CN201810952092 A CN 201810952092A CN 109102833 A CN109102833 A CN 109102833A
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- Prior art keywords
- node
- current potential
- nmos transistor
- bit line
- grid
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Abstract
The invention discloses a kind of SRAM memory cells, are made of two groups of p-type cross-coupled latch structures and two groups of N-type cross-coupled latch structures and four N-type transfer tubes.The present invention had not only been able to achieve soft fault preventing function, but also can work under nearly threshold voltage.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, deposit more particularly to a kind of SRAM (static random access memory)
Storage unit.
Background technique
The reliability for constantly first feeding chip of integrated circuit technique node brings many challenges, and one of challenge is just
It is single-particle inversion caused by single particle effect (SEU) bring soft error.
Soft error may occur in different electronic equipments, such as automotive electronics, Medical Devices etc..
In recent years, since process node is constantly advanced, the distance between device is increasingly closer, and device size is also increasingly
Small, this makes an important sources of the single-particle inversion as soft error.
In addition, low pressure operation is more and more widely used in wearable device, implantable medical device, smart grid, nothing
The SRAM memory cell of line sensing network etc., existing major part soft fault preventing cannot correctly be read and write under low pressure.Traditional 6
Although pipe SRAM memory cell can correct read-write operation under low pressure, do not have the function of soft fault preventing.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of SRAM memory cells, have not only been able to achieve soft fault preventing function, but also
It can work under nearly threshold voltage.
In order to solve the above technical problems, SRAM memory cell of the invention, by two groups of p-type cross-coupled latch structures and
Two groups of N-type cross-coupled latch structures and four N-type transfer tube compositions；
The source electrode of first PMOS transistor and the source electrode of the second PMOS transistor are connected with power voltage terminal VDD, and first
The grid of PMOS transistor is connected with the drain electrode of the second PMOS transistor, and the node of connection is denoted as Q, the second PMOS transistor
Grid be connected with the drain electrode of the first PMOS transistor, the node of connection is denoted as A, forms first group of p-type cross-coupling lock
Storage structure；
The source electrode of third PMOS transistor and the source electrode of the 4th PMOS transistor are connected with power voltage terminal VDD, third
The grid of PMOS transistor is connected with the drain electrode of the 4th PMOS transistor, and the node of connection is denoted as B, the 4th PMOS transistor
Grid be connected with the drain electrode of third PMOS transistor, the node of connection is denoted as QN, forms second group of p-type cross-coupling lock
Storage structure；
The drain electrode of second NMOS transistor and the grid of third NMOS transistor are connected with node Q, the 3rd NMOS crystal
The drain electrode of pipe and the grid of the second NMOS transistor are connected with node QN, and the source electrode of the second NMOS transistor and the 3rd NMOS are brilliant
The source electrode of body pipe is grounded, and forms first group of N-type cross-coupled latch structure；
The drain electrode of first NMOS transistor and the grid of the 4th NMOS transistor are connected with node A, the 4th NMOS crystal
The drain electrode of pipe and the grid of the first NMOS transistor are connected with node B, and the source electrode of the first NMOS transistor and the 4th NMOS are brilliant
The source electrode of body pipe is grounded, and forms second group of N-type cross-coupled latch structure；
The drain electrode of 5th NMOS transistor is connected with bit line BL, and grid is connected with wordline WL, source electrode and node Q
It is connected；The drain electrode of 6th NMOS transistor is connected with bit line BLB, and grid is connected with wordline WL, source electrode and node
QN is connected；The drain electrode of 7th NMOS transistor is connected with bit line BL, and grid is connected with wordline WL, source electrode and node
B is connected, and the drain electrode of the 8th NMOS transistor is connected with bit line BLB, and grid is connected with wordline WL, source electrode and node
A is connected, and the 5th~the 8th NMOS transistor is transfer tube.
Using SRAM memory cell of the invention, 1.2V normal voltage and nearly threshold voltage (nearly threshold voltage refers to:
A voltage range of the supply voltage close to transistor threshold voltage) under can normally complete read-write operation, and when there is soft error
Occur in each node of storage unit, storage unit will not be flipped, and each node still maintains respective normal storage
Value.
This circuit had not only been able to achieve soft fault preventing function, but also can work under nearly threshold voltage, can be applied to highly reliable low
It presses in work system.
The present invention has higher reading static noise margin and lower reading data time, suitable for high speed
In.
Detailed description of the invention
Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:
Fig. 1 is one embodiment schematic diagram of SRAM memory cell；
Fig. 2 is existing 6 pipe SRAM memory cell schematic diagram；
Fig. 3 is existing 10 pipe SRAM memory cell schematic diagram；
Fig. 4 is basic read-write capability waveform diagram；
Fig. 5 is soft fault preventing waveform diagram.
Specific embodiment
As shown in connection with fig. 1, the SRAM memory cell in the following embodiments, by two groups of p-type cross-coupled latch
Structure and two groups of N-type cross-coupled latch structures and four N-type transfer tube compositions, constituting one kind can nearly threshold voltage work
12 pipe soft fault preventing SRAM memory cells, and have the function of fast reading and writing.
The source electrode of PMOS transistor PM1 and the source electrode of PMOS transistor PM2 are connected with power voltage terminal VDD, and PMOS is brilliant
The grid of body pipe PM1 is connected with the drain electrode of PMOS transistor PM2, and the node of connection is denoted as Q, the grid of PMOS transistor PM2
Pole is connected with the drain electrode of PMOS transistor PM1, and the node of connection is denoted as A, forms first group of p-type cross-coupled latch knot
Structure.
The source electrode of PMOS transistor PM3 and the source electrode of PMOS transistor PM4 are connected with power voltage terminal VDD, and PMOS is brilliant
The grid of body pipe PM3 is connected with the drain electrode of PMOS transistor PM4, and the node of connection is denoted as B, the grid of PMOS transistor PM4
Pole is connected with the drain electrode of PMOS transistor PM3, and the node of connection is denoted as QN, forms second group of p-type cross-coupled latch
Structure.
The drain electrode of NMOS transistor NM2 and the grid of NMOS transistor NM3 are connected with node Q, NMOS transistor NM3's
Drain electrode and the grid of NMOS transistor NM2 are connected with node QN, the source electrode of NMOS transistor NM2 and NMOS transistor NM3's
Source electrode ground connection, forms first group of N-type cross-coupled latch structure.
The drain electrode of NMOS transistor NM1 and the grid of NMOS transistor NM4 are connected with node A, NMOS transistor NM4's
The grid of drain electrode and NMOS transistor NM1 are connected with node B, the source electrode of NMOS transistor NM1 and the source of NMOS transistor NM4
Pole ground connection, forms second group of N-type cross-coupled latch structure.
The drain electrode of NMOS transistor NM5 is connected with bit line BL, and grid is connected with wordline WL, source electrode and node Q
It is connected.The drain electrode of NMOS transistor NM6 is connected with bit line BLB, and grid is connected with wordline WL, source electrode and node QN
It is connected.NMOS transistor NM5, NM6 are transfer tube.
The drain electrode of NMOS transistor NM7 is connected with bit line BL, and grid is connected with wordline WL, source electrode and node B
It is connected.The drain electrode of NMOS transistor NM8 is connected with bit line BLB, and grid is connected with wordline WL, source electrode and node A
It is connected.NMOS transistor NM7, NM8 are transfer tube.
Referring to fig. 4, and as shown in connection with fig. 1, the basic read-write capability description of circuit:
1. writing 0: assuming that the current potential of tetra- nodes of original state A, Q, QN, B is respectively as follows: 0,1,0,1.Write 0 process first
Bit line BL is needed to pull down to 0 current potential (low level), bit line BLB is pulled upward to 1 current potential (high level), and then wordline WL is opened, node Q
It is pulled to current potential 0 with the current potential of B, node QN and A are essentially pulled up to the current potential of " supply voltage subtracts a N pipe threshold voltage ", this
It is to have a threshold voltage loss because of the reason of NMOS transistor can only pass weak 1.
Since node Q is 0 current potential, PMOS transistor PM1 is opened, NMOS transistor NM3 shutdown, and node B is that 0 current potential is then led
PMOS transistor PM3 is caused to open, NMOS transistor NM1 shutdown, so, node A and QN have been pulled to 1 current potential.Finally,
A, the current potential of tetra- nodes of Q, QN, B is changed to respectively: 1,0,1,0, logical zero is written into sram cell.
2. writing 1: assuming that the current potential of tetra- nodes of original state A, Q, QN, B is respectively as follows: 1,0,1,0.Write 1 process first
Bit line BL is needed to be pulled upward to 1 current potential, bit line BLB pulls down to 0 current potential, and then wordline WL is opened, and economize on electricity A and QN current potential is pulled to 0
Current potential, node Q and B are essentially pulled up to the current potential of " supply voltage subtracts a N pipe threshold voltage ", this is because NMOS transistor is only
The reason of weak 1 can be passed, has a threshold voltage loss.
Due to node A be 0 current potential, PMOS transistor PM2 open, NMOS transistor NM4 shutdown, node QN be 0 current potential then
PMOS transistor PM4 is caused to open, NMOS transistor NM2 shutdown, so, node Q and B have been pulled to 1 current potential.Most
Eventually, the current potential of tetra- nodes of A, Q, QN, B is changed to respectively: 0,1,0,1, logic 1 is written into sram cell.
3. reading 1: bit line BL and BLB are pulled to 1 current potential in advance, and wordline WL is opened later, since what node Q and B were deposited is
1, so bit line BL current potential is constant, 0 current potential of node A and QN will lead to bit line BLB and is pulled down, when bit line BL and BLB potential difference
When reaching a certain size (for example, 0.1VDD, VDD are supply voltage), it can be read and amplify by sense amplifier, then by data 1
It reads.
4. reading 0: bit line BL and BLB are pulled to 1 current potential in advance, and wordline WL is opened later, since what node QN and A were deposited is
1, so bit line BLB current potential is constant, 0 current potential of node B and Q will lead to bit line BL and is pulled down, when bit line BL and BLB potential difference reaches
When to a certain size (for example, 0.1VDD, VDD are supply voltage), it can be read and amplify by sense amplifier, then read data 0
Out.
In Fig. 4, a, b, c, d, which are respectively represented, to be write 1, reads 1, write 0, read 0 pulse.
It is shown in Figure 5, apply single-particle inversion pulse (SEU) 1, SRAM memory cell respectively in node A, Q, QN and B
It can restore original correct logic state, illustrate the ability that SRAM memory cell of the invention resists soft error.
Fig. 2 is a kind of existing 6 pipe SRAM memory cell circuit, and Fig. 3 is a kind of existing 10 pipe SRAM memory cell electricity
Road compares SRAM memory cell of the invention and both SRAM memory cells, reads static noise margin and reads number
According to comparing result such as the following table 1 of time.
| Read static noise margin | Read data time | |
| SRAM memory cell of the invention | 189.5mV | 210ns |
| The SRAM memory cell of Fig. 2 | 137.9mV | 412.8ns |
| The SRAM memory cell of Fig. 3 | 171.4mV | 411.1ns |
Table 1
The present invention reads the voltage difference required for data between bit line BL and BLB and becomes due to increasing two transfer tubes
It is small, so that SRAM memory cell of the invention reads the time used in data, compares with other two kinds of SRAM memory cells
It is greatly decreased, so that SRAM memory cell speed of the invention greatly improves.
The present invention has maximum reading static noise margin compared with other two kinds of SRAM memory cells, it means that this
Invention is least easy to happen mistake in read procedure, this improves the yield of SRAM.
The present invention and aforementioned two kinds of SRAM memory cells compare, under nearly threshold power voltage, the comparison knot of write error rate
Fruit is as shown in table 2 below.
| 0.6V | 0.55V | 0.5V | 0.45V | |
| SRAM memory cell of the invention | 0 | 0 | 0 | 0 |
| The SRAM memory cell of Fig. 2 | 0 | 0 | 0 | 0 |
| The SRAM memory cell of Fig. 3 | 26.15% | 50.50% | 71.20% | 91.65% |
Table 2
The present invention is under nearly threshold power voltage (0.45V~0.6V) as can be seen from Table 2, and write error rate is 0, the present invention
It can be very good to be applied to nearly threshold power operating at voltages.6 pipe SRAM memory cell circuit shown in Fig. 2 can also be applied to closely
Threshold power operating at voltages, but it is unable to soft fault preventing, the present invention can resist soft error well.It is shown in Fig. 3
SRAM memory cell write error rate is too high, is not suitable for work in nearly threshold voltage.
Above by specific embodiment, invention is explained in detail, but these are not constituted to of the invention
Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these
It should be regarded as protection scope of the present invention.
Claims (5)
1. a kind of SRAM memory cell, it is characterised in that: intersect coupling by two groups of p-type cross-coupled latch structures and two groups of N-types
Close latch structure and four N-type transfer tube compositions；
The source electrode of first PMOS transistor and the source electrode of the second PMOS transistor are connected with power voltage terminal VDD, the first PMOS
The grid of transistor is connected with the drain electrode of the second PMOS transistor, and the node of connection is denoted as Q, the grid of the second PMOS transistor
Pole is connected with the drain electrode of the first PMOS transistor, and the node of connection is denoted as A, forms first group of p-type cross-coupled latch
Structure；
The source electrode of third PMOS transistor and the source electrode of the 4th PMOS transistor are connected with power voltage terminal VDD, the 3rd PMOS
The grid of transistor is connected with the drain electrode of the 4th PMOS transistor, and the node of connection is denoted as B, the grid of the 4th PMOS transistor
Pole is connected with the drain electrode of third PMOS transistor, and the node of connection is denoted as QN, forms second group of p-type cross-coupled latch
Structure；
The drain electrode of second NMOS transistor and the grid of third NMOS transistor are connected with node Q, third NMOS transistor
The grid of drain electrode and the second NMOS transistor is connected with node QN, the source electrode and third NMOS transistor of the second NMOS transistor
Source electrode ground connection, formed first group of N-type cross-coupled latch structure；
The drain electrode of first NMOS transistor and the grid of the 4th NMOS transistor are connected with node A, the 4th NMOS transistor
The grid of drain electrode and the first NMOS transistor is connected with node B, the source electrode of the first NMOS transistor and the 4th NMOS transistor
Source electrode ground connection, formed second group of N-type cross-coupled latch structure；
The drain electrode of 5th NMOS transistor is connected with bit line BL, and grid is connected with wordline WL, and source electrode is connected with node Q
It connects；The drain electrode of 6th NMOS transistor is connected with bit line BLB, and grid is connected with wordline WL, source electrode and node QN phase
Connection；The drain electrode of 7th NMOS transistor is connected with bit line BL, and grid is connected with wordline WL, source electrode and node B phase
Connection, the drain electrode of the 8th NMOS transistor are connected with bit line BLB, and grid is connected with wordline WL, source electrode and node A phase
Connection, the 5th~the 8th NMOS transistor are transfer tube.
2. storage unit as described in claim 1, which is characterized in that write 0 process it is as follows:
If the current potential of tetra- nodes of original state A, Q, QN, B is respectively as follows: 0,1,0,1, bit line BL is pulled down into 0 current potential, bit line
BLB is pulled upward to 1 current potential, opens wordline WL, and the current potential of node Q and B are pulled to 0, and node QN and A are essentially pulled up to that " supply voltage subtracts
Remove a N pipe threshold voltage " current potential；
Due to node Q be 0 current potential, the first PMOS transistor open, third NMOS transistor NM3 shutdown, node B be 0 current potential then
Third PMOS transistor is caused to be opened, the first NMOS transistor NM1 shutdown, then node A and QN has been pulled to high potential 1；Most
Eventually, the current potential of tetra- nodes of A, Q, QN, B is changed to respectively: 1,0,1,0, logical zero is written into sram cell.
3. storage unit as described in claim 1, which is characterized in that write 1 process it is as follows:
If the current potential of tetra- nodes of original state A, Q, QN, B is respectively as follows: 1,0,1,0, bit line BL is pulled upward to 1 current potential, bit line
BLB pulls down to 0 current potential, opens wordline WL, and node A and QN current potential is pulled to 0 current potential, and node Q and B are essentially pulled up to " supply voltage
Subtract a N pipe threshold voltage " current potential；
Since node A is 0 current potential, the second PMOS transistor is opened, the shutdown of the 4th NMOS transistor, and node QN is that 0 current potential is then led
Cause the 4th PMOS transistor open, the second NMOS transistor NM2, then node Q and B has been pulled to 1 current potential, finally, A, Q, QN,
The current potential of tetra- nodes of B is changed to respectively: 0,1,0,1, logic 1 is written into sram cell.
4. storage unit as described in claim 1, which is characterized in that read 1 process it is as follows: bit line BL and BLB all quilts in advance
It draws to 1 current potential, opens wordline WL, what is deposited due to node Q and B is 1, so bit line BL current potential is constant, 0 current potential of node A and QN
It will lead to bit line BLB to be pulled down, when bit line BL and BLB potential difference reaches a certain size, can be read and amplify by sense amplifier,
Then data 1 are read.
5. storage unit as described in claim 1, which is characterized in that read 0 process it is as follows: bit line BL and BLB all quilts in advance
It draws to 1 current potential, opens wordline WL, what is deposited due to node QN and A is 1, so bit line BLB current potential is constant, 0 current potential of node B and Q
It will lead to bit line BL to be pulled down, when bit line BL and BLB potential difference reaches a certain size, can be read and amplify by sense amplifier,
Then data 0 are read.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810952092.1A CN109102833A (en) | 2018-08-21 | 2018-08-21 | SRAM memory cell |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810952092.1A CN109102833A (en) | 2018-08-21 | 2018-08-21 | SRAM memory cell |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112116937A (en) * | 2020-09-25 | 2020-12-22 | 安徽大学 | SRAM circuit structure for realizing multiplication and or logic operation in memory |
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| CN103956184A (en) * | 2014-05-16 | 2014-07-30 | 中国科学院微电子研究所 | Improved SRAM (Static Random Access Memory) memory cell based on DICE (Dual Interlocked Storage Cell) structure |
| CN107240414A (en) * | 2017-06-09 | 2017-10-10 | 中北大学 | Radioresistance memory cell |
| CN107240416A (en) * | 2017-06-13 | 2017-10-10 | 电子科技大学 | A kind of subthreshold value SRAM memory cell circuit |
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2018
- 2018-08-21 CN CN201810952092.1A patent/CN109102833A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103956184A (en) * | 2014-05-16 | 2014-07-30 | 中国科学院微电子研究所 | Improved SRAM (Static Random Access Memory) memory cell based on DICE (Dual Interlocked Storage Cell) structure |
| CN107240414A (en) * | 2017-06-09 | 2017-10-10 | 中北大学 | Radioresistance memory cell |
| CN107240416A (en) * | 2017-06-13 | 2017-10-10 | 电子科技大学 | A kind of subthreshold value SRAM memory cell circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112116937A (en) * | 2020-09-25 | 2020-12-22 | 安徽大学 | SRAM circuit structure for realizing multiplication and or logic operation in memory |
| CN112116937B (en) * | 2020-09-25 | 2023-02-03 | 安徽大学 | SRAM circuit structure for realizing multiplication and/or logic operation in memory |
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Application publication date: 20181228 |