CN109101100B

CN109101100B - Data bit width prediction method and system and applicable electronic equipment

Info

Publication number: CN109101100B
Application number: CN201810884539.6A
Authority: CN
Inventors: 马恺声
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2018-08-06
Filing date: 2018-08-06
Publication date: 2021-10-01
Anticipated expiration: 2038-08-06
Also published as: CN109101100A

Abstract

The application provides a data bit width prediction method, a data bit width prediction system and electronic equipment applicable to the data bit width prediction method, wherein the data bit width prediction method is applied to the electronic equipment with a processor and comprises the following steps: acquiring power supply information of the electronic equipment at least one moment; predicting and calculating the future power-on time and the power-on confidence coefficient of the electronic equipment according to the power supply information; and performing approximate calculation according to the future power-on time, the power-on confidence coefficient and the power storage information of the electronic equipment to obtain a data bit width instruction so as to enable the processor to perform operation according to the data bit width instruction. According to the method and the device, the calculation bit width required by the processor is dynamically predicted by predicting the future energy input of the electronic equipment, and the system power consumption curve is matched with the predicted power curve, so that scientific and reasonable energy management is realized.

Description

Data bit width prediction method and system and applicable electronic equipment

Technical Field

The present application relates to the field of energy management technologies, and in particular, to a data bit width prediction method, a data bit width control system, a nonvolatile processor, a neural network chip, an electronic device, an electronic apparatus, and a computer-readable storage medium.

Background

The rapid development of internet of things devices and wireless communication technologies enables, for example, wearable devices or implantable devices with high performance and small size to be developed rapidly, the demand for high performance means the increase of energy consumption of a system, the development speed of the current battery is far behind the increase of the demand for energy consumption, and the problems of large volume, heavy weight and high maintenance cost still exist in battery power supply. For this reason, the wearable device or the implantable device usually realizes self-powered by collecting external energy, however, self-powered has the defects of limited energy, drastic change and difficult prediction, and therefore, the nodes of the internet of things need to optimize energy utilization efficiency by reasonably storing and utilizing the limited collected energy and reasonably managing energy according to the energy requirements of different loads.

In the nodes of the internet of things, besides signal processing and control operations inside the processor, there are operations of data communication and information interaction between the processor and peripheral devices, such as reading sensor information from a sensor back into the processor, writing and reading data in a memory chip, and transmitting and receiving data through a radio frequency unit. These result in a high demand for power from the processor. In a self-powered system, each atomic operation must be guaranteed to be completed with sufficient energy. Therefore, the energy management devices of the system need to be able to provide such support. Therefore, scientific and reasonable energy management is very important.

Disclosure of Invention

In view of the foregoing disadvantages, the present application provides a data bit width prediction method, a data bit width control system, a non-volatile processor, a neural network chip, an electronic device, an electronic apparatus, and a computer-readable storage medium, so as to achieve scientific and reasonable energy management for the electronic device.

To achieve the above and other related objects, a first aspect of the present application provides a data bit width prediction method applied in an electronic device having a processor, including the steps of: acquiring power supply information of the electronic equipment at least one moment; predicting and calculating the future power-on time and the power-on confidence coefficient of the electronic equipment according to the power supply information; and performing approximate calculation according to the future power-on time, the power-on confidence coefficient and the power storage information of the electronic equipment to obtain a data bit width instruction so as to enable the processor to perform operation according to the data bit width instruction.

A second aspect of the present application provides a data bit width prediction system, which is applied in an electronic device having a processor, and includes a future energy predictor and a bit width predictor; the future energy predictor is used for predicting the future power-on time and the power-on confidence coefficient of the electronic equipment according to the power supply information of the electronic equipment at least one moment; the bit width predictor is used for performing approximate calculation according to the future power-on time, the power-on confidence coefficient and the power storage information of the electronic equipment to obtain a data bit width instruction so as to enable the processor to perform operation according to the data bit width instruction.

A third aspect of the present application provides a non-volatile processor comprising the data bit width prediction system according to the second aspect, an approximate bit width controller, and a start controller. The approximate bit width controller is used for controlling the calculation precision of the processor according to the data bit width instruction when receiving the data bit width instruction output by the data bit width prediction system; and the starting controller is used for starting the processor to work when receiving a starting instruction output by the data bit width prediction system.

A fourth aspect of the present application provides a neural network chip, including the data bit width prediction system according to the second aspect.

A fifth aspect of the present application provides an electronic device, which includes a processor and the data bit width prediction system of the second aspect.

A sixth aspect of the present application provides an electronic device, including the data bit width prediction system according to the second aspect.

A seventh aspect of the present application provides a computer-readable storage medium storing a computer program for energy management, wherein the computer program is configured to implement the data bit width prediction method according to the first aspect when executed.

As described above, the data bit width prediction method, the data bit width control system, the nonvolatile processor, the neural network chip, the electronic device, the electronic apparatus, and the computer-readable storage medium of the present application dynamically predict a calculated bit width required for the processor by predicting a future energy input of the electronic device, and match a system power consumption curve with a predicted power curve, thereby implementing scientific and reasonable energy management.

Drawings

Fig. 1 is a flow chart of a data bit width prediction method according to an embodiment of the present disclosure.

Fig. 2 is a circuit block diagram of a feature extraction module in an embodiment of the present application.

Fig. 3 is a schematic diagram of a neural network according to an embodiment of the present application.

FIG. 4 is a schematic diagram of another embodiment of a neural network.

FIG. 5 is a flow chart of a data bit width prediction method according to another embodiment of the present application.

FIG. 6 is a schematic diagram of an approximate calculation architecture of the data bit width prediction method according to an embodiment of the present application.

FIG. 7 is a flow chart of a data bit width prediction method according to another embodiment of the present application.

FIG. 8 is a schematic diagram of a data bit width prediction system according to an embodiment of the present application.

FIG. 9 is a schematic diagram of the data bit width prediction system of the present application in another embodiment.

FIG. 10 is a schematic diagram of a data bit width prediction system according to still another embodiment of the present application.

FIG. 11 is a diagram illustrating a multiplexing hardware architecture of the data bit width prediction system according to an embodiment of the present invention.

FIG. 12 is a diagram of a multiplexing hardware architecture in another embodiment of the write strategy control system of the present application.

FIG. 13 is a block diagram of a non-volatile processor according to an embodiment of the present application.

Fig. 14 is a schematic diagram of an architecture of a neural network chip according to an embodiment of the present invention.

Fig. 15 is a schematic diagram of an electronic device according to an embodiment of the present application.

Fig. 16 is a schematic diagram of an electronic device according to another embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application is provided for illustrative purposes, and other advantages and capabilities of the present application will become apparent to those skilled in the art from the present disclosure. In the following description, reference is made to the accompanying drawings that describe several embodiments of the application. It is to be understood that other embodiments may be utilized and that compositional and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present application is defined only by the claims of the patent of the present application. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Although the terms first, second, etc. may be used herein to describe various elements in some instances, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first threshold may be referred to as a second threshold, and similarly, a second threshold may be referred to as a first threshold, without departing from the scope of the various described embodiments.

Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. For example, the term "at least one time" in this application includes a time and a plurality of times. As used herein, a phrase referring to "at least one of a list of items refers to any combination of those items, including a single member. By way of example, "at least one of a, b, or c" is intended to encompass: a. b, c, a-b, a-c, b-c and a-b-c.

It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, steps, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, steps, operations, elements, components, species, and/or groups thereof. The terms "or" and/or "as used herein are to be construed as inclusive or meaning any one or any combination. It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It should be understood that the term "instructions" may also be broadly interpreted in this application to mean instructions, data, information, signals, or any combination thereof, and the like. The "Nonvolatile" or "Nonvolatile" are both expressed by the same concept, and the corresponding english language is Nonvolatile.

In internet of things devices such as wearable devices or implantable devices, for example, the cost of replacing batteries, the safety of batteries, the volume of battery compartments, the charging time and the timeliness are all factors to be considered, and many devices desire the volume of batteries in the system to be as small as possible or even no batteries, so self-powered systems including an ambient energy harvesting power supply or a data acquisition device have come to be developed, especially with the development of Nonvolatile Processors (NVPs), so that the ambient energy harvesting power supply is popularized in the use of wearable devices. Non-volatile processors can handle unstable input power by backing up the computational state, and can ensure that systems using these processors are allowed to operate without a battery or super capacitor in a very short time frame as compared to a battery.

Although the non-volatile processor can ensure that the program is continuously executed under the condition of unstable power supply to some extent, when the power supply of the data acquisition device is unstable, the processor in the existing data acquisition device cannot process the latest acquired data, ensure the data accuracy, recover calculation or backup calculation and the like. Of course, the full use of energy may increase the number of backup operations, but also result in more energy being wasted in unnecessary backup and restore operations, and if an energy saving strategy is adopted, this may result in unnecessary leakage of the capacitor, and in addition, the capacitor cannot store newly collected energy even at full charge, and will also delay the service response time. This requires optimization of energy management, such as predicting future energy input to better allocate resources for a subsequent task; predicting a power outage duration to reduce retention time and power for backup operations; or to decide to adopt calculation strategies of different precisions according to predicted energy input, and the like.

The application provides a data bit width prediction method applied to electronic equipment with a processor, which is used for dynamically predicting the calculation bit width required by the processor by predicting the future energy input of the electronic equipment and matching a system power consumption curve with a predicted power curve, thereby realizing scientific and reasonable energy management.

In an embodiment, the processor is, for example, but not limited to, a non-volatile processor (NVP), and in other embodiments, the processor may be a general processor, such as any commercially available processor, controller, microcontroller or state machine without departing from the inventive concepts and concepts disclosed herein. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

In embodiments, the electronic device is an internet of things device, for example a wearable device or an implantable device, such as a wearable electronic device may comprise any type of electronic device that may be worn on a limb of a user. The wearable electronic device may be secured to a human limb such as a wrist, ankle, arm, or leg. Such electronic devices include, but are not limited to, health or fitness assistant devices, digital music players, smart phones, computing devices or display exercise or other activity monitors, time-tellable devices, devices capable of measuring biometric parameters of a wearer or user, and the like. Such as a blood glucose test device or the like.

As one example, the wearable electronic device may be implemented in the form of a wearable health assistant that provides health-related information (real-time or non-real-time) to the user, an authorized third party, and/or an associated monitoring device. The device may be configured to provide health-related information or data, such as, but not limited to, heart rate data, blood pressure data, temperature data, blood oxygen saturation data, diet/nutrition information, medical reminders, health-related reminders or information, or other health-related data. The associated monitoring device may be, for example, a tablet computing device, a telephone, a personal digital assistant, a computer, or the like.

As another example, the electronic device may be configured in the form of a wearable communication device. The wearable communication device may include a processor coupled to or in communication with a memory, one or more communication interfaces, output devices (such as a display and speakers), and one or more input devices. One or more communication interfaces may provide electronic communication between the communication device and any external communication network, device, or platform, such as, but not limited to, a wireless interface, a bluetooth interface, a USB interface, a Wi-Fi interface, a TCP/IP interface, a network communication interface, or any conventional communication interface. In addition to communication, the wearable communication device may provide information, messages, video, operational commands, etc. regarding the time, health, status, or externally connected or communicating devices and/or software running on such devices (and may receive any of the above from an external device).

Referring to fig. 1, a flow chart of an embodiment of a data bit width prediction method according to the present application is shown, as shown in the figure, the data bit width prediction method includes the following steps:

firstly, step S10 is executed to obtain power supply information of the electronic device at least one moment; in an embodiment, the power supply information of the electronic device at least at one moment is acquired when the electronic device is detected to be powered on or in a power-on period.

In the embodiment, the time may be different time periods, and may be divided into a plurality of time levels according to different requirements, such as 10ms, 100ms, 1s, 2s, 3s, 10s, 1 minute, 10 minutes, 1 hour, 1 day, etc., it should be noted that the above time is exemplary, and in different implementation situations, the time is not limited thereto.

In an embodiment, the power supply information is power supply information of the electronic device, the power supply information is generated by a self-powered system of the electronic device, such as an energy harvester, which obtains energy from human body movement, for example, vibration energy from actions or behaviors of walking or limb swinging, jumping, pressing (such as pressure obtained by a small energy harvester implanted in a shoe during running), breathing, and the like, and converts the vibration energy into electric energy, and in other cases, the energy may also come from a natural environment, such as solar energy and the like. The energy harvested by the energy harvester needs to be processed from AC to DC or DC to DC and then the harvested energy is temporarily stored in off-chip or even on-chip capacitors, which are mainly used to support data rather than to store energy.

In an embodiment, the power supply information of the electronic device is obtained by collecting a current value flowing through a detection element or a voltage value at two ends of the detection element at least one moment. Referring to fig. 2, a circuit diagram of a feature extraction module according to an embodiment of the present application is shown, as shown, in this embodiment, the feature extraction module, which is a front-end circuit, includes a power supply, such as a battery or a charger, with one end connected to ground and the other end connected to an Rs resistor, which serves as a detection element, the power supply information provided to the electronic device is acquired by acquiring the value of the current flowing through the sensing element Rs which is a resistor or the value of the voltage across the sensing element Rs to the neural network predictor, the Rs resistor and a 6-bit ADC converter in fig. 2 constitute the detection unit in this embodiment, which is used to detect and acquire the power supply information (Input power sensing), i.e. as indicated by the solid arrow in the illustration of fig. 2, in an embodiment, the power supply information is power-on information of the electronic device, and the power supply information is generated by a self-powered system of the electronic device.

In this embodiment, the energy storage unit is configured to acquire Stored energy information (i.e., the remaining energy of the energy storage element) by acquiring a voltage difference (voltage drop) between two ends of the energy storage element, which is indicated by a dotted arrow in the figure; the energy storage element is a grounding capacitor C1 in FIG. 2. The capacitor C1 and the ADC converter in fig. 2 constitute the detection unit described in this embodiment.

In this embodiment, the received Power-on information (Power Sensing) of the electronic device at one or more time instants is stored in the nonvolatile shift unit. In one example, the last 10 consecutive power-on messages received from the electronic device are used as an example to calculate the power-on time by a counter (not shown), and the counter pushes the last calculated power-on time to the non-volatile shifter to replace the earliest power-on time. In one example, the power supply information of the last 10 historical moments of the electronic device is the last 10 continuous power-on times.

Then, step S11 is executed to predict and calculate the future Power-on Time and the Power-on Confidence (Confidence) of the electronic device according to the Power supply information; in one embodiment, a future power-on time and a power-on confidence of the electronic device are calculated by a neural network according to the power supply information, that is, the future power-on time and the power-on confidence are obtained by performing prediction calculation through the neural network configured as a future energy predictor. In one example, the Neural Network is, for example, a feed forward Neural Network (feed forward Neural Network) that is trained offline or online back propagation. In this embodiment, a feed-forward neural network is used to predict and calculate the future power-on time and the power-on confidence of the electronic device according to the power supply information of the electronic device at the latest 10 historical times.

Referring to a neural network shown in fig. 3, fig. 3 is a schematic diagram of a neural network in an embodiment of the present application, as shown in the drawing, in this embodiment, the neural network is a feed-forward neural network, for example, the feed-forward neural network includes 1 Input Layer (Input Layer), 2 Hidden layers (high Layer 1,2), and 1 Output Layer (Output Layer), each Layer has 10 neurons, each neuron has 10 outputs, and the power supply information received from a non-volatile Shifter (NV Shifter) at 10 time instants (from On time _1 to On time _10) is used to predict the future generated power. But not limited thereto, in other possible embodiments, it is in another neural network structure as shown in fig. 4, fig. 4 shows another neural network schematic diagram in one embodiment of the present application, and as shown in the figure, the feedforward neural network may include more Hidden layers (Hidden layers 1,2 … … N), and each Layer may also include more or less neurons (N). The neural network shown in fig. 3 or fig. 4 is a neural network trained offline or a neural network trained online in reverse propagation.

In the present embodiment, the feedforward neural network configured as the future energy predictor is used to calculate the power-on time for the received last 10 consecutive power-on times of the electronic device, for example, by a counter (not shown) that pushes the last calculated power-on time to the non-volatile shifter instead of the earliest power-on time. Specifically, by configuring a fully connected feed-forward neural network with 2 hidden layers, setting 10 neurons per layer, outputting 10 potential energy levels (energy levels) for the 10 neurons of the layer, translating each energy level for a power-on time, each output indicating a power-on confidence, where the highest value is output as the predicted energy level and its confidence when the power-on confidence is very different from the other confidences. In one case, if the first few predicted energization confidences are within the 10% interval, the energy levels for the predicted future energization times are weighted averaged, and the corresponding energization confidences are also averaged.

Then, step S12 is executed, and approximate calculation is performed according to the future power-on time, the power-on confidence and the power storage information of the electronic device to obtain a data bit width instruction (Bitwidth), so that the processor performs operation according to the data bit width instruction, and further the electronic device can dynamically adjust the calculation precision of the processor according to the expected energy to realize scientific energy management.

In an embodiment, the power storage information (Stored power sensing) of the electronic device is obtained by the detection unit shown in fig. 2 by collecting a voltage drop of an energy storage element. In this embodiment, the energy storage unit is configured to acquire the electricity storage information by collecting a voltage difference (voltage drop) between two ends of an energy storage element, which is indicated by a dotted arrow in the figure, that is, the remaining capacity of the energy storage element, where the energy storage element is a ground capacitor C1 in fig. 2.

In the embodiment, a neural network is used for performing approximate calculation according to the future power-on time, the power-on confidence and the power storage information of the electronic equipment to obtain the data bit width instruction. In one example, the data bit width instruction is calculated by prediction of 2 hidden layers upon receiving 10 potential energy levels (energy levels) and a power-on confidence for each energy level via a neural network configured as a bit width predictor. Specifically, the input layer of the feedforward neural network according to the bit width predictor receives 10 potential energy levels (energy levels) output by the future energy predictor and performs approximate calculation corresponding to the power-on confidence of each energy level to predict and determine the appropriate output data bit width to determine the precision of the processor at which energy level to perform operation. The Neural Network is, for example, a feed-forward Neural Network (feed-forward Neural Network), which is a Neural Network trained offline or a Neural Network trained online in a back propagation manner.

Referring to fig. 5, a flowchart of a data bit width prediction method according to another embodiment of the present application is shown, where in the present embodiment, the step S12 of performing an approximate calculation according to the future power-on time, the power-on confidence and the power storage information of the electronic device to obtain the data bit width instruction further includes:

in step S120, performing a prediction calculation according to the future power-on time, the power-on confidence and the power storage information of the electronic device to obtain approximate configuration data (approximate Config); in this embodiment, when 10 potential energy levels (energy levels) and the power-on confidence corresponding to each energy level are received through the neural network configured as the bit width predictor, the approximate configuration data is calculated by prediction of 2 hidden layers, and the approximate configuration data includes bit width information obtained by the bit width predictor through the neural network according to future power-on time, power-on confidence and power storage information prediction calculation, such as how many bits of bit width the processor needs to calculate, so as to determine the correct or proper bit width configuration.

In step S121, the approximate configuration data (approximate Config) is identified according to the preset approximate indicating data (ACEN), and when it is determined that the approximate configuration data can be approximately calculated, the approximate calculation is performed to generate a data bit width instruction (Bitwidth). In the present embodiment, the approximation indicating data (ACEN) is preset, specifically, data that can be approximated through programmer identification setting, and the data includes a data buffer (data buffer) or an image (image), but does not include a basic variable, such as an index in a "for" loop.

Referring to fig. 6, a schematic diagram of an approximate computing architecture of an embodiment of the data bit width prediction method of the present application is shown, where the approximate computing architecture includes a 5-stage pipeline processor architecture, and a dynamic architecture approximation control unit controls the approximate computing of the pipeline processor architecture. As shown in the figure, a neural network configured as a future Energy predictor is used for predicting and calculating the future Power-on time and the Power-on confidence coefficient of the electronic equipment according to the Power supply information (Input Power), then a neural network configured as a bit width predictor is used for predicting and calculating according to the future Power-on time, the Power-on confidence coefficient and the Power storage information (Stored Energy) of the electronic equipment to obtain approximate configuration data (approximate configuration), then a bit called ACEN is added to each approximate configuration data through an approximate control unit preset with an approximate designation data (ACEN) interface to identify whether the approximate configuration data can be approximated during operation, the dynamic architecture approximation control unit reads the approximate designation data (ACEN) and the obtained approximate configuration data (approximate configuration) from two operators in an instruction, if an operator is determined to be approximated, but the other operator can not be approximated, the instruction can not be approximated, if both operators can be approximated, the data bit width instruction (Bitwidth) is generated to enable the processor to utilize the processor architecture of the 5-stage pipeline to carry out approximation calculation, and further, the calculation (operation) precision of the processor is controlled. As can be seen from the above, a bit width predictor is configured to be activated at the beginning of a programmer-predefined loop in the main program, which is typically a loop for a new frame to be processed. The configured bit width predictor is used to determine the appropriate bit width to complete the loop operation of the entire program during this power-up cycle.

In an embodiment, the dynamic architecture approximation control unit is, for example, an approximation bit width controller disposed in a processor or an execution module, and the approximation bit width controller is configured to control the precision of an operation according to a data bit width instruction (Bitwidth) configured as a neural network output of a bit width predictor when the data bit width instruction is received; in this embodiment, the approximate bit width controller has one or more nonvolatile shift units, such as a nonvolatile Shifter (NV Shifter), into which the approximate bit width controller stores the received data bit width instruction.

The processor is used for calculating and processing the sensing data or the interaction data acquired by the electronic equipment. In some examples, the processing of the sensed data, such as the wearable device, generates user data that may be transmitted by the wireless module or displayed by the display device by processing the collected heart rate data, blood pressure data, temperature data, blood oxygen saturation data, diet/nutrition information, medical reminders, health-related reminders or information, or other health-related data.

In some examples, the processing of the interaction data may be such as by a user operating a wearable device to respond to an event notification generated by a host device. The wearable device can receive notifications of events from the host device and present reminders and prompts for responses to the user. If the user responds to the prompt, the wearable device may transmit the response to the host device. For example, a user may respond to a phone call, text message, or other communication received at a host device.

Referring to fig. 7, a flowchart of a data bit width prediction method according to another embodiment of the present application is shown, as shown in the drawing, in this embodiment, step S10' is first executed to obtain power supply information of the electronic device at least at one time; in an embodiment, the power supply information of the electronic device at least at one moment is acquired when the electronic device is detected to be powered on or in a power-on period. The description of the step S10' refers to the description of the step S10 given above in reference to fig. 1, and is not repeated herein.

Then, step S11' is executed to predict and calculate the future Power-on Time and the Power-on Confidence (Confidence) of the electronic device according to the Power supply information; in an embodiment, a neural network is used to predict and calculate the future power-on time and the power-on confidence of the electronic device according to the power supply information, and the description of the step S11' refers to the description of the step S11 given above, which is not repeated herein.

Then, step S12' is executed to perform approximate calculation according to the future power-on time, the power-on confidence level, and the power storage information of the electronic device to obtain a data bit width instruction (Bitwidth), and perform approximate calculation according to the future power-on time, the power-on confidence level, and the power storage information of the electronic device to predict an output Start Threshold (System Start Stored Energy Threshold).

In this embodiment, a feed-forward neural network configured as a bit width predictor predicts to output a data bit width instruction and a Start Threshold, the feed-forward neural network of the bit width predictor receives, as inputs, an Energy level of a future power-on time, a power-on confidence, and a Stored Energy level included in power storage information, and includes 1 input layer, 2 hidden layers, and 1 output layer, each layer has 10 neurons, each neuron has 10 outputs, and the output layer outputs 2 kinds of information, that is, an output data bit width instruction (Bitwidth) and a Start Threshold (System Start Stored Energy Threshold), wherein 8 outputs of the output layer are used as outputs of the data bit width instruction, and 1 output of the output layer is used as an output of the Start Threshold. In an example, an input layer of a feed-forward neural network configured as a bit width predictor receives 10 potential energy levels (energy levels) output by the future energy predictor and a power-on confidence corresponding to each energy level, and calculates an output start threshold by prediction of 2 hidden layers to give an indication of whether the processor is started or not.

Then, step S13' is executed to perform a prediction calculation according to the data bit width instruction (Bitwidth) and the Power failure information (Power output Sensing) to obtain Quality of Service prediction information (Quality of Service, QoS), where the Power failure information includes a Power failure confidence level; in one embodiment, to avoid the electronic device producing a low quality data output, such as data below 20dB, the corresponding data of 20dB and above is generally considered to be a reasonable quality data. The method of the present application also predicts a potential output quality of a program of the electronic device.

In an embodiment, the power outage information may be collected by a power outage sensing unit of the feature extraction module, for example, the DC-DC converter, the LDO device, the Charge Breaker (Charge Breaker), the leakage capacitor C2 and the ADC converter in fig. 2 constitute a power outage sensing unit, and the system power outage time may be calculated by a voltage drop detected by the ADC by charging the leakage capacitor each time during a recovery operation controlled by the Charge Breaker (Charge Breaker) as shown in fig. 2 and checking the voltage of the capacitor when the electronic device recovers from a power outage. In particular, as shown in the power-off sensing unit portion of fig. 2. Each time the system is powered up (before resuming operation), the leakage capacitor charges at a fully stable voltage. When a power failure occurs, the voltage on the leakage capacitor drops with the passage of time, and the detected power-off time can be obtained by measuring the remaining voltage in the leakage capacitor after the next power-on. The outage information includes an outage Confidence (Confidence) that may be generated by predictive calculations via a feed-forward neural network configured as an outage predictor.

In this embodiment, the qos prediction information is obtained by performing prediction calculation by a neural network according to the data bit width instruction and the power-off information, that is, by configuring the neural network as a qos predictor, the qos predictor obtains an approximate bit width and an average power interrupt prediction confidence during the frame data as input processing.

Finally, executing step S14', when the qos prediction information satisfies a preset condition, outputting the qos prediction information to the processor; and outputting a starting instruction to the processor when the starting threshold meets the preset condition. In this embodiment, the QoS predictor performs prediction calculation according to the data bit width instruction (Bitwidth) and the Power failure information (Power output Sensing) to obtain Predicted QoS; and outputs to the processor when the quality of service prediction information (Predicted QoS) satisfies a Threshold Y, and outputs to the processor a Start instruction (System Start) when the Start Threshold (System Start Stored Energy Threshold) satisfies the Threshold Y. In this embodiment, the threshold Y is, for example, 20dB, but is not limited thereto, and different thresholds Y may be set in different implementation states, for example, for different types of electronic devices. In one embodiment, the QoS predictor implements QoS prediction by a feedforward neural network including 2 hidden layers.

Outputting a start instruction to the processor when the start threshold satisfies the preset condition, for example, if the predicted potential input energy level is low and there is not enough stored energy in the buffer capacitor, the processor is not started; if the predicted potential input energy is high, but the received power-on confidence is low, then the processor is instructed to boot only if the stored energy level is high enough to reach the prediction threshold; if the predicted potential input energy is high and the power-on confidence is high, the processor is instructed to boot up (the predictor outputs a very low threshold) to get better forward progress and QoS satisfaction even though the stored energy is low. In one example, the energization confidence ratio is relatively low, e.g., less than 30%, and the energization confidence ratio is relatively high, e.g., greater than 70%. But not limited thereto, the threshold of the power-on confidence can be dynamically adjusted according to actual situations under the circumstance of knowing the innovative idea of the present application.

Because more electric energy is dissipated in high bit width operation (high calculation precision of a processor) than in low bit width (low calculation precision of the processor), the starting time of the processor is controlled through controlling the processor to start and store an energy threshold value in the application, and the purpose of relieving the low-quality output problem is achieved under the condition that energy management is reasonable, the starting time of the processor is delayed through controlling the parameter of the threshold value Y until enough energy exists in an energy storage capacitor to restart the processor, and high-quality data operation or output is ensured under the reasonable energy management mechanism.

In an embodiment, the control of the processor Start may be implemented by a Start controller, the Start controller is configured to Start the processor when receiving a Start instruction (System Start); in one embodiment, the start-up controller has one or more non-volatile shift cells, such as a non-volatile Shifter (NV Shifter), into which the start-up controller stores received start-up instructions. In this embodiment, the Start Controller is, for example, an NVP Start Trigger (NVP Start Trigger Controller).

The application also provides a data bit width prediction system applied to the electronic equipment with the processor, which is used for dynamically predicting the calculation bit width required by the processor by predicting the future energy input of the electronic equipment and matching the system power consumption curve with the predicted power curve, thereby realizing scientific and reasonable energy management. In an embodiment, the processor is, for example, but not limited to, a non-volatile processor (NVP), and in other embodiments, the processor may be a general processor, such as any commercially available processor, controller, microcontroller or state machine without departing from the inventive concepts and concepts disclosed herein. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

Referring to fig. 8, which is a schematic diagram of the data bit width prediction system 1 according to an embodiment of the present application, the data bit width prediction system includes a future energy predictor 11 and a bit width predictor 12.

The future energy predictor 11 is used for predicting the future power-on time and the power-on confidence coefficient of the electronic equipment according to the power supply information of the electronic equipment at least one moment; in the embodiment, the future energy predictor 11 detects the power supply information of the electronic device at least one moment when the electronic device is powered on or in a power-on period by a feature extraction module 2.

In this embodiment, the received Power-on information (Power Sensing) of the electronic device at one or more time instants is stored in the nonvolatile shift unit. In one example, the last 10 consecutive power-up messages received from the electronic device are used as an example to calculate the power-up time by a counter (not shown), and the counter pushes the last calculated power-up time to the non-volatile shifter to replace the earliest power-down time. In one example, the power supply information of the last 10 historical moments of the electronic device is the last 10 continuous power-on times.

In one embodiment, the future energy predictor 11 performs a prediction calculation on the future power-on time and the power-on confidence of the electronic device by a neural network according to the power supply information, that is, performs a prediction calculation on the neural network configured as the future energy predictor to obtain the future power-on time and the power-on confidence. In one example, the Neural Network is, for example, a feed forward Neural Network (feed forward Neural Network) that is trained offline or online back propagation. In this embodiment, a feed-forward neural network is used to predict and calculate the future power-on time and the power-on confidence of the electronic device according to the power supply information of the electronic device at the latest 10 historical times.

Referring to fig. 3, fig. 3 is a schematic diagram of a neural network according to an embodiment of the present invention, as shown in the drawing, in this embodiment, the neural network is, for example, a feedforward neural network, the feedforward neural network includes 1 Input Layer (Input Layer), 2 Hidden layers (high Layer 1,2), and 1 Output Layer (Output Layer), each Layer has 10 neurons, each neuron has 10 outputs, the future energy predictor includes one or more Nonvolatile shift units for storing the power supply information, and the future energy predictor is used for predicting the future generated power based On the received power supply information at 10 time points (from On time _1 to On time _10) from a Nonvolatile shift (NV shift). But not limited thereto, in other possible embodiments, it is in another neural network structure as shown in fig. 4, fig. 4 shows another neural network schematic diagram in one embodiment of the present application, and as shown in the figure, the feedforward neural network may include more Hidden layers (Hidden layers 1,2 … … N), and each Layer may also include more or less neurons (N). The neural network shown in fig. 3 or fig. 4 is a neural network trained offline or a neural network trained online in reverse propagation.

In the present embodiment, the feedforward neural network configured as the future energy predictor 11 calculates the power-on time for the received last 10 consecutive power-on times of the electronic device by using a counter (not shown) to push the last calculated power-on time to the nonvolatile shifter instead of the earliest power-on time. Specifically, by configuring a fully connected feed-forward neural network with 2 hidden layers, setting 10 neurons per layer, outputting 10 potential energy levels (energy levels) for the 10 neurons of the layer, translating each energy level for a power-on time, each output indicating a power-on confidence, where the highest value is output as the predicted energy level and its confidence when the power-on confidence is very different from the other confidences. In one case, if the first few predicted energization confidences are within the 10% interval, the energy levels for the predicted future energization times are weighted averaged, and the corresponding energization confidences are also averaged.

The bit width predictor 12 is configured to perform approximate calculation according to the future power-on time, the power-on confidence and the power storage information of the electronic device to obtain a data bit width instruction, so that the processor 3 performs operation according to the data bit width instruction, and further, the electronic device can dynamically adjust the calculation precision of the processor according to expected energy to realize scientific energy management.

In the embodiment, the bit width predictor 12 performs approximate calculation by a neural network according to the future power-on time, the power-on confidence and the power storage information of the electronic device to obtain the data bit width instruction. In one example, the data bit width instruction is calculated by prediction of 2 hidden layers upon receiving 10 potential energy levels (energy levels) and a power-on confidence for each energy level via a neural network configured as a bit width predictor 12. Specifically, the input layer of the feedforward neural network according to the bit width predictor receives 10 potential energy levels (energy levels) output by the future energy predictor and performs approximate calculation corresponding to the power-on confidence of each energy level to predict and determine the appropriate output data bit width so as to determine the precision of the operation of the processor at which energy level. The Neural Network is, for example, a feed-forward Neural Network (feed-forward Neural Network), which is a Neural Network trained offline or a Neural Network trained online in a back propagation manner.

In one embodiment, the bit width predictor 12 includes an approximate calculation unit (not shown) for performing a prediction calculation according to the future power-on time, the power-on confidence level, and the power storage information of the electronic device to obtain approximate configuration data; and identifying the approximate configuration data (approximate Config) according to preset approximate indicating data (ACEN), and carrying out approximate calculation to generate a data bit width instruction (BitWidth) when the approximate configuration data is judged to be approximately calculated.

In this embodiment, when 10 potential energy levels (energy levels) and the power-on confidence corresponding to each energy level are received through the neural network configured as the bit width predictor, the approximate configuration data is calculated by prediction of 2 hidden layers, and the approximate configuration data includes bit width information obtained by the bit width predictor through the neural network prediction calculation, such as how many bits the processor needs to calculate to determine a correct or proper bit width configuration.

Referring to fig. 6, in the present embodiment, the approximation indicating data (ACEN) is preset, specifically, data that can be approximated by programmer identification is set, and the data includes data buffer (data buffer) or image (image) but does not include basic variables, such as index in the "for" loop.

As shown in FIG. 6, the approximation calculation architecture includes a 5-stage pipeline processor architecture, and a dynamic architecture approximation control unit controls the approximation calculation of the pipeline processor architecture. As shown in the figure, a neural network configured as a future Energy predictor is used for predicting and calculating the future Power-on time and the Power-on confidence coefficient of the electronic equipment according to the Power supply information (Input Power), then a neural network configured as a bit width predictor is used for predicting and calculating according to the future Power-on time, the Power-on confidence coefficient and the Power storage information (Stored Energy) of the electronic equipment to obtain approximate configuration data (approximate configuration), then a bit called ACEN is added to each approximate configuration data through an approximate control unit preset with an approximate designation data (ACEN) interface to identify whether the approximate configuration data can be approximated during operation, the dynamic architecture approximation control unit reads the approximate designation data (ACEN) and the obtained approximate configuration data (approximate configuration) from two operators in an instruction, if an operator is determined to be approximated, but if the other operator is not close, the instruction is not approximate, and if both operators are approximate, a data bit width instruction (Bitwidth) is generated to enable the processor to perform approximate calculation by using the processor architecture of the 5-stage pipeline, so that the calculation (operation) precision of the processor is controlled. As can be seen from the above, a bit width predictor is configured to be activated at the beginning of a programmer-predefined loop in the main program, which is typically a loop for a new frame to be processed. The configured bit width predictor is used to determine the appropriate bit width to complete the loop operation of the entire program during this power-up cycle.

In the embodiment, the processor 3 performs the operation of controlling the operation by an approximate bit width controller when receiving the data bit width instruction (Bitwidth), the approximate bit width controller is configured to control the accuracy of the operation according to the data bit width instruction when receiving the data bit width instruction (Bitwidth) configured as the neural network output of the bit width predictor; in this embodiment, the approximate bit width controller has one or more nonvolatile shift units, such as a nonvolatile Shifter (NV Shifter), into which the approximate bit width controller stores the received data bit width instruction. The processor is used for calculating and processing the sensing data or the interaction data acquired by the electronic equipment. In some examples, the processing of the sensed data, such as the wearable device, generates user data that may be transmitted by the wireless module or displayed by the display device by processing the collected heart rate data, blood pressure data, temperature data, blood oxygen saturation data, diet/nutrition information, medical reminders, health-related reminders or information, or other health-related data.

In one embodiment, the bit width predictor 12 is further configured to perform an approximate calculation to predict an output start-up threshold according to the future power-on time, the power-on confidence level, and the power storage information of the electronic device. In this embodiment, a feed-forward neural network configured as a bit width predictor 12 performs prediction to output a data bit width instruction and a Start Threshold, the feed-forward neural network of the bit width predictor 12 receives as inputs an Energy level of a future power-on time, a power-on confidence and a Stored Energy level included in power storage information, the feed-forward neural network includes 1 input layer, 2 hidden layers and 1 output layer, each layer has 10 neurons and each neuron has 10 outputs, and the output layer outputs 2 kinds of information, that is, an output data bit width instruction (Bitwidth) and a Start Threshold (System Start Stored Energy Threshold), wherein 8 outputs of the output layer are used as outputs of the data bit width instruction, and 1 output of the output layer is used as an output of the Start Threshold. In an example, an input layer of a feed-forward neural network configured as a bit width predictor receives 10 potential energy levels (energy levels) output by the future energy predictor and a power-on confidence corresponding to each energy level, and calculates an output start threshold by prediction of 2 hidden layers to give an indication of whether the processor is started or not.

In one embodiment, to avoid the electronic device producing a low quality data output, such as data below 20dB, the corresponding data of 20dB and above is generally considered to be a reasonable quality data. The data bit width prediction system of the present application also predicts potential output quality of a program of an electronic device. Referring to fig. 9, which is a schematic diagram of the data bit width prediction system 1 according to another embodiment of the present application, as shown, the data bit width prediction system 1 further includes a quality of service predictor 13. In this embodiment, the processor 3 includes a start controller 30 and an approximate bit width controller 31.

The service quality predictor 13 is configured to perform prediction calculation according to the data bit width instruction and the power failure information to obtain service quality prediction information, and output the service quality prediction information to the processor 3 when the service quality prediction information satisfies a preset condition; and outputting a start instruction to the processor 3 when the start threshold satisfies the preset condition; the power outage information includes a power outage confidence.

In this embodiment, the qos prediction information is obtained by performing prediction calculation by a neural network according to the data bit width instruction and the power-off information, that is, by configuring the neural network as the qos predictor 13, the qos predictor 13 obtains the approximate bit width and the average power interruption prediction confidence during the frame data as input processing. In one embodiment, the neural network is, for example, a feedforward neural network including 2 hidden layers.

In this embodiment, the QoS predictor 13 performs prediction calculation according to the data bit width instruction (Bitwidth) and the Power failure information (Power output Sensing) to obtain Predicted QoS; and outputting a Start instruction (System Start) to the Start controller when the quality of service prediction information (Predicted QoS) satisfies a Threshold Y, and outputting a Start instruction (System Start) to the Start controller when the Start Threshold (System Start Stored Energy Threshold) satisfies the Threshold Y. In this embodiment, the threshold Y is, for example, 20dB, but is not limited thereto, and different thresholds Y may be set in different implementation states, for example, for different types of electronic devices.

For example, if the predicted potential input energy level is relatively low and there is insufficient stored energy in the buffer capacitor, the start controller 10 is caused to control the processor not to start; if the predicted potential input energy is high, but the received energization confidence is low, then the start controller 10 is instructed to control processor start only if the stored energy level is high enough to reach the prediction threshold; if the predicted potential input energy is high and the confidence in power-on is high, even if the stored energy is low, the boot controller 10 is instructed to control processor boot (the predictor output is a very low threshold) for better forward progress and QoS satisfaction. In one example, the energization confidence ratio is relatively low, e.g., less than 30%, and the energization confidence ratio is relatively high, e.g., greater than 70%. But not limited thereto, the threshold of the power-on confidence can be dynamically adjusted according to actual situations under the circumstance of knowing the innovative idea of the present application.

In one example, the control of the processor Start may be implemented by a Start controller 30, the Start controller 30 being configured to Start the operation of the processor 3 when receiving a Start command (System Start); in one embodiment, the start-up controller 30 has one or more non-volatile shift cells, such as a non-volatile Shifter (NV Shifter), into which the start-up controller 30 stores received start-up instructions. In this embodiment, the Start Controller 30 is, for example, an NVP Start Trigger (NVP Start Trigger Controller).

In an example, when the processor 3 receives the data bit width instruction (Bitwidth), the operation of the control operation is performed by the approximate bit width controller, the approximate bit width controller 31 is configured to control the precision of the operation according to the data bit width instruction when receiving the data bit width instruction (Bitwidth) configured as the neural network output of the bit width predictor 12, in this embodiment, the approximate bit width controller 31 has one or more nonvolatile bit width shifting units, such as a nonvolatile Shifter (NV Shifter), and the approximate bit width controller 31 stores the received data bit width instruction into the nonvolatile shifting units. The processor 3 is used for calculating and processing the sensing data or the interaction data acquired by the electronic equipment.

In some examples, the processing of the sensed data, such as the wearable device, generates user data that may be transmitted by the wireless module or displayed by the display device by processing the collected heart rate data, blood pressure data, temperature data, blood oxygen saturation data, diet/nutrition information, medical reminders, health-related reminders or information, or other health-related data.

Referring to fig. 10, a schematic diagram of a data bit width prediction system according to another embodiment of the present invention is shown, wherein the data bit width prediction system includes the future energy predictor 11, the bit width predictor 12, the quality of service predictor 13, the power-down predictor 14, and the backup time predictor 15. In this embodiment, the processor 3 includes a start controller 30, an approximate bit width controller 31, and a retention time controller 32.

In this embodiment, the future energy predictor 11 is configured to predict a future power-on time and a power-on confidence of the electronic device according to power supply information of the electronic device at least one time; please refer to the description of the embodiments related to fig. 8 to fig. 9, which is not repeated herein.

The bit width predictor 12 is configured to perform approximate calculation according to the future power-on time, the power-on confidence and the power storage information of the electronic device to obtain a data bit width instruction, so that the approximate bit width controller of the processor 3 performs operation according to the data bit width instruction, and further, the electronic device can dynamically adjust the calculation precision of the processor according to expected energy to realize scientific energy management. Please refer to the description of the embodiments related to fig. 8 to fig. 9, which is not repeated herein.

The service quality predictor 13 is used for performing prediction calculation according to the data bit width instruction and the power failure information to obtain service quality prediction information, and outputting the service quality prediction information to the processor when the service quality prediction information meets a preset condition; and outputting a start instruction to the processor 3 when the start threshold satisfies the preset condition; the power outage information includes a power outage confidence. Please refer to the description of the embodiments related to fig. 8 to fig. 9, which is not repeated herein.

The power-off predictor 14 is used for predicting and calculating the future power-off time and the power-off confidence of the electronic equipment according to the power-off information of the electronic equipment at least at one moment. In an embodiment, the power-off information of the electronic device at least one moment is acquired when the power-off of the electronic device is detected or during a power-off period.

In an embodiment, the power failure information is information of interruption of power input in the electronic device due to insufficient power supply, energy exhaustion, human factors (such as human setting or human damage) or unforeseen accidents, and the like, such as information of time of power failure and duration of power failure. In one embodiment, 10 levels of power down time may be set, for example, 10ms, 100ms, 1s, 2s, 3s, 10s, 1 minute, 10 minutes, 1 hour, 1 day, etc. for different periods of time.

In an embodiment, the power-off information is obtained by collecting a voltage drop across a power-off element at the time, and referring to fig. 2, which is a circuit block diagram of a feature extraction module in an embodiment of the present application, as shown in the figure, in one example, the power-off information can be collected by a power-off induction unit of the feature extraction module shown in fig. 2, such as the DC-DC converter, the LDO device, the Charge Breaker (Charge Breaker), the leakage capacitor C2 and the ADC converter in fig. 2, and the system power-off time can be calculated by detecting the voltage drop through the ADC by charging the leakage capacitor each time during a recovery operation controlled by the Charge Breaker (Charge Breaker) as shown in fig. 2 and checking the voltage of the capacitor when the electronic device recovers from the power-off. In particular, as shown in the power-off sensing unit portion of fig. 2. Each time the system is powered up (before resuming operation), the leakage capacitor charges at a fully stable voltage. When a power failure occurs, the voltage on the leakage capacitor drops with the passage of time, and the detected power-off time can be obtained by measuring the remaining voltage in the leakage capacitor after the next power-on. In this embodiment, the received Power-off information (Power output Sensing) of the electronic device at one or more time points is stored in the nonvolatile shift unit. In one example, the last 10 consecutive power-off messages received from the electronic device are used to calculate the power-off time by a counter (not shown), which pushes the last calculated power-off time to the non-volatile shifter to replace the earliest power-off time.

In one embodiment, the outage predictor 14 performs a prediction calculation by a neural network to obtain a future outage Time and an outage Confidence of the electronic device, for example, the neural network is configured to perform the prediction calculation by the outage predictor 14 to obtain the future outage Time (Power-off Time) and the outage Confidence (Confidence) of the electronic device. In an embodiment, the outage predictor 14 includes one or more non-volatile shift units, which are non-volatile shifters, for storing the outage information. The input layer of the neural network is used for receiving Power-off information such as 10 historical Power-off times from the nonvolatile shifting unit, and after 2 hidden layers of the feedforward neural network are calculated, future Power-off times (Power-off times) of 10 Power-off Time levels and Power-off Confidence degrees (Confidence) corresponding to each future Power-off Time are predicted by the output layer, so that the prediction of possible future Power supply break or Power supply break Time which occurs already is realized.

The backup time predictor 15 is configured to perform prediction calculation according to the future power failure time and the power failure confidence coefficient to obtain a write strategy instruction and a write strategy confidence coefficient, so that the processor 3 executes write operation according to the write strategy instruction; the write strategy command includes at least one of write current and write time information for performing a write operation. The writing time is a data writing time duration, in a specific implementation, the data writing time duration is determined by a writing pulse width, and the writing current and the writing pulse width can affect a retention (holding or backup) time of the written data. In this embodiment, the write strategy command is configured to include a Retention Time of write data or is a Retention Time (Retention Time) strategy, and the write strategy control method according to the present application can improve the backup Retention Time to reduce the standby energy, thereby implementing energy saving control.

In the embodiment, the backup time predictor 15 obtains the write strategy command and the write strategy confidence by receiving the future power-off time and the power-off confidence through a Neural Network, specifically, the Neural Network is, for example, a feed-forward Neural Network (feed-forward Neural Network), the feed-forward Neural Network is a Neural Network trained offline or a Neural Network trained online in a back propagation manner, and the feed-forward Neural Network has a Network structure as shown in fig. 3 or fig. 4. For example, the neural network is configured as a time backup predictor for prediction computation to obtain Write strategy instructions (Write Configuration) and Write strategy Confidence (Confidence).

The retention time controller 32 is configured to receive the write strategy command output by the backup time predictor, and execute a write operation according to at least one of information of a write current and a write time included in the write strategy command. In this embodiment, the retention time controller has one or more non-volatile shift cells, such as a non-volatile Shifter (NV Shifter), into which the retention time controller 32 stores the received write strategy instructions. The retention time controller 32 performs a write operation according to the received write strategy command, in an example, data written to the memory of the electronic device by the write operation is, for example, calculation or processing data of the processor, or a backup calculation state is recorded.

In one embodiment, the future energy predictor 11 and the bit width predictor 12 in the data bit width prediction system shown in fig. 8 can realize the prediction calculation of the future power-on time and the power-on confidence degree through a multiplexing hardware architecture.

In one embodiment, the future energy predictor 11, the bit width predictor 12 and the service quality predictor 13 in the data bit width prediction system shown in fig. 9 can realize the prediction calculation of the future power-on time, the power-on confidence and the service quality prediction information through a multiplexing hardware architecture.

In one embodiment, the future energy predictor 11, the approximate bit width predictor 12, the service quality predictor 13, the power failure predictor 14, and the backup time predictor 15 in the data bit width prediction system shown in fig. 10 may implement prediction calculation of future power-on time and power-on confidence, prediction calculation of data bit width instructions and start thresholds, prediction calculation of service quality prediction information, prediction calculation of future power-off time and power-off confidence, and prediction calculation of write strategy instructions and write strategy confidence through a multiplexing hardware architecture.

Referring to fig. 11, a schematic diagram of a multiplexing hardware architecture of the data bit width prediction system in an embodiment of the present application is shown, as shown in the drawing, a neural network module 10 in the multiplexing hardware architecture includes a neural network unit 101 and a one-time prediction state machine 102, where the neural network unit 101 includes a neuron register 1011, a weight register 1012 storing a plurality of weights, a plurality of selectors 1013 for selecting data input or output, and a multiply-accumulate unit 1014. The one-time prediction state machine 102 is used to control the timing of the neural network unit 101 receiving the at least one information for one-time prediction calculation. The neural network module 10 shown in fig. 11 is a serial architecture, and the one-time prediction state machine 102 controls the corresponding selector 1013 to select a weight value and source neurons and target neurons to be activated from the weight value register 1012 according to the input of the neural network unit 101 (for example, at least one of power supply information, power storage information, and power failure information of the electronic device obtained by the feature extraction module), and then delivers the weight value and the source neurons and the target neurons to a Multiply-and-Accumulate (MAC) unit 1014 after calculation, and then writes back the neurons in the neural network unit until all the neurons in the input layer, the hidden layer, and the output layer are processed. The weights pre-stored in the weight register 1012 are obtained by training.

In this embodiment, the weight register 1012 includes a Nonvolatile shift unit or a Nonvolatile memory unit for storing the weight corresponding to each prediction calculation, where the Nonvolatile shift unit is a Nonvolatile Shifter (NV shift), and the Nonvolatile memory unit is a Nonvolatile memory (NVM).

In the present embodiment, the one-time prediction state machine 102 has a nonvolatile shift unit or a nonvolatile storage unit for storing a timing control program, specifically, for controlling the output timing of each selector 1013 by the timing control program. The nonvolatile shift unit is a nonvolatile shifter, and the nonvolatile storage unit is a nonvolatile memory.

The timing control module 102 is configured to control a timing of a prediction calculation of at least one of a data bit width instruction (Bitwidth), a System Start instruction (System Start) or a Write policy instruction (Write Configuration) output by the neural network module 10 based on at least one of received Power supply information (Power Sensing), Power storage information (Stored Energy Sensing), and Power failure information (Power output Sensing) at least one time, so as to ensure that the plurality of prediction calculations can share one neural network module, in other words, a prediction hardware (a neural network architecture) can be used to complete functions of all the predictors.

More specifically, referring to fig. 12, a schematic diagram of a multiplexing hardware architecture of the write strategy control system according to another embodiment of the present application is shown, as shown in fig. 12, in order to enable multiple types of predictive computation to complete computation in different time periods or different time nodes in one hardware architecture in the embodiment shown in fig. 12, a hardware architecture is further specified in the present application. As shown in the figure, the neural network module 10 further includes a softmax state machine 103 and a judgment unit 104 (i.e., a portion shown in fig. 12 where OR is 0) configured in the multiply-accumulate unit. In this embodiment, to normalize the hardware architecture, a number of virtual connections are constructed in the network of the neural network module to normalize the neural network topology by inserting 0 connection Weights (i.e., Weights 1, Weights 2 … … Weights 5 of the weight registers shown in FIG. 12).

In the embodiment shown in FIG. 12, the one-time predictive state machine 102 includes a non-volatile shift unit for storing a timing control program. The schematic of the one-shot prediction state machine 102 controlling the timing of the one-shot prediction computation of the information that the neural network element receives the input is represented by the dashed arrow shown in fig. 12; the schematic of the timing control module controlling the timing of the neural network module is represented by the dotted line arrows shown in fig. 12.

When the neural network module performs one-time prediction (such as prediction of future on-off time or prediction of future power-off time), the single-time prediction state machine 102 controls the selector to output the selected weight value and the source neuron and the target neuron which need to be activated to the judging unit 104 after one-time calculation, whether any input of the judging unit 104 is 0 or not is judged, if any input is 0, the multiplier is bypassed, if any input is not 0, the multiplier multiplies and accumulates the inputs, and then the neurons in the neural network unit 101 are written back until all neurons in the input layer, the hidden layer and the output layer are processed. Finally, the softmax layer is executed under the control of the softmax state machine 103. After all steps are performed by the neural network module, the outputs of the neural network module are then selected for storage in non-volatile shift cells in the slave processor 3, and some of the outputs are updated in non-volatile memory (NVM) as shown in fig. 12 (e.g., the timing control module also controls the neural network module to update the power down information in one power up cycle; or the timing control module controls the neural network module to update the power up information in one power down cycle) for the next other prediction, such as power down prediction confidence or power up confidence. In this embodiment, the multiplier and the adder in the multiply-accumulate unit are a floating-point multiplier and a floating-point adder.

In this embodiment, the timing control module includes a nonvolatile shift unit or a nonvolatile memory unit for storing a timing control program, where the nonvolatile shift unit is a nonvolatile shifter and the nonvolatile memory unit is a nonvolatile memory.

In one embodiment, the neural network module includes one or more nonvolatile shift units and nonvolatile storage units, and the nonvolatile shift units are used for storing power supply information, power storage information and power failure information received from one or more moments of the electronic device acquired by the feature extraction module. As shown, the Power supply information (Power Sensing) and the Power failure information (Power output Sensing) are Stored in the nonvolatile shift units, the Power storage information (Stored Energy Sensing) is directly extracted from the feature extraction module 2 to the neural network module, and the nonvolatile memory stores updated information, such as the timing control module further controls the neural network module to update the Power failure information in one Power-on cycle; or the time sequence control module controls the neural network module to update the power supply information in a power failure period for next other prediction, such as power failure prediction confidence or power on confidence.

The method and the device realize various prediction calculations in different time periods through a hardware architecture of the neural network predictor, in other words, the method and the device realize the prediction calculations of a plurality of small-scale neural networks in different time periods, thereby achieving the purpose of saving hardware cost and area.

Referring to fig. 13, which is a schematic diagram illustrating an architecture of a Nonvolatile processor (NVP) according to an embodiment of the present application, as shown in the figure, the Nonvolatile processor 4 includes: a data bit width prediction system 40, an approximate bit width controller 42, and a start-up controller 41. In different implementation scenarios, the non-volatile processor may have a variety of packaging configurations depending on the requirements of different electronic devices.

The data bit width prediction system 40 is configured to dynamically predict a calculation bit width required by the processor by predicting future energy input of the electronic device, and match a system power consumption curve with a predicted power curve, so as to implement scientific and reasonable energy management, please refer to the description in the embodiments related to fig. 8 to 12, which is not described herein again.

The approximate bit width controller 42 is configured to control the calculation precision of the processor 4 according to the data bit width instruction when receiving the data bit width instruction output by the data bit width prediction system 40; the approximate bit width controller is used for controlling the precision of operation according to a data bit width instruction (Bitwidth) when the data bit width instruction is received and is configured as a bit width predictor; please refer to the description of the embodiments related to fig. 6 and fig. 9 to fig. 10, which is not repeated herein.

In this embodiment, the approximate bit width controller has one or more nonvolatile shift units, such as a nonvolatile Shifter (NV Shifter), into which the approximate bit width controller stores the received data bit width instruction. The processor is used for calculating and processing the sensing data or the interaction data acquired by the electronic equipment. In some examples, the processing of the sensed data, such as the wearable device, generates user data that may be transmitted by the wireless module or displayed by the display device by processing the collected heart rate data, blood pressure data, temperature data, blood oxygen saturation data, diet/nutrition information, medical reminders, health-related reminders or information, or other health-related data.

And the starting controller is used for starting the processor when receiving a starting instruction (System Start) output by the data bit width prediction System. In one embodiment, the start-up controller has one or more non-volatile shift cells, such as a non-volatile Shifter (NV Shifter), into which the start-up controller stores received start-up instructions. In this embodiment, the Start Controller is, for example, an NVP Start Trigger (NVP Start Trigger Controller). Please refer to the description of the embodiments related to fig. 9 to fig. 10, which is not repeated herein.

For example, if the predicted potential input energy level is relatively low and there is insufficient stored energy in the buffer capacitor, the processor is disabled; if the predicted potential input energy is high, but the received power-on confidence is low, then the processor is instructed to boot only if the stored energy level is high enough to reach the prediction threshold; if the predicted potential input energy is high and the power-on confidence is high, the processor is instructed to boot up (the predictor outputs a very low threshold) to get better forward progress and QoS satisfaction even though the stored energy is low. In one example, the energization confidence ratio is relatively low, e.g., less than 30%, and the energization confidence ratio is relatively high, e.g., greater than 70%. But not limited thereto, the threshold of the power-on confidence can be dynamically adjusted according to actual situations under the circumstance of knowing the innovative idea of the present application.

The non-volatile processor also receives Predicted QoS (Predicted QoS) output by the write strategy control system, so that the processor predicts potential output quality of an electronic device running program based on dynamic bit width execution approximation and different approximation methods in dynamic backup data retention time, and the result of the whole energy management system has QoS control.

In the embodiment, the nonvolatile processor adopts a 5-stage pipeline processor architecture, referring to fig. 6, as shown, the approximation calculation architecture includes a 5-stage pipeline processor architecture, and the approximation calculation is controlled by a dynamic architecture approximation control unit. As shown in the figure, a neural network configured as a future Energy predictor is used for predicting and calculating the future Power-on time and the Power-on confidence coefficient of the electronic equipment according to the Power supply information (Input Power), then a neural network configured as a bit width predictor is used for predicting and calculating according to the future Power-on time, the Power-on confidence coefficient and the Power storage information (Stored Energy) of the electronic equipment to obtain approximate configuration data (approximate configuration), then a bit called ACEN is added to each approximate configuration data through an approximate control unit preset with an approximate designation data (ACEN) interface to identify whether the approximate configuration data can be approximated during operation, the dynamic architecture approximation control unit reads the approximate designation data (ACEN) and the obtained approximate configuration data (approximate configuration) from two operators in an instruction, if an operator is determined to be approximated, but the other operator can not be approximated, the instruction can not be approximated, if both operators can be approximated, the data bit width instruction (Bitwidth) is generated to enable the processor to utilize the processor architecture of the 5-stage pipeline to carry out approximation calculation, and further, the calculation (operation) precision of the processor is controlled. As can be seen from the above, a bit width predictor is configured to be activated at the beginning of a programmer-predefined loop in the main program, which is typically a loop for a new frame to be processed. The configured bit width predictor is used to determine the appropriate bit width to complete the loop operation of the entire program during this power-up cycle.

Referring to fig. 14, it is shown as an architecture diagram of the neural network chip in an embodiment of the present application, and as shown in the drawing, the neural network chip 5 includes a data bit width prediction system 50. In this embodiment, the execution module 6 is, for example, a processor, such as a Nonvolatile processor (NVP), and in other cases, the execution module may also be a chip or a module external to the processor.

The data bit width prediction system 50 is configured to dynamically predict a calculation bit width required by the processor by predicting future energy input of the electronic device, and match a system power consumption curve with a predicted power curve, so as to implement scientific and reasonable energy management, please refer to the description in the embodiments related to fig. 8 to 12, which is not described herein again.

Please refer to the description of the embodiment related to fig. 10 and 13 in the above description for the approximate bit width controller 61 of the execution module 6, which is not described herein again.

Please refer to the above description of the embodiments related to fig. 10 and 13 for the start controller 60 of the execution module 6, which is not repeated herein.

In an embodiment, the neural network chip 5 may utilize one prediction hardware (a neural network architecture) to perform all the functions of the various neural network predictors. The hardware architecture of the neural network predictor is referred to the states shown in fig. 11 to fig. 12, and will not be described herein again. Under different implementation scenarios, the neural network chip can present various packaging structures according to the requirements of application to different electronic devices.

The present application also provides an electronic device (not shown) including the data bit width prediction system described in the above embodiments. In one embodiment, the electronic device is, for example, a circuit board or a card on which an integrated circuit or a chip is disposed. The circuit board is, for example, a double-layer PCB board or a multi-layer PCB board.

The present application also provides an electronic device, which in embodiments provided herein is an internet of things device, for example, a wearable device or an implantable device, such as a wearable electronic device may include any type of electronic device that may be worn on a limb of a user. The wearable electronic device may be secured to a human limb such as a wrist, ankle, arm, or leg. Such electronic devices include, but are not limited to, health or fitness assistant devices, digital music players, smart phones, computing devices or display exercise or other activity monitors, time-tellable devices, devices capable of measuring biometric parameters of a wearer or user, and the like. Such as a blood glucose test device or the like.

Referring to fig. 15, which is a schematic diagram of an embodiment of the electronic device 7 of the present application, as shown, the electronic device includes a feature extraction module 71, a data bit width prediction system 72, and a processor 73.

The feature extraction module 71 is configured to extract power-off information of the electronic device at least at one moment, for example, the embodiment described with reference to fig. 2 is not repeated here.

The data bit width prediction system 72 is configured to dynamically predict a calculation bit width required by the processor by predicting future energy input of the electronic device, and match a system power consumption curve with a predicted power curve, so as to implement scientific and reasonable energy management, please refer to the description in the embodiments related to fig. 8 to 12, which is not described herein again.

The processor 73, upon receiving a data bit width instruction (Bitwidth), performs operations to control operations by an approximate bit width controller, which is configured to control the accuracy of operations based on the data bit width instruction (Bitwidth) as output by the neural network configured as a bit width predictor. In the present embodiment, the processor 73 is, for example, a Nonvolatile processor (NVP). Please refer to the description of the embodiments related to fig. 8 to fig. 13, which is not repeated herein.

Please refer to fig. 16, which is a schematic diagram of an electronic device according to another embodiment of the present application. As shown, in an embodiment, the electronic device 7 further comprises a power supply means 70 for generating or storing electrical energy. In this embodiment, the power supply device 70 is, for example, a battery or a self-powered system, which includes an energy harvester, and the energy harvester obtains energy from human body movement, such as vibration energy from actions or behaviors of walking or swinging, jumping, pressing (such as pressure obtained by a small energy harvester implanted in a shoe during running), breathing, etc., and converts the vibration energy into electric energy, and in other cases, the energy may come from the natural environment, such as solar energy, etc. The power harvested by the power device 70 needs to be processed from AC to DC or DC to DC and then the harvested energy is temporarily stored in off-chip or even on-chip capacitors, which are used primarily to support data rather than to store energy. In one embodiment, the feature extraction module may be part of a power supply device.

In one embodiment, as shown in fig. 16, the electronic device 7 further includes one or more sensing devices 75, and the one or more sensing devices 75 are configured to sense at least one of geographical location information, ambient light information, ambient magnetic field information, sound information, temperature information, humidity information, pressure sensing information, acceleration information, ultraviolet information, blood glucose information, alcohol concentration information, pulse information, heart rate information, respiration information, and exercise amount information.

In embodiments, the sensors 75 may include various electronic, mechanical, electromechanical, optical, or other devices that provide information related to external conditions around the wearable device. In some embodiments, the sensor may provide a digital signal to the processing subsystem, for example, on a streaming basis or in response to polling by the processing subsystem, as desired. Any type of environmental sensor and combination of environmental sensors may be used; by way of example, accelerometers, magnetometers, gyroscopes and GPS receivers are shown.

Some environmental sensors may provide information about the location and/or motion of the wearable device. For example, an accelerometer may sense acceleration (relative to free fall) along one or more axes, e.g., using piezoelectric or other components in conjunction with associated electronics to generate a signal. A magnetometer may sense an ambient magnetic field (e.g., the earth's magnetic field) and generate a corresponding electrical signal that may be interpreted as a compass direction. Gyroscopic sensors may sense rotational motion in one or more directions, for example using one or more MEMS (micro-electromechanical systems) gyroscopes and associated control and sensing circuitry. A Global Positioning System (GPS) receiver may determine a location based on signals received from GPS satellites.

Other sensors may be included in addition to or in place of these examples. For example, the sound sensor may incorporate a microphone along with associated circuitry and/or program code to determine, for example, decibel levels of ambient sound, and may also include a temperature sensor, a proximity sensor, an ambient light sensor, a biometric sensor/physiological characteristic sensor such as a heartbeat, respiration, pulse, blood glucose, alcohol concentration detection sensor, and the like. In some embodiments, physiological or biometric sensors may be used to verify the identity of the wearer of the wearable device.

In one embodiment, as shown in FIG. 16, the electronic device further includes a storage device 74 for storing data output by the processor. In some examples, the storage device 74 is, for example, a Non-volatile memory (NVM), a Read-only memory (ROM), a Random Access Memory (RAM), an EEPROM, a CD-ROM or other magnetic storage device, a magnetic disk storage device or other magnetic storage device, a flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium.

In one embodiment, as shown in fig. 16, the electronic device further includes a wireless communication module 76 for transmitting data output by the processor or receiving data wirelessly transmitted by an external device. The communication interface of the wireless communication module 76 may be, for example, but not limited to, a wireless interface, a Bluetooth interface, a USB interface, a Wi-Fi interface, a TCP/IP interface, a network communication interface, or any conventional communication interface.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be in the form of an indirect coupling or communication connection through some interfaces, devices or units.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The present application also provides a computer-readable storage medium storing an energy management computer program, which when executed implements the data bit width prediction method described above with respect to fig. 1, 5, and 7.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application.

In the embodiments provided herein, the computer-readable and writable storage medium may include Read-only memory (ROM), random-access memory (RAM), EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, a usb disk, a removable hard disk, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable-writable storage media and data storage media do not include connections, carrier waves, signals, or other transitory media, but are intended to be non-transitory, tangible storage media. Disk and disc, as used in this application, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

The above embodiments are merely illustrative of the principles and utilities of the present application and are not intended to limit the application. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical concepts disclosed in the present application shall be covered by the claims of the present application.

Claims

1. A data bit width prediction method is applied to an electronic device with a processor, and is characterized by comprising the following steps:

acquiring power supply information of the electronic equipment at least one moment;

predicting and calculating the future power-on time and the power-on confidence coefficient of the electronic equipment by a neural network according to the power supply information; and

performing prediction calculation according to the future power-on time, the power-on confidence coefficient and the power storage information of the electronic equipment to obtain approximate configuration data; and identifying the approximate configuration data according to preset approximate marking data, and performing approximate calculation to generate a data bit width instruction when the approximate configuration data can be approximately calculated, so that the processor performs operation according to the data bit width instruction.

2. The method for predicting bit width of data according to claim 1, wherein the step of obtaining power supply information of the electronic device at least at one time is obtaining power supply information of the electronic device at least at one time when it is detected that the electronic device is powered on.

3. The method for predicting the bit width of data according to claim 1, wherein the step of obtaining the power supply information of the electronic device at least at one time is to obtain the power supply information of the electronic device by collecting a current value flowing through a detection element or a voltage value across the detection element at least one time.

4. The method for predicting the bit width of data according to claim 1, wherein in the step of performing the approximate calculation according to the future power-on time, the power-on confidence level, and the power storage information of the electronic device to obtain the data bit width instruction, the power storage information is obtained by collecting a voltage drop of an energy storage element.

5. The method of claim 1, wherein the step of performing an approximate calculation according to the future power-on time, the power-on confidence level, and the power storage information of the electronic device to obtain the data bit width instruction comprises performing an approximate calculation by a neural network according to the future power-on time, the power-on confidence level, and the power storage information of the electronic device to obtain the data bit width instruction.

6. The method for predicting the bit width of data according to claim 1 or 5, wherein the step of performing an approximate calculation according to the future power-on time, the power-on confidence level, and the power storage information of the electronic device to obtain the data bit width instruction further comprises: and performing approximate calculation according to the future power-on time, the power-on confidence coefficient and the power storage information of the electronic equipment to predict and output a starting threshold value.

7. The method for predicting data bit width according to claim 1, wherein the step of performing approximate calculation to predict an output enable threshold according to the power storage information, the future power-on time and the power-on confidence level comprises:

performing prediction calculation according to the data bit width instruction and outage information to obtain service quality prediction information, wherein the outage information comprises outage confidence;

outputting the service quality prediction information to the processor when the service quality prediction information meets a preset condition; and outputting a starting instruction to the processor when the starting threshold meets the preset condition.

8. The method of claim 6, wherein the step of performing a prediction calculation according to the data bit width command and the power-off information to obtain QoS prediction information comprises performing a prediction calculation according to the data bit width command and the power-off information by using a neural network to obtain QoS prediction information.

9. A data bit width prediction system applied to an electronic device with a processor is characterized by comprising

The future energy predictor is used for predicting the future power-on time and the power-on confidence coefficient of the electronic equipment by a neural network according to the power supply information of the electronic equipment at least one moment; and

the bit width predictor is used for performing prediction calculation according to the future power-on time, the power-on confidence coefficient and the power storage information of the electronic equipment to obtain approximate configuration data; and identifying the approximate configuration data according to preset approximate marking data, and performing approximate calculation to generate a data bit width instruction when the approximate configuration data can be approximately calculated, so that the processor performs operation according to the data bit width instruction.

10. The data bit width prediction system of claim 9, wherein the future energy predictor obtains power supply information for the electronic device at least one time when the electronic device is detected to be powered on by the future energy predictor.

11. The system according to claim 9, wherein the future energy predictor obtains power supply information and power storage information of the electronic device at least one time by a feature extraction module.

12. The system according to claim 11, wherein the feature extraction module obtains power supply information of the electronic device by collecting a current value flowing through a detection element or a voltage value across the detection element at least one time and obtains the power storage information by collecting a voltage drop across an energy storage element.

13. The data bit width prediction system of claim 9, wherein the future energy predictor comprises one or more non-volatile shift units to store the supply information.

14. The system according to claim 9, wherein the bit width predictor performs approximate calculation by a neural network according to the future power-on time, the power-on confidence and the power storage information of the electronic device to obtain the data bit width instruction.

15. The data bit width prediction system of claim 9, wherein the bit width predictor is further configured to perform an approximate calculation to predict an output launch threshold based on the future power-on time, a power-on confidence, and power storage information of the electronic device.

16. The data bit width prediction system according to claim 15, further comprising a quality of service predictor, configured to perform prediction calculation according to the data bit width command and power-off information to obtain quality of service prediction information, and output the quality of service prediction information to the processor when the quality of service prediction information satisfies a predetermined condition; outputting a starting instruction to the processor when the starting threshold meets the preset condition; the power outage information includes a power outage confidence.

17. The system according to claim 16, wherein the qos predictor obtains qos prediction information by performing prediction calculation through a neural network according to the data bit width instruction and power-off information.

18. The data bit width prediction system of claim 9, wherein the processor is a non-volatile processor.

19. A non-volatile processor, comprising:

the data bit width prediction system of any of claims 9-18;

the approximate bit width controller is used for controlling the calculation precision of the processor according to the data bit width instruction when receiving the data bit width instruction output by the data bit width prediction system;

and the starting controller is used for starting the work of the processor when receiving a starting instruction output by the data bit width prediction system.

20. A neural network chip, comprising the data bit width prediction system of any one of claims 9-18.

21. An electronic device comprising a processor the data bit width prediction system according to any one of claims 9-18.

22. A computer-readable storage medium storing a computer program for energy management, wherein the computer program is configured to implement the data bit width prediction method according to any one of claims 1 to 8 when executed.