CN109087684B - Data channel aging circuit, memory and aging method thereof - Google Patents
Data channel aging circuit, memory and aging method thereof Download PDFInfo
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- CN109087684B CN109087684B CN201811202829.4A CN201811202829A CN109087684B CN 109087684 B CN109087684 B CN 109087684B CN 201811202829 A CN201811202829 A CN 201811202829A CN 109087684 B CN109087684 B CN 109087684B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The present disclosure provides a data channel aging circuit, a memory, a data channel aging method, and a memory aging method. The data channel aging circuit in the embodiment of the disclosure comprises a storage unit, wherein the storage unit stores a voltage switching signal for providing a target voltage state for each data channel in the integrated circuit; the control unit is used for generating a voltage control signal and sending the voltage control signal to each data channel; and the gating unit is used for switching the conducting state of each data channel based on the voltage switching signal, and adjusting the voltage level of each data channel by utilizing the voltage control signal so as to generate voltage stress aging. The data channel aging circuit provided by the embodiment of the disclosure can improve the reliability of the aging test result and improve the working stability of the integrated circuit product after the aging test.
Description
Technical Field
The disclosure relates to the field of electrical technology, and in particular relates to a data channel aging circuit, a memory, a data channel aging method and a memory aging method.
Background
As an important link in the production process of the integrated circuit, the aging test enables defects of the integrated circuit to be exposed as early as possible in the test stage through continuous or periodical overload work for a period of time, thereby reducing the probability of failure of the integrated circuit product in the initial use stage and improving the stability and reliability of the integrated circuit product.
Burn-in testing of integrated circuits generally involves an integrated circuit burn-in machine that can transmit data to the integrated circuit under test via a test channel under certain external test conditions (e.g., high temperature, bias, etc.) to accelerate burn-in of the integrated circuit in an operating state. Due to the limited test channels, the number of integrated circuits that can be burn-in tested at the same time will also be limited. Therefore, in order to increase the number of integrated circuits tested together, only a part of data channels in the integrated circuits can be selected for data transmission in a data compression mode, so that the burn-in test efficiency of the integrated circuits can be improved.
However, the burn-in test performed in the data compression mode can only achieve the test purpose for a part of the data channels of the integrated circuit, and whether the data channels which are not subjected to the burn-in test have defects or not can not be detected, so that even the integrated circuit which passes the burn-in test still has a certain hidden trouble. Therefore, how to improve the reliability of the burn-in test without affecting the test efficiency is a current urgent problem to be solved.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The disclosure provides a data channel aging circuit, a memory, a data channel aging method and a memory aging method, and further solves the technical problem of poor reliability of an aging test result caused by the limitation of the related art at least to a certain extent.
According to one aspect of the present disclosure, there is provided a data channel burn-in circuit for performing burn-in test on an integrated circuit, the data channel burn-in circuit comprising:
a memory unit in which a voltage switching signal for providing a target voltage state for each data channel in the integrated circuit is stored;
the control unit is used for generating a voltage control signal and sending the voltage control signal to each data channel;
and the gating unit is used for switching the conducting state of each data channel based on the voltage switching signal, and adjusting the voltage level of each data channel by utilizing the voltage control signal so as to generate voltage stress aging.
In an exemplary embodiment of the present disclosure, the control unit includes:
the signal input end is used for receiving an aging control signal;
the voltage converter is used for generating the voltage control signal after performing voltage conversion on the aging control signal;
and the signal output end is used for sending the voltage control signals to the data channels.
In one exemplary embodiment of the present disclosure, the voltage converter includes:
one end of the first capacitor is connected with the signal input end, and the other end of the first capacitor is connected with an intermediate node;
a first semiconductor switch, a first pole of which is connected with the intermediate node, and a second pole and a grid of which are connected with a first voltage terminal;
a second semiconductor switch, a first pole of which is connected with the signal output end, and a second pole and a grid of which are connected with the intermediate node;
and one end of the second capacitor is connected with the second voltage end, and the other end of the second capacitor is connected with the signal output end.
In an exemplary embodiment of the present disclosure, the voltage converter further includes:
and the inverter is positioned between the signal input end and the first capacitor.
In an exemplary embodiment of the disclosure, the voltage level of the first voltage terminal is an operating voltage of the integrated circuit, and the voltage level of the second voltage terminal is a ground voltage.
In an exemplary embodiment of the present disclosure, the gating unit includes:
and the decoder is used for decoding the voltage switching signals stored in the storage units and placing part of the data channels in the on state based on the voltage switching signals.
In an exemplary embodiment of the present disclosure, the gating unit is connected to all or part of the data paths of the integrated circuit.
According to one aspect of the present disclosure, there is provided a memory, which is characterized by comprising a data channel burn-in circuit according to any of the above exemplary embodiments, the data channel burn-in circuit being configured to perform a burn-in test on an integrated circuit of the memory.
According to one aspect of the present disclosure, there is provided a data channel burn-in method for burn-in testing an integrated circuit, the method comprising:
determining a target voltage state of each data channel in the integrated circuit according to the voltage switching signal;
switching on states of the data channels based on the voltage switching signals;
the voltage level of each data channel is adjusted by a voltage control signal to generate voltage stress aging.
According to one aspect of the present disclosure, there is provided a memory burn-in method, the memory including an integrated circuit having a plurality of data channels, wherein a part of the data channels are machine burn-in data channels, and another part of the data channels are voltage burn-in data channels; the method comprises the following steps:
connecting the machine aging data channel to an integrated circuit aging machine, and transmitting data to the machine aging data channel by using the integrated circuit aging machine;
determining a target voltage state of the voltage aging data channel according to a voltage switching signal;
switching on states of the voltage aging data channels based on the voltage switching signals;
the voltage level of the voltage aging data channel is adjusted by a voltage control signal to generate voltage stress aging.
In the data channel aging circuit provided by the embodiment of the disclosure, the voltage states of the data channels can be switched to generate voltage stress aging by sending the voltage control signals to the data channels in the integrated circuit and matching with corresponding voltage switching signals. Therefore, the effect of performing the aging test on all or most of the data channels of the integrated circuit can be realized, thereby improving the reliability of the aging test result and improving the working stability of the integrated circuit product after the aging test.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.
Fig. 1 is a schematic diagram of a data channel aging circuit in an exemplary embodiment of the present disclosure.
Fig. 2 is a schematic diagram of a control unit portion of a data channel aging circuit according to an exemplary embodiment of the present disclosure.
Fig. 3 is a flow chart of steps of a data channel aging method in an exemplary embodiment of the present disclosure.
Fig. 4 is a flowchart of steps of a memory burn-in method in an exemplary embodiment of the present disclosure.
Wherein reference numerals are as follows:
11-a memory unit;
12-a control unit;
13-a gating unit;
201-a signal input;
202-a first capacitance;
203-an inverter;
204-intermediate nodes;
205-a first semiconductor switch;
206-a first voltage terminal;
207-a second semiconductor switch;
208-a second capacitance;
209-a second voltage terminal;
210-signal output.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.
Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and do not limit the number of their objects.
In an exemplary embodiment of the present disclosure, a data channel burn-in circuit is provided for burn-in testing an integrated circuit, and may particularly achieve the effect of burn-in testing all or most of the data channels of the integrated circuit, where the data channels refer to data input/output paths (I/O paths) in the integrated circuit.
As shown in fig. 1, the data channel aging circuit mainly includes a memory unit 11, a control unit 12, and a strobe unit 13. The memory cell 11 and the control unit 12 are connected to the strobe unit 13, respectively, and the strobe unit 13 is connected to the respective data channels DQ0, DQ1 … … DQn of the integrated circuit. The data channels may be all data channels of the integrated circuit or may be part of data channels of the integrated circuit, which is not particularly limited in the present exemplary embodiment.
The memory unit 11 stores therein a voltage switching signal for providing a target voltage state for each data channel in the integrated circuit. The target voltage state may be a High potential (High) state or a Low potential (Low) state, and each data channel may be switched between the two potential states. The target voltage state of each data channel can be obtained by using the voltage switching signal stored in the memory unit 11, so that a reference and a basis can be provided for the subsequent voltage control.
The control unit 12 is used for generating and sending voltage control signals to the various data channels in the integrated circuit. The voltage control signal may be used to raise or lower the voltage level in each data channel. For example, the background voltage in a certain data channel is originally at a relatively low voltage level, and the voltage control signal is a high-potential voltage signal with the same phase, so that the data channel will pull up its voltage level under the influence of the voltage control signal. The effect of the voltage control signal on the voltage level of each data channel is also that of reducing the voltage level, and depends on different voltage control signals and on the conduction state of each data channel.
The gating unit 13 may adjust the on state of each data channel by adjusting the on state of each data channel, specifically, based on the voltage switching signal stored in the storage unit 11, and adjust the voltage level of each data channel by using the voltage control signal sent by the control unit 12, so that each data channel is in a high potential state or a low potential state respectively. The data channel selected to be conducted will be pulled up or lowered down its voltage level under the action of the voltage control signal. In addition, the voltage switching signal will also change to cause the voltage level of each data channel to be in a dynamic process. The effect that the background voltages of all the data channels are different can be achieved through a voltage switching mode, so that voltage stress aging is generated on all the data channels.
In the data channel aging circuit provided in this exemplary embodiment, the voltage states of the data channels may be switched to generate voltage stress aging by sending a voltage control signal to each data channel in the integrated circuit and matching with a corresponding voltage switching signal. In the process of performing the burn-in test on the integrated circuit, a part of data channels of the integrated circuit are connected to the burn-in machine of the integrated circuit, the part of data channels are in a working state of data input/output, and other data channels which are not connected can be used for performing voltage stress burn-in by using the data channel burn-in circuit in the exemplary embodiment, so that the effect of performing the burn-in test on all or most of the data channels of the integrated circuit can be realized, the reliability of the burn-in test result is improved, and the working stability of the integrated circuit product after the burn-in test is improved.
On the basis of the above exemplary embodiment, the control unit 12 may further include: a signal input, a voltage converter and a signal output.
The signal input terminal is used for receiving a burn-in control signal, and the burn-in control signal can be a control signal read from the outside of the integrated circuit. In the burn-in test of the integrated circuit, after entering the burn-in test mode, the data channel burn-in circuit can be started to perform voltage stress burn-in on each data channel by reading the burn-in control signal.
The voltage converter is used for performing voltage conversion on the received aging control signal and then generating a voltage control signal. The voltage converter may be a conventional DC-DC converter, for example a charge pump. In addition, any other electronic component or circuit configuration unit capable of realizing voltage boosting, voltage dropping or voltage inverting may be used as the voltage converter, and the exemplary embodiment is not particularly limited thereto.
The signal output terminal is used for sending the voltage control signal to each data channel, and the signal output terminal may be directly connected to each data channel, or may be indirectly connected to each data channel through the gating unit 13, which is not limited in particular in this exemplary embodiment.
The voltage converter in the present exemplary embodiment may employ a switched capacitor type circuit configuration unit as shown in fig. 2. One end of the first capacitor 202 is connected to the output end of the inverter 203, the input end of the inverter 203 is connected to the signal input end 201, and the other end of the first capacitor 202 is connected to an intermediate node 204.
A first pole of the first semiconductor switch 205 is connected to the intermediate node 204, and a second pole and a gate of the first semiconductor switch 205 are connected to the first voltage terminal 206. The voltage level of the first voltage terminal 206 may be an operating voltage of the integrated circuit.
A first pole of the second semiconductor switch 207 is connected to the signal output 210 and a second pole and gate of the second semiconductor switch 207 are connected to the intermediate node 204.
One end of the second capacitor 208 is connected to the second voltage terminal 209, and the other end of the second capacitor 208 is connected to the signal output terminal 210. The voltage level of the second voltage terminal 209 may be a ground voltage.
In an exemplary embodiment of the present disclosure, the gating unit 13 may include a decoder for decoding the voltage switching signal stored in the memory unit 11 and placing a portion of the data channels in the on state based on the voltage switching signal. For example, the voltage switching signal stored in the memory cell 11 may be a logical string composed of 0 and 1 corresponding to each data channel arranged in order, wherein 0 represents a low potential state and 1 represents a high potential state. The target voltage state of each data channel can be obtained to be a high potential state or a low potential state by decoding the logic character string. Each data channel may form a plurality of potential states as shown in table 1, with different potential states being controlled by different voltage switching signals.
Table 1 potential state switching table for each data channel
| State 1 | State 2 | …… | State m | |
| DQ0 | High | Low | …… | Low |
| DQ1 | Low | High | …… | Low |
| …… | …… | …… | …… | …… |
| DQn | Low | Low | …… | High |
On the basis of the data channel aging circuit provided by the above exemplary embodiment, the present disclosure further provides a data channel aging method for performing an aging test on an integrated circuit. As shown in fig. 3, the method may mainly include the steps of:
and S310, determining the target voltage state of each data channel in the integrated circuit according to the voltage switching signal.
The method comprises determining target voltage states of data channels in an integrated circuit according to voltage switching signals stored in a memory cell. The target voltage state may be a High potential (High) state or a Low potential (Low) state, and each data channel may be switched between the two potential states. The target voltage state of each data channel can be obtained by using the voltage switching signal stored in the memory unit 11, so that a reference and a basis can be provided for the subsequent voltage control.
And S320, switching the conducting state of each data channel based on the voltage switching signal.
The gate unit may selectively turn on the respective data channels based on the voltage switching signal stored in the memory unit. For example, if the target voltage state of some of the data channels is a high state, the gating unit may select to turn on the data channels.
Step S330, the voltage control signal is used to adjust the voltage level of each data channel to generate voltage stress aging.
The voltage control signal sent by the control unit can be used for adjusting the voltage level of each data channel so as to generate voltage stress aging. For example, if the voltage control signal is used to pull up the voltage level of the data channel selected to be turned on in step S320, the voltage level of some other data channels is relatively lowered; if the voltage control signal is used to decrease the voltage level of the data channels selected to be turned on in step S320, the voltage level of some other data channels is relatively increased.
The data channel aging method provided by the exemplary embodiment can achieve the purpose of generating voltage stress aging by switching the background voltage of each data channel in the integrated circuit, thereby realizing the aging test of all the data channels in the integrated circuit.
In another exemplary embodiment of the present disclosure, a memory is provided that includes a data channel burn-in circuit as provided in the above embodiments for burn-in testing an integrated circuit of the memory. When the memory is subjected to burn-in test, part of the data channels in the memory can be subjected to machine burn-in by using an integrated circuit burn-in machine, and the other part of the data channels can be subjected to voltage stress burn-in by using a data channel burn-in circuit.
On the basis of the exemplary embodiment, a memory aging method is provided. The memory for burn-in test by the method comprises an integrated circuit with a plurality of data channels, wherein one part of the data channels are machine burn-in data channels, and the other part of the data channels are voltage burn-in data channels.
As shown in fig. 4, the memory aging method provided in the present exemplary embodiment may mainly include the following steps:
and S410, connecting the machine aging data channel to the integrated circuit aging machine, and transmitting data to the machine aging data channel by using the integrated circuit aging machine.
The method comprises the steps of connecting a memory to an integrated circuit burn-in machine, specifically connecting a machine burn-in data channel to a test channel of the integrated circuit burn-in machine, and transmitting data to the machine burn-in data channel by the integrated circuit burn-in machine after entering a burn-in test mode.
And S420, determining a target voltage state of the voltage aging data channel according to the voltage switching signal.
In the aging test mode, the data channel aging circuit can synchronously read an aging control signal, and under the driving of the aging control signal, the voltage stress aging process of the voltage aging data channel is started. Specifically, the target voltage state of each data channel in the integrated circuit is determined according to the voltage switching signals stored in the memory cells. The target voltage state may be a High potential (High) state or a Low potential (Low) state, and each data channel may be switched between the two potential states. The target voltage state of each data channel can be obtained by using the voltage switching signal stored in the memory unit 11, so that a reference and a basis can be provided for the subsequent voltage control.
And S430, switching the conducting state of the voltage aging data channel based on the voltage switching signal.
The gate unit may selectively turn on the respective data channels based on the voltage switching signal stored in the memory unit. For example, if the target voltage state of some of the data channels is a high state, the gating unit may select to turn on the data channels.
Step S440, the voltage control signal is used to adjust the voltage level of the voltage aging data channel to generate voltage stress aging.
The voltage control signal sent by the control unit can be used for adjusting the voltage level of each data channel so as to generate voltage stress aging. For example, if the voltage control signal is used to pull up the voltage level of the data channel selected to be turned on in step S320, the voltage level of some other data channels is relatively lowered; if the voltage control signal is used to decrease the voltage level of the data channels selected to be turned on in step S320, the voltage level of some other data channels is relatively increased.
The memory aging method provided by the exemplary embodiment can achieve the purpose of generating voltage stress aging by switching the background voltage of the voltage aging data channels in the memory, thereby realizing the aging test of all the data channels in the integrated circuit. After the aging of the machine and the aging of the voltage stress, the data input and output test is carried out on the memory, if the data transmission error occurs, the memory can be judged to be faulty, so that the memory product with poor reliability can be judged in advance, the reliability of the aging test result is improved, and the working stability of the integrated circuit product after the aging test is improved.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (7)
1. A data channel burn-in circuit for burn-in testing an integrated circuit, the data channel burn-in circuit comprising:
a memory unit in which a voltage switching signal for providing a target voltage state for each data channel in the integrated circuit is stored, the voltage switching signal being a logical character string composed of 0 and 1 corresponding to each data channel arranged in order, 0 representing a low potential state, and 1 representing a high potential state;
the control unit is used for generating a voltage control signal and sending the voltage control signal to each data channel;
a gate unit for switching on states of the data channels based on the voltage switching signals, and adjusting voltage levels of the data channels by using the voltage control signals to generate voltage stress aging;
wherein the control unit includes:
the signal input end is used for receiving an aging control signal;
the voltage converter is used for generating the voltage control signal after performing voltage conversion on the aging control signal;
the signal output end is used for sending the voltage control signals to the data channels;
wherein the voltage converter comprises:
one end of the first capacitor is connected with the signal input end, and the other end of the first capacitor is connected with an intermediate node;
a first semiconductor switch, a first pole of which is connected with the intermediate node, and a second pole and a grid of which are connected with a first voltage terminal;
a second semiconductor switch, a first pole of which is connected with the signal output end, and a second pole and a grid of which are connected with the intermediate node;
one end of the second capacitor is connected with the second voltage end, and the other end of the second capacitor is connected with the signal output end;
wherein the gating unit includes:
and the decoder is used for decoding the voltage switching signals stored in the storage units and placing part of the data channels in the on state based on the voltage switching signals.
2. The data channel aging circuit of claim 1, wherein the voltage converter further comprises:
and the inverter is positioned between the signal input end and the first capacitor.
3. The data channel burn-in circuit of claim 1 wherein the voltage level of said first voltage terminal is an operating voltage of said integrated circuit and the voltage level of said second voltage terminal is a ground voltage.
4. The data channel burn-in circuit of claim 1 wherein said gating cell is coupled to all or a portion of a data channel of said integrated circuit.
5. A memory comprising a data channel burn-in circuit as claimed in any one of claims 1 to 4 for performing burn-in testing of an integrated circuit of the memory.
6. A data channel burn-in method for burn-in testing an integrated circuit, applied to the data channel burn-in circuit of any one of claims 1 to 4, the method comprising:
determining a target voltage state of each data channel in the integrated circuit according to the voltage switching signal;
switching on states of the data channels based on the voltage switching signals;
the voltage level of each data channel is adjusted by a voltage control signal to generate voltage stress aging.
7. A memory burn-in method, said memory comprising an integrated circuit having a plurality of data channels, wherein a portion of said data channels are machine burn-in data channels and another portion of said data channels are voltage burn-in data channels; the method comprises the following steps:
connecting the machine aging data channel to an integrated circuit aging machine, and transmitting data to the machine aging data channel by using the integrated circuit aging machine;
determining a target voltage state of the voltage aging data channel according to a voltage switching signal;
switching on states of the voltage aging data channels based on the voltage switching signals;
the voltage level of the voltage aging data channel is adjusted by a voltage control signal to generate voltage stress aging.
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| PCT/CN2019/110551 WO2020078265A1 (en) | 2018-10-16 | 2019-10-11 | Data channel aging circuit, memory and aging method |
| US17/230,829 US11367506B2 (en) | 2018-10-16 | 2021-04-14 | Data channel aging circuit, memory and aging method |
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