CN109086520A - A method of improving synchronous logic real time execution reliability - Google Patents
A method of improving synchronous logic real time execution reliability Download PDFInfo
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- CN109086520A CN109086520A CN201810868564.5A CN201810868564A CN109086520A CN 109086520 A CN109086520 A CN 109086520A CN 201810868564 A CN201810868564 A CN 201810868564A CN 109086520 A CN109086520 A CN 109086520A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Abstract
The invention discloses a kind of methods for improving synchronous logic real time execution reliability, pass through specification circuit design, the insertion automation modification netlist step in EDA process, redundant circuit is inserted into netlist, improve the reliability of circuit, including original sync logic, it is characterized by also including VOTEs decision logic parts, it is inserted into VOTEs decision logic part by combinational logic part and the duplication of sequential logic part and in feedback and output stage, so that original sync logic be made to be converted into the novel synchronous logic circuit of reliability optimization.
Description
Technical field
The present invention relates to sync logic technical field, specifically a kind of raising synchronous logic real time execution is reliable
The method of property.
Background technique
It is widely applied now with chip technology in the high reliable request field such as automotive electronics, unmanned plane, automatic Pilot, with
And chip technology becomes closer to physics limit, the highly reliable demand of Key Circuit is more and more important, and electronic system needs to enhance
That externally interferes is immune, it is desirable to reduce or reduce by electromagnetic interference, the mistake such as soft failure of high energy particle generation generates when occurring
Influence, especially require harsh field, fault recovery and immunocompetence to chip to safe and reliable in unmanned plane, traffic etc.
It is expected that very high, it might even be possible to sacrifice at obtaining these reliabilities originally.
Design of Digital Circuit, can be abstracted into circuit unified form, can usually regard an input synchronizer as, behind
Connect a Mealy machine.
Under extraneous disturbed condition, wrong overturning may occur for the state of state machine, this can form burst several periods
Failure in addition chromic trouble.If these failures can disappear after the reset, general we are known as soft failure.
Normal circuit soft failure is minimum probability event, accordingly, it is considered to which a possibility that many places soft failure occurs simultaneously is non-
Often low, if being avoided that the generation of certain partial circuit single-bit soft failure, we, which are just believed that, avoids soft failure.
Summary of the invention
The purpose of the present invention is to provide a kind of pair of common synchronization logic circuits to carry out abstract decomposition, is then automated
Adjustment and circuit insertion, in conjunction with the control of layout, can reach raising circuit reliability, keep circuit dry to cosmic ray, electromagnetism
Disturbing single-bit soft failure caused by equal direct fault locations mode has immune ability.
Technical solution used by the present invention solves the above problems is: the side of the raising synchronous logic real time execution reliability
Method, including original sync logic, it is characterised in that: further include VOTEs decision logic part, by combinational logic part and
Sequential logic part replicates and is inserted into VOTEs decision logic part in feedback and output stage, to make original sync logic
It is converted into the novel synchronous logic circuit of reliability optimization；The original sync logic possesses single clock, input letter
Signal after number synchronizing for synchronization signal or synchronized device, input signal enter combinational logic part, combinational logic part according to
Current input and current internal buffer status codetermine next value and output for clapping internal register, and original synchronize is patrolled
The combinational logic part and sequential logic part collected in circuit carry out n times duplication, so that every bit sequential logic register all obtains
Error correcting capability centainly is obtained, the sequence feedback access of each circuit is then cut off, is inserted into VOTEs decision logic part, is determined defeated
Drive the sequential logic partial feedback of original combinational logic partial response to circuit output port out.
Further, the value of the number of copy times n is 3 or more.
Further, VOTEs decision logic part is realized using resistance combining judgement output circuit comprising n
Logic level is exported, when there is no when mistake, output logic level having the same is equivalent to normal logic electricity for circuit
Mouth of clearing has been connected the resistance of R/n, and when wherein mistake occurs for x bit, level compares on the contrary, being equivalent to n-x at this time
It is special correct, there is x bit level opposite or opens a way, as long as at this point, output level still meets the requirement of Vth and has a margin,
The single channel still can work normally, to have fault-tolerant ability.
Further, the invention also includes optimization processing step, the optimization processing step includes netlist PARSER, netlist
Analysis and netlist modification, are completed in optimization process using automatic method, in the generation net of original sync logic
The optimization processing step is inserted into after the process of table to realize the automation of circuit conversion.
The present invention proposes to set for the universal redundancy of one kind of Synchronization Design circuit unit from the angle of circuit structure
Meter method can achieve and instant soft failure is immunized, and maintenance time be got to certain local chronic frustrations, so that failure influences drop
The effect of grade；Specifically, by specification circuit design, insertion automation modification netlist step, is inserted in netlist in EDA process
Enter redundant circuit, improves the reliability of circuit, have the advantage that
1, there is immune and automatic recovery ability for most of soft failure failure；
2, having for part hard failure, which reduces failure, influences grade, obtains the ability of maintenance time；
3, The present invention gives specific EDA to automate operational feasibility, can promote on a large scale.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the original sync logic in the present invention.
Fig. 2 is the novel synchronous logic circuit of the reliability optimization in the present invention.
Fig. 3 is the resistance combining judgement output circuit in the present invention.
Fig. 4 is the three input resistances combining judgement waveform diagram in the present invention
Fig. 5 is the original EDA process selected parts figure in the present invention.
Fig. 6 is the EDA process selected parts figure after present invention insertion optimization processing step.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Embodiment 1.
As shown in Fig. 1 to 2, the method that one of embodiment of the present invention improves synchronous logic real time execution reliability, packet
Original sync logic is included, further includes VOTEs decision logic part, is replicated by combinational logic part and sequential logic part
And it is inserted into VOTEs decision logic part in feedback and output stage, so that original sync logic be made to be converted into reliability optimization
Novel synchronous logic circuit；The original sync logic possesses single clock, and input signal is synchronization signal or warp
Synchronizer synchronize after signal, input signal enters combinational logic part, and combinational logic part is according to current input and current
Internal register state codetermines next value and output for clapping internal register and the circuit of register output can be seen
It is that internal register direct break-through in combinational logic part is primary at output.By the combinational logic in original sync logic
Part and sequential logic part carry out n times duplication, preferably, the value of number of copy times n is 3 or more, so that every bit timing
Logic register all obtains certain error correcting capability, then cuts off the sequence feedback access (in figure No. X) of each circuit, inserts
Enter VOTEs decision logic part, determines the sequential logic partial feedback of the original combinational logic partial response of output driving to electricity
Road output port, the VOTEs decision logic part can be accomplished in several ways.
As shown in figure 3, the VOTEs decision logic part in the present embodiment is realized using resistance combining judgement output circuit,
It includes n output logic level, when there is no when mistake, output logic level having the same is equivalent to just for circuit
Normal logic level exports the resistance for the R/n that connected, and when wherein mistake occurs for x bit (level is opposite), is equivalent at this time
There is n-x bit correct, x bit level is opposite or opens a way (worst case is that x level is opposite), as long as at this point, output
Level still meets the requirement of Vth and has a margin, then the single channel still can work normally, to have fault-tolerant ability.With n=3
For, when mistake occurs all the way for certain of decision circuit, it is such as shorted to GND, output voltage will be varied, but still can be normal
It receives, as shown in Figure 4.
The present embodiment further includes optimization processing step, the optimization processing step include netlist PARSER, netlist analysis and
Netlist modification, realize during using automatic method (EDA) complete, original process as shown in figure 5, original process life
At optimization processing step is inserted into after the step of netlist, original process is converted into process shown in fig. 6, realize circuit conversion from
Dynamicization.
It should be pointed out that being above schematical by the detailed description that preferred embodiment carries out technical solution of the present invention
And not restrictive.Those skilled in the art can be to recorded in embodiment on the basis of reading description of the invention
Technical solution modify or equivalent replacement of some of the technical features, and these are modified or replaceed, not
The essence of corresponding technical solution is set to be detached from the range of technical solution of the embodiment of the present invention.
Claims (4)
1. a kind of method for improving synchronous logic real time execution reliability, including original sync logic, it is characterised in that: also
Including VOTEs decision logic part, it is inserted by combinational logic part and the duplication of sequential logic part and in feedback and output stage
VOTEs decision logic part, so that original sync logic be made to be converted into the novel synchronous logic circuit of reliability optimization；
The original sync logic possesses single clock, input signal is synchronization signal or synchronized device synchronize after letter
Number, input signal enters combinational logic part, and combinational logic part is total according to current input and current internal buffer status
With determine it is next clap internal register value and output, by original sync logic combinational logic part and sequential logic
Part carries out n times duplication and then cuts off each electricity so that every bit sequential logic register all obtains certain error correcting capability
The sequence feedback access on road is inserted into VOTEs decision logic part, determine the original combinational logic partial response of output driving when
Sequence logical gate feeds back to circuit output port.
2. a kind of method for improving synchronous logic real time execution reliability according to claim 1, it is characterised in that: described
The value of number of copy times n is 3 or more.
3. a kind of method for improving synchronous logic real time execution reliability according to claim 1, it is characterised in that: described
It is realized using resistance combining judgement output circuit VOTEs decision logic part comprising n output logic level, when circuit does not have
When having generation mistake, output logic level having the same is equivalent to the electricity that normal logic level exports the R/n that connected
Resistance, when wherein x bit occurs wrong, level has x bit level on the contrary, to be equivalent to n-x bit at this time correct
Opposite or open circuit, as long as the single channel still can work normally at this point, output level still meets the requirement of Vth and has a margin,
To have fault-tolerant ability.
4. a kind of method for improving synchronous logic real time execution reliability according to claim 1, it is characterised in that: also wrap
Optimization processing step is included, the optimization processing step includes netlist PARSER, netlist analysis and netlist modification, in optimization processing mistake
It is completed in journey using automatic method, the optimization processing step is inserted into after the process of the generation netlist of original sync logic
The rapid automation to realize circuit conversion.
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| CN201810868564.5A CN109086520A (en) | 2018-08-02 | 2018-08-02 | A method of improving synchronous logic real time execution reliability |
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| US20020162086A1 (en) * | 2001-04-30 | 2002-10-31 | Morgan David A. | RTL annotation tool for layout induced netlist changes |
| US20030125925A1 (en) * | 2001-12-27 | 2003-07-03 | Walther John Stephen | Batch editor for netlists described in a hardware description language |
| CN101615211A (en) * | 2009-08-04 | 2009-12-30 | 复旦大学 | Commercial on-spot programmable device is used for the anti-irradiance method of triplication redundancy under the radiation environment |
| CN102033772A (en) * | 2010-12-28 | 2011-04-27 | 复旦大学 | Circuit rewriting command system for FPGA mapping |
| CN102820879A (en) * | 2012-08-17 | 2012-12-12 | 中国电子科技集团公司第五十八研究所 | Radiation-proof triple-modular redundancy circuit structure |
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2018
- 2018-08-02 CN CN201810868564.5A patent/CN109086520A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020162086A1 (en) * | 2001-04-30 | 2002-10-31 | Morgan David A. | RTL annotation tool for layout induced netlist changes |
| US20030125925A1 (en) * | 2001-12-27 | 2003-07-03 | Walther John Stephen | Batch editor for netlists described in a hardware description language |
| CN101615211A (en) * | 2009-08-04 | 2009-12-30 | 复旦大学 | Commercial on-spot programmable device is used for the anti-irradiance method of triplication redundancy under the radiation environment |
| CN102033772A (en) * | 2010-12-28 | 2011-04-27 | 复旦大学 | Circuit rewriting command system for FPGA mapping |
| CN102820879A (en) * | 2012-08-17 | 2012-12-12 | 中国电子科技集团公司第五十八研究所 | Radiation-proof triple-modular redundancy circuit structure |
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