CN109086180B - Memory inspection test method - Google Patents
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- CN109086180B CN109086180B CN201810970180.4A CN201810970180A CN109086180B CN 109086180 B CN109086180 B CN 109086180B CN 201810970180 A CN201810970180 A CN 201810970180A CN 109086180 B CN109086180 B CN 109086180B
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- 238000010998 test method Methods 0.000 title claims abstract description 12
- 238000007689 inspection Methods 0.000 title claims abstract description 8
- 238000012360 testing method Methods 0.000 claims abstract description 147
- 238000000034 method Methods 0.000 claims abstract description 28
- 230000002457 bidirectional effect Effects 0.000 claims abstract description 16
- 230000006870 function Effects 0.000 claims abstract description 15
- 238000012937 correction Methods 0.000 claims abstract description 6
- 230000002950 deficient Effects 0.000 claims abstract description 5
- 238000013500 data storage Methods 0.000 claims description 3
- 230000000977 initiatory effect Effects 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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Abstract
The invention provides a memory inspection test method, which comprises the following steps: in the starting process of the server memory, starting an RMT function in BIOS to perform RTM test; and the RTM test ends and enters a Memtest stage, and a pause test and a bidirectional march test are carried out, wherein the bidirectional march test comprises a transverse march test on the basis of a longitudinal march test. In the step of starting the server memory, starting an RMT function in the BIOS to perform RTM test, wherein the RTM test comprises the following steps: and detecting the memory with errors, and shielding the errors in the memory by an independent error correction chip. If a permanent memory error is detected, the RMT identifies the defective memory and removes it from the operating system.
Description
Technical Field
The invention relates to the technical field of computer memory detection, in particular to a memory detection testing method.
Background
In recent years, the supply of the memory of the server is short, the price of the ship rises, and the price doubles within two years. However, in terms of quality, data is increasingly poor with the increase in capacity, process switching, and short supply and demand. Batch problems with memory are often exploded at the production line and customer locations, causing complaints and normal applications. In the production process, due to the fact that the detection method is not strict, fault memory or memory with poor physical appearance flows out of a production line, and the use of a client is affected.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a memory test method to solve the technical problems.
The technical scheme of the invention is as follows:
a memory inspection test method comprises the following steps:
in the starting process of the server memory, starting an RMT function in BIOS to perform RTM test;
and the RTM test ends and enters a Memtest stage, and a pause test and a bidirectional march test are carried out, wherein the bidirectional march test comprises a transverse march test on the basis of a longitudinal march test.
Further, in the step of starting the server memory, when the BIOS starts the RMT function to perform the RTM test, performing the RTM test includes:
and detecting the memory with errors, and shielding the errors in the memory by an independent error correction chip.
Further, in the step of starting the server memory, when the BIOS starts the RMT function to perform the RTM test, performing the RTM test further includes:
if a permanent memory error is detected, the RMT identifies the defective memory and removes it from the operating system.
Further, in the step of starting the server memory, when the BIOS starts the RMT function to perform the RTM test, performing the RTM test further includes:
and outputting a test log in the RTM test process, checking an error log of the RMT in the BIOS, and determining the memory slot position with the problem.
Further, the step rtmt test ends and enters a Memtest stage, and the pause test and the bidirectional march test are performed, where the pause test includes:
the memory Memtest phase is a test process pause of 7.8 mus.
Further, the step rtmt test ends and enters a Memtest stage, and in the pause test and the bidirectional march test, the transverse march test based on the longitudinal march test includes:
dividing a DRAM into a plurality of small blocks;
each time one block is tested, resetting the block to be tested;
bit by bit position 1, each position one bit, testing whether the bit is 1 or not, if so, continuing, or else reporting an error.
Further, the step rtmt of ending the rtmtest and entering the Memtest stage, performing a pause test and a bidirectional march test, and performing a transverse march test based on the longitudinal march test further includes:
after the test of all the set 1 is finished, clearing 0 bit by bit, and testing whether the clearing 0 bit is 0 or not every clearing one bit, if so, the correctness is realized, otherwise, an error is reported.
Further, the test is completed with backup test data.
Further, the step of testing the finished backup data includes:
building a plurality of clients of test data to be backed up, building a data storage server, and connecting the clients and the storage server to be tested to a switch to build a local area network;
collecting all test data under the OS;
processing the test data and initiating a request for backing up the file to a storage server; the method comprises the following steps of putting collected test data under a root directory, naming according to a data backup naming rule, packaging and compressing into a backup file, wherein the data backup naming rule is as follows:
naming according to the mode of time plus memory number;
and the storage server starts to calculate the local available storage space after receiving the request, and receives the transmitted backup file if the available space is larger than the size of the backup file.
Further, the step of testing the backup data after completing the test further comprises:
and the storage server starts to calculate the local available storage space after receiving the request, if the available storage space is smaller than the size of the test data backup file, the storage server searches the local oldest primary backup data according to the data backup naming rule, starts a clearing instruction, and calculates the local available storage space again until enough space is available for receiving the test data backup file transmitted by the client. Memory error correction Reliable Memory Technology (RMT).
According to the technical scheme, the invention has the following advantages: the invention provides a simple and tight test method for memory inspection, which can realize the increase of the memory detectable rate by adding pause test and test in the other direction of march on the basis of the original MEMTEST test project after the production line production process and the booting stage and the RMT test process. In the production stage of the server, the purpose of memory sorting is achieved, and the fault memory is intercepted into a factory.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Therefore, compared with the prior art, the invention has prominent substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.
Drawings
FIG. 1 is a flow chart of march testing in a memory test method;
FIG. 2 is a flow chart of a method for backing up test data.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings by way of specific examples, which are illustrative of the present invention and are not limited to the following embodiments.
Example one
As shown in fig. 1, a method for testing memory inspection includes the following steps:
s1: in the starting process of the server memory, starting an RMT function in BIOS to perform RTM test;
s2: and the RTM test ends and enters a Memtest stage, and a pause test and a bidirectional march test are carried out, wherein the bidirectional march test comprises a transverse march test on the basis of a longitudinal march test.
In the step S1, in the process of starting the server memory, when the BIOS starts the RMT function to perform the RTM test, performing the RTM test includes:
and detecting the memory with errors, and shielding the errors in the memory by an independent error correction chip.
In the step S1, in the starting process of the server memory, when the BIOS starts the RMT function to perform the RTM test, performing the RTM test further includes:
if a permanent memory error is detected, the RMT identifies the defective memory and removes it from the operating system.
In the step S1, in the starting process of the server memory, when the BIOS starts the RMT function to perform the RTM test, performing the RTM test further includes:
and outputting a test log in the RTM test process, checking an error log of the RMT in the BIOS, and determining the memory slot position with the problem.
In step S2, performing the pause test includes:
the memory Memtest phase is a test process pause of 7.8 mus. Trfc ("SDRAM row refresh cycle time", which is the number of clock cycles required for row cell refresh) is added, which also indicates that a refresh command is sent twice to another row cell in the same bank, JEDEC specification 7.8 μ s, adjusted to 15.6 μ s) to lengthen the capacitance time of the cell and screen out the cells with poor retention of capacitance.
In step S2, performing the transverse march test on the basis of the longitudinal march test includes:
s21: dividing a DRAM into a plurality of small blocks;
s22: each time one block is tested, resetting the block to be tested;
s23: bit by bit position 1, each position one bit, testing whether the bit is 1 or not, if so, continuing, or else reporting an error.
S24: after the test of all the set 1 is finished, clearing 0 bit by bit, and testing whether the clearing 0 bit is 0 or not every clearing one bit, if so, the correctness is realized, otherwise, an error is reported.
S3: and testing the finished backup data.
Example two
A memory inspection test method comprises the following steps:
s1: in the starting process of the server memory, starting an RMT function in BIOS to perform RTM test;
s2: and the RTM test ends and enters a Memtest stage, and a pause test and a bidirectional march test are carried out, wherein the bidirectional march test comprises a transverse march test on the basis of a longitudinal march test.
In the step S1, in the process of starting the server memory, when the BIOS starts the RMT function to perform the RTM test, performing the RTM test includes:
and detecting the memory with errors, and shielding the errors in the memory by an independent error correction chip.
In the step S1, in the starting process of the server memory, when the BIOS starts the RMT function to perform the RTM test, performing the RTM test further includes:
if a permanent memory error is detected, the RMT identifies the defective memory and removes it from the operating system.
In the step S1, in the starting process of the server memory, when the BIOS starts the RMT function to perform the RTM test, performing the RTM test further includes:
and outputting a test log in the RTM test process, checking an error log of the RMT in the BIOS, and determining the memory slot position with the problem.
In step S2, performing the pause test includes:
the memory Memtest phase is a test process pause of 7.8 mus. Trfc ("SDRAM row refresh cycle time", which is the number of clock cycles required for row cell refresh) is added, which also indicates that a refresh command is sent twice to another row cell in the same bank, JEDEC specification 7.8 μ s, adjusted to 15.6 μ s) to lengthen the capacitance time of the cell and screen out the cells with poor retention of capacitance.
In step S2, performing the transverse march test on the basis of the longitudinal march test includes:
s21: dividing a DRAM into a plurality of small blocks;
s22: each time one block is tested, resetting the block to be tested;
s23: bit by bit position 1, each position one bit, testing whether the bit is 1 or not, if so, continuing, or else reporting an error.
S24: after the test of all the set 1 is finished, clearing 0 bit by bit, and testing whether the clearing 0 bit is 0 or not every clearing one bit, if so, the correctness is realized, otherwise, an error is reported.
S3: and testing the finished backup data.
As shown in fig. 2, step S3 includes:
s31: building a plurality of clients of test data to be backed up, building a data storage server, and connecting the clients and the storage server to be tested to a switch to build a local area network;
s32: collecting all test data under the OS;
s33: processing the test data and initiating a request for backing up the file to a storage server; the method comprises the following steps of putting collected test data under a root directory, naming according to a data backup naming rule, packaging and compressing into a backup file, wherein the data backup naming rule is as follows:
naming according to the mode of time plus memory number;
s34: and the storage server starts to calculate the local available storage space after receiving the request, and receives the transmitted backup file if the available space is larger than the size of the backup file.
In this embodiment, the storage server starts to calculate the local available storage space after receiving the request, and if the available storage space is smaller than the size of the test data backup file, the storage server searches for the locally oldest primary backup data according to the data backup naming rule, starts a clear instruction, and calculates the local available storage space again until there is sufficient space to receive the test data backup file transmitted by the client.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (4)
1. A memory inspection test method is characterized by comprising the following steps:
in the starting process of the server memory, starting an RMT function in BIOS to perform RTM test; the method specifically comprises the following steps:
detecting the memory with errors, and shielding the errors in the memory through an independent error correction chip; if a permanent memory error is detected, the RMT will identify the defective memory and remove it from the operating system; outputting a test log in the RTM test process, checking an error log of RMT in a BIOS, and determining a memory slot position with a problem;
the RTM test is ended and enters a Memtest stage, and a pause test and a bidirectional march test are carried out, wherein the bidirectional march test comprises a transverse march test on the basis of a longitudinal march test;
backing up test data after the test is finished; the method specifically comprises the following steps: building a plurality of clients of test data to be backed up, building a data storage server, and connecting the clients and the storage server to be tested to a switch to build a local area network; collecting all test data under the OS; processing the test data and initiating a request for backing up the file to a storage server; the method comprises the following steps of putting collected test data under a root directory, naming according to a data backup naming rule, packaging and compressing into a backup file, wherein the data backup naming rule is as follows: naming according to the mode of time plus memory number; the storage server starts to calculate the local available storage space after receiving the request, and receives the transmitted backup file if the available space is larger than the size of the backup file; and the storage server starts to calculate the local available storage space after receiving the request, if the available storage space is smaller than the size of the test data backup file, the storage server searches the local oldest primary backup data according to the data backup naming rule, starts a clearing instruction, and calculates the local available storage space again until enough space is available for receiving the test data backup file transmitted by the client.
2. The memory test method according to claim 1, wherein the step RTM test ends and enters a Memtest stage, and the pause test and the bidirectional march test are performed, and the pause test includes:
the memory Memtest phase is a test process pause of 7.8 mus.
3. The memory test method of claim 2, wherein the step RTM test ends and enters a Memtest stage, and in performing a pause test and a bidirectional march test, performing a transverse march test based on a longitudinal march test comprises:
dividing a DRAM into a plurality of small blocks;
each time one block is tested, resetting the block to be tested;
bit by bit position 1, each position one bit, testing whether the bit is 1 or not, if so, continuing, or else reporting an error.
4. The memory test method according to claim 3, wherein the step of RTM ending the test and entering Memtest phase, performing a pause test and a bidirectional march test, and performing a transverse march test based on a longitudinal march test further comprises:
after the test of all the set 1 is finished, clearing 0 bit by bit, and testing whether the clearing 0 bit is 0 or not every clearing one bit, if so, the correctness is realized, otherwise, an error is reported.
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| US5815512A (en) * | 1994-05-26 | 1998-09-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory testing device |
| US6779141B1 (en) * | 2000-06-08 | 2004-08-17 | Sun Microsystems, Inc. | System and method for implementing memory testing in a SRAM unit |
| KR100928323B1 (en) * | 2002-05-27 | 2009-11-25 | 연세대학교 산학협력단 | Test method for dual port memory |
| CN1485623A (en) * | 2002-09-27 | 2004-03-31 | 记忆科技(深圳)有限公司 | Highly effective testing method for dynamic storage module |
| CN101034366A (en) * | 2006-03-07 | 2007-09-12 | 鸿富锦精密工业（深圳）有限公司 | Computer testing system and method |
| CN103198000A (en) * | 2013-04-02 | 2013-07-10 | 浪潮电子信息产业股份有限公司 | Method for positioning faulted memory in linux system |
| CN103412807A (en) * | 2013-08-12 | 2013-11-27 | 浪潮电子信息产业股份有限公司 | Memory inspection testing system |
| CN103984634B (en) * | 2014-06-05 | 2017-06-30 | 浪潮电子信息产业股份有限公司 | A kind of internal memory unsteady pressure method of testing of LINUX servers |
| US9805825B1 (en) * | 2015-08-24 | 2017-10-31 | Apple Inc. | Memory error capture logic |
| CN105468485A (en) * | 2015-11-19 | 2016-04-06 | 英业达科技有限公司 | Character-oriented memory test method |
| CN106226645B (en) * | 2016-07-15 | 2020-06-23 | 联想(北京)有限公司 | Connection detection device and method |
| CN106991026A (en) * | 2017-04-28 | 2017-07-28 | 郑州云海信息技术有限公司 | It is a kind of to pass through the method that network carries out server memory Rank margin test in batches |
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