CN109064980A - Liquid crystal display backlight multi partition control device - Google Patents
Liquid crystal display backlight multi partition control device Download PDFInfo
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- CN109064980A CN109064980A CN201811115221.8A CN201811115221A CN109064980A CN 109064980 A CN109064980 A CN 109064980A CN 201811115221 A CN201811115221 A CN 201811115221A CN 109064980 A CN109064980 A CN 109064980A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3406—Control of illumination source
- G09G3/342—Control of illumination source using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines
- G09G3/3426—Control of illumination source using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines the different display panel areas being distributed in two dimensions, e.g. matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention relates to liquid crystal display fields, the poor problem of picture Lag synchronization is connected in parallel for driving chip, a kind of liquid crystal display backlight multi partition control device is proposed, including power panel, LED light bar, driving chip group, the microprocessor for the brightness processed chip of sampled images subregion luminance information and for luminance information to be converted to subregion backlight signal；The luminance information input pin of the luminance information output pin connection microprocessor of brightness processed chip, the field sync signal foot of the field sync signal foot connection microprocessor of brightness processed chip, the clock signal foot of the clock signal foot connection microprocessor of brightness processed chip；Driving chip group and microprocessor correspond, the Backlit message of microprocessor output feeds back to the backlight signal feedback foot of microprocessor after transmitting step by step in driving chip group, be respectively serially connected with LED light bar between any one driving foot and the power supply foot of power panel of driving chip；The present invention is suitable for the backlight control of liquid crystal display.
Description
Technical field
The present invention relates to liquid crystal display field, in particular to a kind of liquid crystal display backlight multi partition control device.
Background technique
With the development of Mini LED technology, backlight multi partition light modulation subregion on liquid crystal display, flat panel TV can be with
From tens current subregions up to a hundred, thousands of even more subregions can be developed to.LED backlight subregion is more, and brightness of image is moved
State adjusts more accurate, to improve the effect of dynamic contrast, LED backlight can will significantly using a large amount of subregion dimming modes
Promote the image quality effect of flat panel TV, liquid crystal display.
LED backlight subregion dynamic adjustment technique is the important technology for promoting LED television image quality and showing, working principle at present
Be microprocessor according to the bright dark degree of picture material come the backlight illumination of dynamic regulation corresponding region, keep bright image brighter and
Dark image is darker, to improve the effect of dynamic contrast.It is existing for using multiple driving chips be connected in parallel after connect it is micro-
Processor, driving chip are respectively independently decoded to control the electric current of driving foot again after receiving the backlight signal that microprocessor issues
Data lack communication between each driving chip independently of each other, and microprocessor can not know whether that all driving chips are complete at this time
At above-mentioned treatment process, the time that microprocessor issues next backlight signal can not be adjusted according to the actual situation,
It is only capable of making relatively fixed delay, the poor synchronization for the data that can so cause decoding to issue has more apparent delay；If adopting
Microprocessor is respectively fed back to after having been handled with each driving chip, then the backlight signal of microprocessor can be made to feed back foot not
It is enough.The backlight subarea quantity that available liquid crystal screen and flat panel TV are able to achieve simultaneously is smaller, increases significantly the number of partitions of backlight
Image quality HDR display effect can be promoted, and to realize the high-precision drive control of the thousands of multi partitions of backlight, is shown to promote image quality
Effect theoretically requires the Division area of backlight smaller, and number of partitions is The more the better.
Summary of the invention
The technical problems to be solved by the present invention are: driving chip is overcome to be connected in parallel, picture Lag synchronization is poor to be asked
Topic, proposes a kind of liquid crystal display backlight multi partition control device.
The present invention solves above-mentioned technical problem, the technical solution adopted is that:
Liquid crystal display backlight multi partition control device, including power panel, LED light bar, driving chip group, for sampled images point
The brightness processed chip of area's luminance information and for by luminance information conversion subregion backlight signal microprocessor, brightness processed core
The luminance information output pin of piece connects the luminance information input pin of all microprocessors, the field sync signal foot of brightness processed chip
The field sync signal foot of all microprocessors is connected, the clock signal foot of brightness processed chip connects the clock of all microprocessors
Signal pins；Driving chip group and microprocessor correspond, and enabling driving chip number in driving chip group is n, and n >=2 are successively remembered
For the 1st driving chip to the n-th driving chip, the backlight signal output pin of the microprocessor connects in corresponding driving chip group the
The backlight signal input pin of 1 driving chip, the backlight signal output pin of the 1st driving chip connect the 2nd in corresponding driving chip group
The backlight signal input pin of driving chip, and so on, the backlight signal output pin of the (n-1)th driving chip connects in driving chip group
The backlight signal input pin of the n-th driving chip in corresponding driving chip group is connect, the output pin of the backlight signal of the n-th driving chip connects
Connect corresponding microprocessor backlight signal feedback foot, the field sync signal foot of all driving chips of driving chip group with it is corresponding
The field sync signal foot of microprocessor is connected, and the backlight signal decoding deadline of all driving chips is in a field sync signal
In period；LED light bar, LED light are respectively serially connected between any one driving foot and the power supply foot of power panel of driving chip
The anode connection power panel of item, the driving foot of the cathode connection driving chip of LED light bar.
Preferably, the MOSI foot of the microprocessor connects the MOSI foot of the 1st driving chip of corresponding driving chip group, the
The MISO foot of 1 driving chip connects the MOSI foot of the second driving chip in corresponding driving chip group, and so on, driving chip group
The MISO foot of interior (n-1)th driving chip connects the MOSI foot of the n-th driving chip in corresponding driving chip group, the n-th driving chip
MISO foot connects the MISO foot of corresponding microprocessor；The CLK foot of the microprocessor connects to be owned in corresponding driving chip group
The CLK foot of driving chip, the VSYNC foot of microprocessor connects the VSYNC foot of all driving chips in corresponding driving chip group, micro-
The EN foot of processor connects the EN foot of all driving chips in corresponding driving chip group, and the CSB foot connection of microprocessor is corresponding to drive
The CSB foot of all driving chips in dynamic chipset.
Preferably, the number of both driving chip group and microprocessor is p, and p >=2, driving chip group is successively denoted as
For 1st driving chip group to pth driving chip group, microprocessor is successively denoted as the 1st microprocessor to p-th of microprocessor, often
A driving chip group includes n driving chip, and the driving chip in pth driving chip group is successively denoted as pth1Driving chip is to
pnThe backlight signal output pin of driving chip, p-th of microprocessor connects pth1The backlight signal input pin of driving chip, pth1
The backlight signal output pin of driving chip connects pth2The backlight signal input pin of driving chip, and so on, pthn-1Drive core
The backlight signal output pin of piece connects pthnThe backlight signal input pin of driving chip, pthnThe backlight signal of driving chip it is defeated
The backlight signal that foot connects p-th microprocessor out feeds back foot, and so on each corresponding microprocessor of driving chip group
Connection.
It further, further include the first feed circuit, the first feed circuit includes the foot that reports an error of diode one, microprocessor
With the foot that reports an error of driving chip, report an error foot and the corresponding microprocessor of any one driving chip reports an error in driving chip group
Diode one, the cathode of the foot connection diode one that reports an error of driving chip, the anode of diode one are respectively serially connected between foot
Connect the foot that reports an error of microprocessor.
Further, further include the second feed circuit, the second feed circuit include diode two, power panel feedback foot and
The feedback foot of driving chip is respectively serially connected with two poles between the feedback foot of any one driving chip and the feedback foot of power panel
Pipe two, the cathode of the feedback foot connection diode two of driving chip, the feedback foot of the anode connection power panel of diode two.
Preferably, the driving foot of any one of driving chip is multiple.
The beneficial effects of the present invention are:
1) driving chip is attached by the way of daisy chain, and transmission mode of the backlight signal on each driving chip is
It transmits step by step, adjustment clock frequency makes the backlight signal of driving chip decode the deadline a field sync signal period
Interior, the backlight signal that so returning to microprocessor can feed back to according to driving chip starts the transmission of next backlight signal,
It so ensure that each driving chip decodes each backlight signal to complete and by the output of driving each backlight subarea of foot control system
The process of electric current is in synchronous coordination state, and driving chip is connected in parallel to the backlight delay control of the Millisecond of generation independently of each other
System improves the synchronism of picture, avoids the trailing phenomenon and splashette phenomenon of picture in delicate grade.
2) when the number of microprocessor be it is multiple, be denoted as p, corresponding driving chip group is also p, remembers any one driving chip
The number of driving foot be m, then corresponding backlight subarea number at most can reach p × p × m, and the number of backlight subarea obtains
The increase of geometry times, individually controls the brightness of each subregion, is greatly improved black and white field scene contrast and promotes image quality display effect
Fruit.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the embodiment of the present invention one；
Fig. 2 is the structural schematic diagram of the embodiment of the present invention two；
Wherein, SOC is brightness processed chip, and U1 is the 1st microprocessor, and Up is p-th of microprocessor, Q1_1~Q1_n
Driving chip in 1st driving chip group, Qp_1~Qp_n are the driving chip in pth driving chip group, and DY is power panel, D1
For diode one, D2 is diode two.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, right with reference to the accompanying drawings and embodiments
The present invention is further elaborated.
Liquid crystal display backlight multi partition control device, including power panel, LED light bar, driving chip group, for sampled images point
The brightness processed chip of area's luminance information and for by luminance information conversion subregion backlight signal microprocessor, brightness processed core
The luminance information output pin of piece connects the luminance information input pin of all microprocessors, the field sync signal foot of brightness processed chip
The field sync signal foot of all microprocessors is connected, the luminance information output pin of brightness processed chip connects all microprocessors
The field sync signal foot of luminance information input pin, brightness processed chip connects the field sync signal foot of all microprocessors, brightness
The clock signal foot of processing chip connects the clock signal foot of all microprocessors；Driving chip group and microprocessor one are a pair of
It answers, enabling driving chip number in driving chip group is n, and n >=2 are successively denoted as the 1st driving chip to the n-th driving chip, described micro-
The backlight signal output pin of processor connects the backlight signal input pin of the 1st driving chip in corresponding driving chip group, the 1st driving
The backlight signal output pin of chip connects the backlight signal input pin of the 2nd driving chip in corresponding driving chip group, and so on,
The backlight signal output pin of the (n-1)th driving chip connects the back of the n-th driving chip in corresponding driving chip group in driving chip group
Optical signal input pin, the backlight signal that the output pin of the backlight signal of the n-th driving chip connects corresponding microprocessor are fed back foot, are driven
The field sync signal foot of all driving chips of dynamic chipset is connected with the field sync signal foot of corresponding microprocessor, all drives
The backlight signal decoding deadline of dynamic chip is within a field sync signal period；Driving chip any one driving foot with
LED light bar, the anode connection power panel of LED light bar are respectively serially connected between the power supply foot of power panel, the cathode of LED light bar connects
Connect the driving foot of driving chip.
Above-mentioned microprocessor calculates and corresponding backlight signal is sent to driving chip driving core after the value of backlight signal
Piece is used to receive the electric current that backlight signal is decoded the then LED light bar by the driving respective backlight subarea of foot control system, power supply
Plate is for providing the voltage of LED light bar.Wherein, a LED light bar can have multiple LED and be composed in series, a driving foot connection
LED light bar can correspond to a backlight subarea, transmission mode of the backlight signal on driving chip is to transmit step by step, i.e. driving core
Piece is attached by the way of daisy chain, and adjustment clock frequency makes the processing deadline of driving chip synchronize week at one
In phase, the backlight signal that so returning to microprocessor can feed back to according to driving chip starts the hair of next backlight signal
It send, the transmission of so entire backlight signal is in synchronous regime.
The mode that SPI can be used in microprocessor is communicated with driving chip, the MOSI foot connection pair of the microprocessor
The MOSI foot of the 1st driving chip of driving chip group is answered, the MISO foot of the 1st driving chip connects second in corresponding driving chip group
The MOSI foot of driving chip, and so on, the MISO foot of the (n-1)th driving chip connects corresponding driving chip group in driving chip group
The MISO foot of the MOSI foot of interior n-th driving chip, the n-th driving chip connects the MISO foot of corresponding microprocessor；Micro- place
The CLK foot for managing device connects the CLK foot of all driving chips in corresponding driving chip group, and the VSYNC foot of microprocessor, which connects, to be corresponded to
The VSYNC foot of all driving chips in driving chip group, the EN foot of microprocessor connect all drivings in corresponding driving chip group
The EN foot of chip, the CSB foot of microprocessor connect the CSB foot of all driving chips in corresponding driving chip group.Wherein, micro process
The MOSI foot of device is that its backlight signal output pin is used to export original backlight signal, and the MISO foot of microprocessor is its backlight letter
Number feedback foot is used to receive the backlight signal of the n-th driving chip output, and the MOSI foot of driving chip is its backlight signal input pin
For receiving the backlight signal of upper level, the MISO foot of driving chip is its backlight signal output pin for exporting next stage backlight
Signal, CLK foot are clock signal foot, and VSYNC foot is field sync signal foot, and CSB foot is chip selection signal foot, and EN foot is enabled foot.
Which can guarantee the same VSYNC (field sync signal) in the period all driving chips can complete to have decoded backlight signal
At and by driving each backlight subarea of foot control system output electric current.
To guarantee the sufficiently large of backlight subarea quantity, the number of both driving chip group and microprocessor is p a, and p >=
2, driving chip group is successively denoted as the 1st driving chip group to pth driving chip group, and microprocessor is successively denoted as the 1st micro process
For device to p-th of microprocessor, driving chip group includes n driving chip, and the driving chip in pth driving chip group is successively denoted as
Pth1Driving chip is to pthnThe backlight signal output pin of driving chip, p-th of microprocessor connects pth1The backlight of driving chip
Signal input pin, pth1The backlight signal output pin of driving chip connects pth2The backlight signal input pin of driving chip, with such
It pushes away, pthn-1The backlight signal output pin of driving chip connects pthnThe backlight signal input pin of driving chip, pthnDriving chip
The output pin of backlight signal connect the backlight signal of p-th microprocessor and feed back foot, and so on each driving chip group with
Its connection for corresponding to microprocessor.Wherein, the number of the driving chip in each driving chip group can be the same or different.
The invention also includes the first feed circuit, the first feed circuit include diode one, microprocessor report an error foot and
The foot that reports an error of driving chip, the foot that reports an error of the report an error foot and corresponding microprocessor of any one interior driving chip of driving chip group
Between be respectively serially connected with diode one, the cathode of the foot connection diode one that reports an error of driving chip, the anode of diode one is even
Connect the foot that reports an error of microprocessor.
For detecting driving chip, whether operation irregularity drives first feed circuit when driving chip is working properly
The foot output high level that reports an error of chip, diode one end；When driving chip operation irregularity, the foot output that reports an error of driving chip
Low level, diode one are connected, and corresponding microprocessor prompts to report an error because its foot that reports an error is low level at this time.
The invention also includes the second feed circuit, the second feed circuit includes diode two, the feedback foot of power panel and drive
The feedback foot of dynamic chip, is respectively serially connected with diode between the feedback foot of any one driving chip and the feedback foot of power panel
Two, the cathode of the feedback foot connection diode two of driving chip, the feedback foot of the anode connection power panel of diode two.
Second feed circuit for detect corresponding LED light bar whether operation irregularity, when the corresponding LED light of driving chip
Item is working properly, and the feedback foot of driving chip exports high level, and diode two ends at this time；When LED light bar open circuit or short circuit,
The feedback foot of driving chip exports low level, and diode two is connected, and power panel triggers its protection because it feeds back due to foot is low level
Mechanism stops working, and LED light bars all at this time can also stop working.
To make each driving chip can drive multiple LED light bars, the driving foot of any one of driving chip is
It is multiple.
Embodiment one
As shown in Figure 1, liquid crystal display backlight multi partition control device in the present embodiment, including power panel DY, LED light bar, the 1st
Driving chip group Q1_1~Q1_n, for the brightness processed chip SOC of sampled images subregion luminance information and for believing brightness
1st microprocessor U1 of breath conversion subregion backlight signal, the luminance information output pin SYS_MISO of brightness processed chip SOC connect
Meet the luminance information input pin SYS_MISO of the 1st microprocessor U1, the field sync signal foot SYS_ of brightness processed chip SOC
VSYNC connects the field sync signal foot SYS_VSYNC of the 1st microprocessor U1, the clock signal foot of brightness processed chip SOC
SYS_CLK connects the clock signal foot of the 1st microprocessor U1；1st driving chip group Q1_1~Q1_n includes n driving core
Piece is successively denoted as the 1st1Driving chip Q1_1 to the 1stnThe backlight signal of Q1_n, n >=2,1st microprocessor U1 of driving chip is defeated
Foot MOSI connection the 1st out1The backlight signal input pin MOSI of driving chip Q1_1, the 1st1The backlight signal of driving chip Q1_1 is defeated
Out the 1st in the corresponding driving chip group of foot MISO connection2The backlight signal input pin MOSI of driving chip Q1_2, and so on, it drives
The 1st in dynamic chipsetn-1The backlight signal output pin of driving chip (omitting on figure) connects the 1st in corresponding driving chip groupnDriving
The backlight signal input pin MOSI of chip Q1_n, the 1stnThe output pin MISO connection correspondence of the backlight signal of driving chip Q1_n is micro-
The backlight signal of processor U1 feeds back foot MISO, the field sync signal foot VSYNC of all driving chips of driving chip group with
The connected VSYNC of the field sync signal foot of corresponding microprocessor U1, the backlight signal decoding deadline of all driving chips is one
In a field sync signal period；The driving foot for enabling driving chip is m, m >=2, is expressed as OUT1~OUTm in figure, will be any one
The driving foot of a driving chip is denoted as OUT, then each between the power supply foot VLED+ of any one driving foot OUT and power panel DY
From LED light bar, the anode connection power panel DY of LED light bar is serially connected with, the cathode of LED light bar connects the driving foot of driving chip
OUT.The model of driving chip Q1~Qn can be to select iW7038, and the model of microprocessor is chosen as EFM32HG222.
The present embodiment further includes the first feed circuit, and the first feed circuit includes one D1 of diode, first microprocessor U1
Report an error foot FAULTB and driving chip the foot FAULTB that reports an error, any one driving in the 1st driving chip group Q1_1~Q1_n
Reporting an error for chip is respectively serially connected with one D1 of diode between foot FAULTB and the foot that reports an error of first microprocessor U1, drive core
The cathode of one D1 of foot FAULTB connection diode that reports an error of piece, the anode connection first microprocessor U1's of one D1 of diode reports an error
Foot FAULTB.
The present embodiment further includes the second feed circuit, and the second feed circuit includes the feedback of two D2 of diode, power panel DY
Between the feedback foot FB of foot FB and driving chip, the feedback foot FB of the feedback foot FB and power panel DY of any one driving chip
Respectively it is serially connected with two D2 of diode, the cathode of feedback two D2 of foot FB connection diode of driving chip, the anode of two D2 of diode
Connect the feedback foot FB of power panel DY.
When all devices are all working properly, brightness processed chip SOC is carried out every auspicious image information by number of partitions bright
Digitization is spent, samples the corresponding luminance information in each area, and first microprocessor is issued into the packing of all subregion luminance informations
Processing；First microprocessor U1 is decoded processing to the brightness processed chip SOC luminance information sent and is converted to accordingly
Backlight signal be sent to the 1st1Driving chip Q1_1, the 1st1Driving chip Q1_1 is sent out after obtaining the backlight signal for corresponding to oneself
The entire backlight signal received is sent to be sent to the 1st2Driving chip Q1_2, while the 1st1Driving chip Q1_1 will correspond to the back of oneself
Optical signal, which is decoded, is converted to the size of current that current value controls each driving foot；And so on, the 1stnDriving chip Q1_n
It obtains and sends the entire backlight signal received after oneself corresponding backlight signal and be sent to first microprocessor U1, first
Microprocessor U1 knows that the backlight signal of a frame is disposed, and starts the transmission of the backlight signal of next frame.
When all driving chips in the first driving chip group are working properly, the foot FAULTB output that reports an error of driving chip
High level, at this point, all one D1 of diode end；When any driving chip operation irregularity, the foot that reports an error of driving chip
FAULTB exports low level, corresponding one D1 of diode conducting, and corresponding microprocessor U1 is because of its foot FAULTB that reports an error at this time
Low level and prompt to report an error.
When the corresponding LED light bar of all driving chips in the first driving chip group is working properly, the feedback of driving chip
Foot FB exports high level, at this point, two D2 of all diodes ends；When any LED light bar open circuit or short circuit when, driving chip it is anti-
Feed pin FB exports low level, corresponding two D2 of diode conducting, and power panel DY triggers its guarantor because it feeds back due to foot FB is low level
Protection mechanism stops working, and LED light bars all at this time can also stop working.
Embodiment two
As shown in Fig. 2, using multiple driving chip groups and multi-microprocessor on the basis of example 1, wherein
The backlight signal of all driving chips decodes the deadline within a field sync signal period, each driving chip group Qp_1-
The connection type of Qp_n corresponding microprocessor Up is consistent with the connection type of embodiment one, corresponding first feed circuit
Connection type be also consistent, all microprocessor U1- of luminance information output pin SYS_MISO connection of brightness processed chip SOC
All micro- places of field sync signal foot SYS_VSYNC connection of the luminance information input pin SYS_MISO of Up, brightness processed chip SOC
The field sync signal foot SYS_VSYNC of device U1-Up is managed, the clock signal foot SYS_CLK connection of brightness processed chip SOC is all micro-
The clock signal foot of processor U1-Up.
The present embodiment further includes the second feed circuit, and the second feed circuit includes the feedback of two D2 of diode, power panel DY
Between the feedback foot FB of foot FB and driving chip, the feedback foot FB of the feedback foot FB and power panel DY of any one driving chip
Respectively it is serially connected with two D2 of diode, the cathode of feedback two D2 of foot FB connection diode of driving chip, the anode of two D2 of diode
Connect the feedback foot FB of power panel DY.That is the feedback foot FB of power panel DY is public for each driving chip group
's.
When all devices are all working properly, brightness processed chip SOC is carried out every auspicious image information by number of partitions bright
Digitization is spent, samples the corresponding luminance information in each area, and all microprocessor U1- are issued into the packing of all subregion luminance informations
Up processing；1st microprocessor U1 is decoded processing to the brightness processed chip SOC luminance information sent and is converted to accordingly
Backlight signal be sent to the 1st of the 1st driving chip group1Driving chip Q1_1, the 1st1Driving chip Q1_1, which is obtained, corresponds to oneself
Backlight signal after send the entire backlight signal received and be sent to the 1st2Driving chip Q1_2, while the 1st1Driving chip Q1_1
The backlight signal for corresponding to oneself is decoded and is converted to the size of current that current value controls each driving foot；And so on, the
1nDriving chip Q1_n, which is obtained, to be sent the entire backlight signal received after oneself corresponding backlight signal and is sent to the 1st micro- place
Device U1 is managed, the 1st microprocessor U1 knows that the backlight signal of a frame is disposed, start the transmission of the backlight signal of next frame.
The similarly signal flow process of available p-th of microprocessor and pth driving chip group.
When all driving chips in driving chip group are working properly, the high electricity of foot FAULTB output that reports an error of driving chip
It is flat, at this point, all one D1 of diode end；When any driving chip operation irregularity of any driving chip group, core is driven
The foot FAULTB output low level that reports an error of piece, corresponding one D1 of diode are connected, at this time micro- place corresponding with driving chip group
Reason device prompts to report an error because its foot FAULTB that reports an error is low level.
When the corresponding LED light bar of all driving chips is working properly, the feedback foot FB of driving chip exports high level, this
When, all two D2 of diode cut-offs；When any LED light bar open circuit or short circuit, the feedback foot FB of driving chip exports low level,
Corresponding two D2 of diode conducting, power panel DY stop working because it feeds back foot FB to trigger its protection mechanism due to low level, this
The LED light bar of Shi Suoyou can also stop working.
Claims (6)
1. liquid crystal display backlight multi partition control device, including power panel, LED light bar, driving chip group, it is used for sampled images subregion
The brightness processed chip of luminance information and for by luminance information conversion subregion backlight signal microprocessor, which is characterized in that
The luminance information output pin of brightness processed chip connects the luminance information input pin of all microprocessors, the field of brightness processed chip
Synchronization signal foot connects the field sync signal foot of all microprocessors, and the clock signal foot of brightness processed chip connects all micro- places
Manage the clock signal foot of device；Driving chip group and microprocessor correspond, and enabling driving chip number in driving chip group is n, n
>=2, successively it is denoted as the 1st driving chip to the n-th driving chip, the corresponding driving of backlight signal output pin connection of the microprocessor
The backlight signal input pin of 1st driving chip in chipset, the corresponding driving core of backlight signal output pin connection of the 1st driving chip
The backlight signal input pin of 2nd driving chip in piece group, and so on, the backlight letter of the (n-1)th driving chip in driving chip group
Number output pin connects the backlight signal input pin of the n-th driving chip in corresponding driving chip group, the backlight signal of the n-th driving chip
Output pin connect the backlight signal of corresponding microprocessor and feed back foot, the field sync signal of all driving chips of driving chip group
Foot is connected with the field sync signal foot of corresponding microprocessor, and the backlight signal decoding deadline of all driving chips is at one
In the field sync signal period；LED is respectively serially connected between any one driving foot and the power supply foot of power panel of driving chip
Lamp bar, the anode connection power panel of LED light bar, the driving foot of the cathode connection driving chip of LED light bar.
2. liquid crystal display backlight multi partition control device as described in claim 1, which is characterized in that the MOSI of the microprocessor
Foot connects the MOSI foot of the 1st driving chip of corresponding driving chip group, and the MISO foot of the 1st driving chip connects corresponding driving chip
The MOSI foot of second driving chip in group, and so on, the MISO foot connection of the (n-1)th driving chip is corresponding in driving chip group drives
The MOSI foot of the n-th driving chip, the MISO foot of the n-th driving chip connect the MISO foot of corresponding microprocessor in dynamic chipset；
The CLK foot of the microprocessor connects the CLK foot of all driving chips in corresponding driving chip group, the VSYNC foot of microprocessor
The VSYNC foot of all driving chips in corresponding driving chip group is connected, the EN foot of microprocessor connects in corresponding driving chip group
The EN foot of all driving chips, the CSB foot of microprocessor connect the CSB foot of all driving chips in corresponding driving chip group.
3. liquid crystal display backlight multi partition control device as described in claim 1, which is characterized in that driving chip group and micro process
The number of both devices is p, and p >=2, driving chip group is successively denoted as the 1st driving chip group to pth driving chip group, micro- place
Reason device is successively denoted as the 1st microprocessor to p-th of microprocessor, and each driving chip group includes n driving chip, and pth is driven
Driving chip in dynamic chipset is successively denoted as pth1Driving chip is to pthnDriving chip, the backlight signal of p-th of microprocessor
Output pin connects pth1The backlight signal input pin of driving chip, pth1The backlight signal output pin of driving chip connects pth2It drives
The backlight signal input pin of dynamic chip, and so on, pthn-1The backlight signal output pin of driving chip connects pthnDriving chip
Backlight signal input pin, pthnThe backlight signal that the output pin of the backlight signal of driving chip connects p-th of microprocessor is anti-
Feed pin, and so on each corresponding microprocessor of driving chip group connection.
4. the liquid crystal display backlight multi partition control device as described in claims 1 or 2 or 3, which is characterized in that further include first anti-
Current feed circuit, the first feed circuit include diode one, microprocessor report an error foot and driving chip the foot that reports an error, driving chip group
Reporting an error for any one interior driving chip is respectively serially connected with diode one between foot and the foot that reports an error of corresponding microprocessor, drive
The cathode of the foot connection diode one that reports an error of dynamic chip, the foot that reports an error of the anode connection microprocessor of diode one.
5. liquid crystal display backlight multi partition control device as claimed in claim 4, which is characterized in that further include the second feedback electricity
Road, the second feed circuit include the feedback foot for feeding back foot and driving chip of diode two, power panel, any one driving chip
Feedback foot and power panel feedback foot between be respectively serially connected with diode two, the feedback foot of driving chip connects diode two
Cathode, diode two anode connection power panel feedback foot.
6. liquid crystal display backlight multi partition control device as described in claim 1, which is characterized in that any one of driving core
The driving foot of piece is multiple.
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| CN201811115221.8A CN109064980A (en) | 2018-09-25 | 2018-09-25 | Liquid crystal display backlight multi partition control device |
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Application publication date: 20181221 |