CN109039946B - Token adding method and device, storage medium and information processing device - Google Patents

Token adding method and device, storage medium and information processing device Download PDF

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CN109039946B
CN109039946B CN201710430698.4A CN201710430698A CN109039946B CN 109039946 B CN109039946 B CN 109039946B CN 201710430698 A CN201710430698 A CN 201710430698A CN 109039946 B CN109039946 B CN 109039946B
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ram
clock
state information
sub
ferrule
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CN109039946A (en
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李亚婷
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/10Flow control; Congestion control
    • H04L47/215Flow control; Congestion control using token-bucket
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/10Flow control; Congestion control
    • H04L47/20Traffic policing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/10Flow control; Congestion control
    • H04L47/28Flow control; Congestion control in relation to timing considerations

Abstract

The invention discloses a token adding method, which comprises the steps of presetting a first Random Access Memory (RAM) and a second RAM, and when one RAM in the two RAMs is subjected to first operation, performing second operation on the other RAM; performing first operation on the first RAM or the second RAM according to a first preset rule; when the data packet arrives, performing second operation on the first RAM and/or the second RAM according to a second preset rule, and adding tokens into the token bucket according to a third preset rule according to a second operation result; the first operation is to update clock ferrule state information in RAM, and the second operation is to read clock ferrule state information in RAM. The invention also discloses a token adding device, a storage medium and an information processing device.

Description

Token adding method and device, storage medium and information processing device
Technical Field
The present invention relates to the field of data communications, and in particular, to a token adding method and apparatus, a storage medium, and an information processing apparatus.
Background
The token bucket algorithm is the most common algorithm in network traffic supervision, and the principle of the token bucket algorithm is as follows: adding certain tokens into the token bucket at intervals according to a certain speed, taking the tokens from the token bucket when a data packet arrives, comparing the number of the tokens with the length of the message according to a certain rule to mark the color of the message, and carrying out flow supervision according to the color of the message. In the flow supervision process, multiple service flows are often supervised at the same time, so that each service flow needs to be sequentially operated when a token is added; in the case that the service flow entry is particularly large, the time required for one token adding action cycle is relatively long, and then, for the same service flow, the interval for adding tokens is increased, which means that the granularity of tokens added each time is increased, and the supervision error is increased.
Currently, token addition is performed in a mode of packet triggering token addition in the industry, namely, a token is added when a data packet arrives each time, and then token consumption and message coloring are performed according to the message length; the method needs to record the time difference between the last data packet and the current data packet, and then multiplies the time difference by the token accumulation rate to obtain the number of tokens to be added; in the actual implementation process, because the bit width of the clock counter is limited, when the time difference is calculated, whether the clock counter has a loop needs to be considered, according to the loop times, the last time and the current data packet arrival time are matched to obtain the data packet arrival time interval, and then token addition and flow supervision are performed; the method can improve the accuracy of flow supervision and reduce huge storage bandwidth consumed by periodically adding tokens.
In the above method of adding tokens by packet triggering, there are two update operation sources for a Random Access Memory (RAM) that records the number of times of a boot:
1. when the current global clock crosses zero, the zero crossing is automatically turned and refreshed, so that the original loop times are read from the RAM, and then 1 is added and written back;
2. when a data packet comes, the token bucket algorithm reads out the ferrule times of the service flow corresponding to the data packet from the RAM, and writes back 0 after the supervision is completed, so that the ferrule times are recorded from 0 again from the current data packet.
It can be seen that the existing method for recording the number of times of ferrule has two types of problems:
first, if a read port and a write port (1w1r) RAM are used, the above two ferrule counting operations do not have enough time slots to complete; for example: for a supervision system with 16K service flows, reading and adding 1 to write back the loop number in the RAM in sequence from the time when the clock is 0, and assuming that two cycles are needed, one cycle occupies a reading port and the other occupies a writing port, so that 32K cycles are needed for completing all automatic zero-crossing refreshing; during the period, if data packets arrive continuously in each period, the prior method has no enough time slot for reading and writing the ferrule count;
secondly, in order to overcome the first problem, a RAM with two reading ports and two writing ports (2w2r) can be adopted, so that the time slot requirement of clock loop counting can be met; however, in the actual implementation process, no existing RAM of 2w2r exists, and the function is generally implemented by using 10 blocks of RAM of 1w1r, which is very resource-consuming; such as: to implement a 32Kx2 clock loop RAM, a total of 6 blocks of 32Kx1 and 4 blocks of 32Kx2 of 1w1r RAM are required to implement.
Therefore, how to guarantee that the traffic supervision can support the continuous data packet coming scene in each period, and avoid consuming a large amount of resources, and guarantee the high precision and the practicability of the token bucket algorithm is a problem to be solved urgently.
Disclosure of Invention
In view of this, embodiments of the present invention are expected to provide a token adding method and apparatus, a storage medium, and an information processing apparatus, which can ensure that traffic supervision can support a scenario in which data packets are continuously sent in each cycle, avoid consuming a large amount of resources, and ensure high accuracy and practicability of a token bucket algorithm.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the embodiment of the invention provides a token adding method, which comprises the steps of presetting a first RAM (random access memory) and a second RAM, and when first operation is carried out on one RAM in the two RAMs, carrying out second operation on the other RAM; the method further comprises the following steps:
performing first operation on the first RAM or the second RAM according to a first preset rule;
when the data packet arrives, performing second operation on the first RAM and/or the second RAM according to a second preset rule, and adding tokens into the token bucket according to a third preset rule according to a second operation result;
the first operation is to update clock ferrule state information in RAM, and the second operation is to read clock ferrule state information in RAM.
Preferably, the method further comprises: dividing a clock cycle into four sub-cycles with equal duration, namely a first sub-cycle, a second sub-cycle, a third sub-cycle and a fourth sub-cycle, and performing a first operation when each sub-cycle is finished;
the duration of each sub-period is greater than the full duration of the token bucket;
the clock ferrule state information includes: initial state, half overflow and full overflow.
Preferably, the performing the first operation on the first RAM or the second RAM according to the first preset rule includes:
when the first sub-period and the second sub-period are finished, performing first operation on the first RAM;
and performing the first operation on the second RAM at the end of the third sub-period and the fourth sub-period.
Preferably, the performing the first operation on the first RAM at the end of the first sub-period includes: if the clock ferrule state information in the first RAM is in an initial state, setting the clock ferrule state information to be half-overflow; if the clock ferrule state information in the first RAM is full overflow, keeping the current clock ferrule state information in the first RAM;
and when the second sub-period is finished, performing a first operation on the first RAM, wherein the first operation comprises: if the clock ferrule state information in the first RAM is half-overflow, setting the clock ferrule state information to be full-overflow, otherwise, keeping the clock ferrule state information in the first RAM;
at the end of the third sub-period, performing a first operation on the second RAM, including: if the clock ferrule state information in the second RAM is in the initial state, setting the clock ferrule state information to be half-overflow; if the clock ferrule state information in the second RAM is full overflow, keeping the current clock ferrule state information in the second RAM;
at the end of the fourth sub-period, performing a first operation on the second RAM, including: and if the clock ferrule state information in the second RAM is half-overflow, setting the clock ferrule state information to be full-overflow, and otherwise, keeping the current clock ferrule state information in the second RAM.
Preferably, the performing the second operation on the first RAM and/or the second RAM according to the second preset rule includes:
when the arrival time point of the data packet is in each sub-period, performing second operation on the first RAM and the second RAM; when the clock ferrule state information read by the second operation in the first RAM and the second RAM is full overflow, determining a second operation result as full overflow;
when the arrival time point of the data packet is in the first operation process after the first sub-period is finished or the first operation process after the second sub-period is finished, performing second operation on the second RAM; determining the clock ferrule state information in the second RAM read by the second operation as a second operation result;
when the arrival time point of the data packet is in a third operation process after the third sub-period is finished or a first operation process after the fourth sub-period is finished, performing a second operation on the first RAM; and determining the clock ferrule state information read by the second operation in the first RAM as a second operation result.
Preferably, the adding tokens to the token bucket according to a third preset rule according to the second operation result includes:
if the second operation result is full overflow, filling the token bucket; otherwise, determining the time difference between the current data packet and the last data packet, and determining the product of the determined time difference and the preset token adding speed as the number of tokens added to the token bucket.
Preferably, the method further comprises:
if the first RAM or the second RAM is subjected to second operation, after the second operation result is obtained, setting the state information of the clock ferrule in the first RAM or the second RAM subjected to the second operation to be in an initial state;
and if the first RAM and the second RAM are subjected to second operation, setting the state information of the clock ferrules in the first RAM and the second RAM subjected to the second operation to be in an initial state after the second operation result is obtained.
The embodiment of the invention also provides a token adding device, which comprises: the device comprises a setting module, a first operation module and a second operation module; wherein:
the setting module: the method comprises the steps that two RAMs, namely a first RAM and a second RAM are preset, and when one RAM in the two RAMs is subjected to first operation, the other RAM is subjected to second operation;
the first operation module is used for performing first operation on the first RAM or the second RAM according to a first preset rule;
the second operation module is used for performing second operation on the first RAM and/or the second RAM according to a second preset rule when a data packet arrives, and adding tokens into the token bucket according to a third preset rule according to a second operation result;
the first operation is to update clock ferrule state information in RAM, and the second operation is to read clock ferrule state information in RAM.
Preferably, the setting module is further configured to:
dividing a clock cycle into four sub-cycles with equal duration, namely a first sub-cycle, a second sub-cycle, a third sub-cycle and a fourth sub-cycle, and performing a first operation when each sub-cycle is finished;
the duration of each sub-period is greater than the full duration of the token bucket;
the clock ferrule state information includes: initial state, half overflow and full overflow.
Preferably, the first operating module is specifically configured to:
when the first sub-period and the second sub-period are finished, performing first operation on the first RAM;
and performing the first operation on the second RAM at the end of the third sub-period and the fourth sub-period.
Preferably, the first operating module is specifically configured to:
when the first sub-period is finished, if the clock ferrule state information in the first RAM is in an initial state, setting the clock ferrule state information to be half-overflow; if the clock ferrule state information in the first RAM is full overflow, keeping the current clock ferrule state information in the first RAM;
when the second sub-period is over, if the state information of the clock ferrule in the first RAM is half-overflow, setting the state information of the clock ferrule to be full-overflow, otherwise, keeping the state information of the clock ferrule in the first RAM;
when the third sub-period is finished, if the clock ferrule state information in the second RAM is in an initial state, setting the clock ferrule state information to be half-overflow; if the clock ferrule state information in the second RAM is full overflow, keeping the current clock ferrule state information in the second RAM;
and when the fourth sub-period is finished, if the clock ferrule state information in the second RAM is half-overflow, setting the clock ferrule state information to be full-overflow, and otherwise, keeping the current clock ferrule state information in the second RAM.
Preferably, the second operation module is specifically configured to:
when the arrival time point of the data packet is in each sub-period, performing second operation on the first RAM and the second RAM, and when the clock ferrule state information read by the second operation in the first RAM and the second RAM is full overflow, determining a second operation result as full overflow;
when the arrival time point of the data packet is in the first operation process after the first sub-period is finished or the first operation process after the second sub-period is finished, performing second operation on the second RAM; determining the clock ferrule state information in the second RAM read by the second operation as a second operation result;
when the arrival time point of the data packet is in a third operation process after the third sub-period is finished or a first operation process after the fourth sub-period is finished, performing a second operation on the first RAM; and determining the clock ferrule state information read by the second operation in the first RAM as a second operation result.
Preferably, the second operation module is specifically configured to:
if the second operation result is full overflow, filling the token bucket; otherwise, determining the time difference between the current data packet and the last data packet, and determining the product of the determined time difference and the preset token adding speed as the number of tokens added to the token bucket.
Preferably, the second operation module is further configured to:
if the first RAM or the second RAM is subjected to second operation, after the second operation result is obtained, setting the state information of the clock ferrule in the first RAM or the second RAM subjected to the second operation to be in an initial state;
and if the first RAM and the second RAM are subjected to second operation, setting the state information of the clock ferrules in the first RAM and the second RAM subjected to the second operation to be in an initial state after the second operation result is obtained.
An embodiment of the present invention further provides a storage medium, on which an executable program is stored, where the executable program is executed by a processor, and implements any of the above steps of operating a RAM.
The embodiment of the invention also provides an information processing device, which comprises a memory, a processor and an executable program which is stored on the memory and can be run by the processor, wherein the device also comprises two RAMs used for storing the state information of the clock ferrule; the processor, when executing the executable program, performs any of the steps described above for operating on the RAM.
The token adding method and the token adding device provided by the embodiment of the invention are characterized in that two RAMs, namely a first RAM and a second RAM, are preset, and when one RAM in the two RAMs is subjected to first operation, the other RAM is subjected to second operation; performing first operation on the first RAM or the second RAM according to a first preset rule; when the data packet arrives, performing second operation on the first RAM and/or the second RAM according to a second preset rule, and adding tokens into the token bucket according to a third preset rule according to a second operation result; the first operation is to update clock ferrule state information in RAM, and the second operation is to read clock ferrule state information in RAM. Therefore, the two RAMs update the state information of the clock ferrule at intervals, when one RAM updates the state information of the clock ferrule, the other RAM provides the state information of the clock ferrule needed by the addition of the token, and thus, the two RAMs can alternately complete the updating and providing operation of the state information of the clock ferrule so as to ensure that the state information of the clock ferrule needed by the addition of the token can be provided in each reading and writing period of the state information of the clock ferrule and support the scene that each period continuously comes in data packets; in addition, the embodiment of the invention only adopts two RAMs, can avoid consuming a large amount of resources and can ensure the high precision and the practicability of the token bucket algorithm.
Drawings
FIG. 1 is a flow chart of a token adding method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the overall flow of network traffic supervision according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating the monitoring of network traffic during a period according to an embodiment of the present invention;
fig. 4 is a schematic flow chart of network traffic supervision in a 1 st 1/4 jump scenario according to an embodiment of the present invention;
fig. 5 is a schematic flow chart of network traffic supervision in a 2 nd 1/4 jump scenario according to an embodiment of the present invention;
fig. 6 is a schematic flow chart of network traffic supervision in a 3 rd 1/4 hopping scenario according to an embodiment of the present invention;
fig. 7 is a schematic flow chart of network traffic supervision in a 4 th 1/4 jump scenario according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a token adding apparatus according to an embodiment of the present invention.
Detailed Description
In the embodiment of the invention, two RAMs, namely a first RAM and a second RAM are preset, and when a first operation is carried out on one RAM in the two RAMs, a second operation is carried out on the other RAM; performing first operation on the first RAM or the second RAM according to a first preset rule; when the data packet arrives, performing second operation on the first RAM and/or the second RAM according to a second preset rule, and adding tokens into the token bucket according to a third preset rule according to a second operation result; the first operation is to update clock ferrule state information in RAM, and the second operation is to read clock ferrule state information in RAM.
The present invention will be described in further detail with reference to examples.
As shown in fig. 1, the token adding method provided in the embodiment of the present invention includes:
step 101: presetting two RAMs, namely a first RAM and a second RAM, and performing second operation on one RAM in the two RAMs when performing first operation on the other RAM;
here, the first operation is updating clock loop state information in the RAM, and the second operation is reading the clock loop state information in the RAM for calculating the number of tokens added to the token bucket; setting of the RAM can be carried out in the network flow monitoring device; wherein the clock ferrule state information may include: initial state, half overflow and full overflow, the three clock ferrule state information can be represented in RAM by 00, 01 and 10 respectively, and can also be represented by other self-defined modes; the initial state, the half overflow and the full overflow can be used for recording the mark of the clock timer crossing the sub-period so as to be used as the basis for continuously adding the token;
two RAMs, namely a first RAM and a second RAM, can be arranged in the network flow monitoring device for recording the ferrule condition, and two RAMs of 1w1r can be respectively used as the first RAM and the second RAM; here, the first and second electrodes; the first RAM and the second RAM may be configured to: one of the RAMs is occupied with clock loop state information updates, and the other RAM provides the clock loop state information needed for current token additions.
Further, the clock period may be divided into 4 equal sub-periods of the first sub-period, the second sub-period, the third sub-period, and the fourth sub-period in the network traffic policing device; the clock cycle can be a clock cycle used for recording the arrival time of two successive data packets, and a clock counter can realize the clock cycle counting function; the clock period can be divided into more than 1 sub-period, and similar to recording clock ferrule state information when a clock counter appears in a ferrule in the prior art, the clock ferrule state information can be recorded in the RAM when one sub-period is finished; the first sub-period, the second sub-period, the third sub-period and the fourth sub-period may be 4 periods sequentially arranged in one clock period; the duration of each sub-period is greater than the full duration of the token bucket; the token bucket full time length refers to a time length from adding tokens to an empty token bucket at a predetermined token adding rate until the token bucket is full.
Step 102: performing first operation on the first RAM or the second RAM according to a first preset rule;
here, the first preset rule is a rule for updating the state information of the clock loop to the RAM, and may be determined according to the number of sub-cycles in the one clock cycle and a relationship between the sub-cycles and the token bucket full-time.
Further, the clock cycle may be divided into 4 sub-cycles with equal cycles, and the duration of each sub-cycle is greater than the token bucket full duration; in this case, the first preset rule may be: when the first sub-period and the second sub-period are finished, performing first operation on the first RAM; when the third sub-period and the fourth sub-period are finished, performing first operation on the second RAM;
specifically, the clock period is usually counted by a clock period clock counter, and the high 2 bits of the clock counter can reflect the condition of 4 sub-periods, for example, when the high 2 bits 00 jump to 01, the first sub-period ends, when the high 2 bits 01 jump to 10, the second sub-period ends, when the high 2 bits 10 jump to 11, the third sub-period ends, and when the high 2 bits 11 jump to 00, the fourth sub-period ends; here, the zero-crossing self-refresh scenario may be determined in a scenario where the high 2 bits 00 of the clock counter jump to 01, 01 jumps to 10, 10 jumps to 11, and 11 jumps to 00; performing first operation on a first RAM and a second RAM in a zero-crossing self-refreshing scene; meanwhile, 00 hops 01 are determined as the 1 st 1/4 hopping scene, 01 hops 10 are determined as the 2 nd 1/4 hopping scene, 10 hops 11 are determined as the 3 rd 1/4 hopping scene, and 11 hops 00 are determined as the 4 th 1/4 hopping scene; in the 4 jumping scenes, updating the state information of the clock loop for each service flow; the number of service flows determines the time length for completing the updating of the state information of all clock ferrules, namely the time length of a hopping scene, for example, according to the prior art, 32K read-write cycles are required for updating the state information of the clock ferrules of 16K service flows.
At the end of the first sub-period, i.e. in the 1 st 1/4 jump scenario, performing a first operation on the first RAM, including: if the clock ferrule state information in the first RAM is in an initial state, setting the clock ferrule state information to be half-overflow; if the clock ferrule state information in the first RAM is full overflow, keeping the current clock ferrule state information in the first RAM; here, a half-overflow condition may indicate that the clock counter has experienced an 1/4 transition scenario, but cannot determine whether the clock counter has walked longer than 1 sub-cycle; the full overflow state represents that the clock counter has undergone 1/4 hopping scenes at least twice, and the two hopping scenes can ensure that the time length of the clock counter is greater than or equal to the sub-period, and the time length of the sub-period is greater than the time length of the full token bucket; therefore, the initial state, the half overflow state and the full overflow state can be used as the basis for continuously adding tokens;
specifically, when the current clock count has the 1 st 1/4 jump scene, the first RAM performs zero-crossing updating; here, 00, 01, and 10 are used in RAM to indicate clock-loop status information, respectively: initial state, half-spill and full-spill said three clock ferrule state information; in the 1 st 1/4 jump scenario, only 00 and 10 states exist for the first RAM, since the last first RAM update process has only two possibilities: the arrival of the data packet is updated to 00, or 10/00 keeps under the 2 nd 1/4 jump scene, or 01 jump is changed to 10; thus, at this time, the refresh of the first RAM is: if the clock ferrule state information in the first RAM is 00, rewriting to 01, otherwise, keeping 10;
and when the second sub-period is finished, performing a first operation on the first RAM, wherein the first operation comprises: if the clock ferrule state information in the first RAM is half-overflow, setting the clock ferrule state information to be full-overflow, otherwise, keeping the clock ferrule state information in the first RAM;
specifically, when the current clock count has the 2 nd 1/4 jump scenario, the first RAM performs zero-crossing update, and at this time, the state information of the clock loop in the first RAM may have three situations: when the arrival of the data packet is updated to 00, the 00 jumps to 01 when the 1 st 1/4 jumps, or the 10 keeps when the 1 st 1/4 jumps; at this time, the refresh of the first RAM is: if the clock-ring status information in the first RAM is 01, indicating that no packet arrived in this 1/4 cycles, the half overflow indicated by 01 needs to be rewritten to 10 indicating a full overflow; if the clock collar status information 10 or 00 in the first RAM remains unchanged.
At the end of the third sub-period, performing a first operation on the second RAM, including: if the clock ferrule state information in the second RAM is in the initial state, setting the clock ferrule state information to be half-overflow; if the clock ferrule state information in the second RAM is full overflow, keeping the current clock ferrule state information in the second RAM;
specifically, when the current clock count has the 3 rd 1/4 jump scene, the second RAM performs zero-crossing updating; in the 3 rd 1/4 jump scenario, only 00 and 10 states exist for the second RAM, since the last second RAM update process has only two possibilities: the arrival of the data packet is updated to 00, or 10/00 keeps under the 4 th 1/4 jump scene, or 01 jumps to 10; thus, at this time, the refresh to the second RAM is: if the clock collar status information in the second RAM is 00, then the rewrite is 01, otherwise, 10 is maintained.
At the end of the fourth sub-period, performing a first operation on the second RAM, including: if the clock ferrule state information in the second RAM is half-overflow, setting the clock ferrule state information to be full-overflow, otherwise, keeping the current clock ferrule state information in the second RAM;
specifically, when the 4 th 1/4 jump scenario occurs in the current clock count, the second RAM performs zero-crossing update, and at this time, the state information of the clock loop in the second RAM may have three situations: when the arrival of the data packet is updated to 00, the 00 jumps to 01 when the 3 rd 1/4 jumps, or the 10 keeps when the 3 rd 1/4 jumps; at this time, the refresh of the second RAM is: if the clock-ring status information in the second RAM is 01, indicating that no data packet arrives in 1/4 cycles, the half-overflow indicated by 01 needs to be rewritten to 10 to indicate a full overflow; if the clock collar status information in the second RAM is 10 or 00, it remains unchanged.
Step 103: when the data packet arrives, performing second operation on the first RAM and/or the second RAM according to a second preset rule, and adding tokens into the token bucket according to a third preset rule according to a second operation result;
here, the second preset rule is a rule for reading the clock loop status information from the RAM, and may be determined according to the condition that the clock loop status information is updated in the RAM in the first preset rule; adding tokens to the token bucket is controlled based on determining a second operation result from the clock collar state information in the second RAM, such as when the first RAM performs a clock collar state information update.
Further, the second preset rule may be that when the arrival time point of the packet is within each sub-period, the first RAM and the second RAM are subjected to a second operation; when the clock ferrule state information read by the second operation in the first RAM and the second RAM is full overflow, determining a second operation result as full overflow; when the arrival time point of the data packet is in the first operation process after the first sub-period is finished or the first operation process after the second sub-period is finished, performing second operation on the second RAM; determining the clock ferrule state information in the second RAM read by the second operation as a second operation result; when the arrival time point of the data packet is in a third operation process after the third sub-period is finished or a first operation process after the fourth sub-period is finished, performing a second operation on the first RAM; determining the clock ferrule state information in the first RAM read by the second operation as a second operation result;
specifically, if the arrival time of the data packet is in each sub-period, that is, when the data packet is not in a scene where the high 2 bits of the clock counter jump from 00 to 01, or the 01 jump to 10, or the 10 jump to 11, or the 11 jump to 00, the state information of the clock ferrules in the first RAM and the second RAM can be read, and the result of the second operation is determined by combining the state information of the clock ferrules in the two RAMs; in a scene that the arrival time of the data packet is in each sub-period, when the state information of the clock ferrules in the first RAM and the second RAM is full overflow, determining a second operation result as full overflow; when the clock ferrule state information in the first RAM and the second RAM is not all full overflow, determining the second operation result as non-full overflow;
if the arrival time of the data packet is in a scene that the high 2 bits of the clock counter jump from 00 to 01 or 01 jumps to 10, namely a 1 st 1/4 jump scene and a 2 nd jump scene; according to step 102, at this time, the first RAM is occupied by clock ferrule status information updates; at this time, the clock collar status information in the second RAM may be determined as a second operation result;
if the arrival time of the data packet is in a scene that the high 2 bits of the clock counter are changed from 10 to 11 or 11 to 00, namely a 3 rd 1/4 jump scene and a 4 th jump scene; according to step 102, at this time, the second RAM is occupied by clock ferrule status information updates; at this point, the clock collar status information in the third RAM may be determined as the second operation result.
After a second operation result is determined, adding tokens into the token bucket according to a third preset rule; the third preset rule is used for determining a rule for adding tokens into the token bucket according to the clock ferrule state information; the token adding amount can be determined by filling the token bucket or according to the product of the token adding speed and the interval time difference between the previous data packet and the next data packet; here, the time length of each sub-period can be determined according to the relation between the time length of each sub-period and the time length of the full token bucket, the state indicated by the set clock ferrule state information, and the like; as the above 4 sub-period durations are all greater than the full token bucket adding duration, the full overflow state determined by the two 1/4 hopping scenarios can be ensured, and the token bucket can be filled if the two packet arrival time intervals are certainly greater than the full token bucket adding duration;
specifically, if the second operation result is full overflow, the token bucket is filled; otherwise, the time interval between the arrival of the two data packets before and after the arrival of the two data packets cannot be completely ensured to be longer than the time length of adding the full token bucket; accordingly, a time difference between a current packet and a last packet may be determined, and a product of the determined time difference multiplied by a preset token addition speed is determined as the number of tokens added to the token bucket. Here, the time difference between the current packet and the last packet may be determined by using the existing technology, recording the arrival global time when each packet arrives, and keeping in a preset memory or buffer, and when the time difference needs to be calculated, taking out the time values of the two previous and next packets and subtracting to obtain the time difference.
Further, if the second operation is performed on the first RAM or the second RAM, after the second operation result is obtained, the clock ferrule state information in the first RAM or the second RAM on which the second operation is performed is set to be in an initial state; if the first RAM and the second RAM are subjected to second operation, after a second operation result is obtained, setting the state information of the clock ferrules in the first RAM and the second RAM, which are subjected to the second operation, to be an initial state;
specifically, if the arrival time point of the data packet is within each sub-period, the clock loop status information of the first RAM and the second RAM may be set to 00 after determining the second operation result; if the arrival time of the data packet is in a scene that the high 2 bits of the clock counter are changed from 00 to 01 or 01 is changed to 10, namely a 1 st 1/4 jump scene and a 2 nd jump scene, the data packet is the second RAM in the second operation object, and therefore, the clock ferrule state information of the second RAM can be set to 00; if the arrival time of the data packet is in the first RAM at the scene that the high 2 bits of the clock counter are changed from 10 to 11 or 11 to 00, namely the 3 rd 1/4 jump scene and the 4 th jump scene, at this time, the data packet is the second operation object, therefore, the clock ring status information of the first RAM can be set to 00.
By adopting the method provided by the embodiment of the invention, two RAMs are alternately used, and when one RAM is occupied by updating the clock ferrule state information, the other RAM is used for providing the clock ferrule state information added by the token of the token bucket; the two RAMs respectively record the clock ring state information of two adjacent 1/4 hopping scenes, the interval duration of the two adjacent 1/4 hopping scenes is larger than the full duration of the token bucket, and the clock ring state information can be accurately provided.
The positive effects produced by the present invention will be described in further detail with reference to specific examples below;
the overall flow of network traffic supervision by using the token adding method of the embodiment of the invention is shown in fig. 2:
step 201: receiving a service message and acquiring queue information corresponding to the message;
step 202: according to the queue information of the message, inquiring the arrival time of the last data packet, the current clock time and the clock ferrule state information corresponding to the queue, and calculating the token adding action of the token bucket corresponding to the queue: filling a token bucket or adding tokens according to the time difference between the current clock time and the arrival time of the last data packet multiplied by a token adding rate;
step 203: acquiring a configured supervision algorithm and a working mode corresponding to the queue and the current token bucket state of the queue, and then adding tokens according to the queue information of the message and the token adding action, wherein the adding cannot exceed the maximum capacity of the token bucket;
step 204: and carrying out flow supervision on the service message according to the token bucket state of the message queue and related configuration of a supervision algorithm, and coloring or carrying out discarding and forwarding actions.
In the scenario that the arrival time point of the data packet is within each sub-period, the detailed flow of network traffic supervision is as shown in fig. 3:
step 301: receiving a service message, acquiring queue information corresponding to the message, and acquiring the current clock time, wherein 1/4 jump scene conditions of current clock counting do not occur; here, the 1/4 jump scenario case represents a scenario in which no 00 jump to 01, 01 jump to 10, 10 jump to 11, and 11 jump to 00 occur in the upper 2 bits of the current clock time;
step 302: reading the values of the two RAMs of the queue according to the queue information of the message, if the two RAMs are both 10, the current queue is indicated that no data packet arrives at least in 1/4 periods, and filling the token bucket according to the premise that the clock counter 1/4 period ensures that the token bucket can be filled; under other conditions, 1/4 cycle loop can not be ensured to occur between two times of data packet arrival, at this time, the arrival time of the last data packet of the queue needs to be obtained, the time difference is calculated by combining the current clock time, and the time difference is multiplied by the token adding speed to obtain the number of tokens to be added at this time;
step 303: acquiring supervision algorithm configuration and current token bucket parameters of the queue according to the queue information of the message, adding tokens according to rules by combining the number of the tokens to be added obtained in the last step, wherein the value of the token bucket after addition cannot exceed the maximum capacity of the tokens;
step 304: and monitoring the message according to the monitoring algorithm configured by the queue, performing token consumption, and marking colors.
The detailed flow of network traffic supervision when the packet arrival time point jumps in the 1 st 1/4 jump scenario is shown in fig. 4:
the 1 st 1/4 transition scenario here represents the transition of the current clock counter from 00 to 01 at the 2 nd high bit.
Step 401: receiving a service message, acquiring queue information corresponding to the message, acquiring current clock time, and finding that the 1 st 1/4 jump scene condition occurs in the current clock count, wherein the first RAM updates the clock ferrule state information in the scene, and at the moment, the first RAM only has 00 and 10 scenes, which is because the last updating process of the first RAM has only two possibilities: the arrival of the data packet is updated to 00, or 10/00 keeps or 01 jumps to 10 under the 2 nd jump scene of 1/4; therefore, the refresh principle at this time is 00 overwrite to 01, or 10 hold;
step 402: adding a token according to the clock ferrule state information in the second RAM; reading the clock ferrule state information of the second RAM of the queue according to the queue information of the message, wherein the last updating actions of the second RAM include two actions: the arrival of the data packet is updated to 00 or 10/00 keeps under the 4 th 1/4 jump scene, or 01 jumps to 10; therefore, the second RAM at this time may be 10 or 00. If it is 10, indicating no packet has arrived for at least 1/4 cycles of the clock counter, the token bucket will be refilled; if the current queue is 00, acquiring the last data packet arrival time of the current queue, calculating a time difference by combining the current clock time, and multiplying the time difference by the token adding speed to obtain the number of tokens to be added at this time;
step 403: acquiring supervision algorithm configuration and current token bucket parameters of the queue according to the queue information of the message, adding tokens according to rules by combining the number of the tokens to be added obtained in the last step, wherein the value of the token bucket after addition cannot exceed the maximum capacity of the tokens;
step 404: and monitoring the message according to a monitoring algorithm configured by the queue, performing token consumption, and marking colors.
The detailed flow of network traffic supervision when the packet arrival time point jumps in the 2 nd 1/4 jump scenario is shown in fig. 5:
the 2 nd 1/4 jump scenario here represents the jump process of the current clock counter from 01 to 10 at the high 2 bits;
step 501: receiving a service message, acquiring queue information corresponding to the message, acquiring current clock time, and finding that the situation of the 2 nd 1/4 jump scene occurs in the current clock count, wherein the first RAM updates the state information of the clock loop in the scene, and at this time, the first RAM may have three situations: when the arrival of the data packet is updated to 00, the 00 jump becomes 01 in the 1 st 1/4 jump scene, or the 10 is maintained in the 1 st 1/4 jump scene. The refresh principle at this time is: if 01, meaning that no packet arrived within this 1/4 cycles, then the half overflow denoted 01 needs to be rewritten to 10 to denote a full overflow, and if 10 or 00, then hold;
step 502: adding a token according to the clock ferrule state information in the second RAM; reading the clock ferrule state information of the second RAM according to the queue information of the message, wherein the state of the second RAM can be 10 or 00; the principle is the same as that of step 402, and is not described herein again; if the number of the tokens is 10, the token bucket is filled according to a rule, the arrival time of the last data packet of the current queue is obtained in the case of 00, the time difference is calculated by combining the current clock time, and the time difference is multiplied by the token adding speed to obtain the number of the tokens to be added;
step 503: acquiring supervision algorithm configuration and current token bucket parameters of the queue according to the queue information of the message, adding tokens according to rules by combining the number of the tokens to be added obtained in the last step, wherein the value of the token bucket after addition cannot exceed the maximum capacity of the tokens;
step 504: and monitoring the message according to a monitoring algorithm configured by the queue, performing token consumption, and marking colors.
The detailed flow of network traffic supervision when the packet arrival time point jumps in the 3 rd 1/4 jump scenario is shown in fig. 6:
the 3 rd 1/4 jump scenario here represents the jump process where the current clock counter jumps from 10 to 11 in the high 2 bits.
Step 601: receiving a service message, acquiring queue information corresponding to the message, acquiring current clock time, and finding the situation that the current clock count has the 3 rd 1/4 jump scene, wherein the state information of a clock loop is updated by a second RAM in the scene, the refreshing principle is that 00 is rewritten into 01, and 10 is kept; the principle is similar to that of step 401, and is not described herein again;
step 602: adding a token according to the clock ferrule state information in the first RAM; reading the clock ferrule state information of the first RAM according to the queue information of the message, and if the clock ferrule state information is 10, performing a filling action on the token bucket according to a rule; 00, obtaining the last data packet arrival time of the current queue, calculating the time difference by combining the current clock time, and multiplying the time difference by the token adding speed to obtain the number of tokens to be added at this time; the principle is the same as that of step 402, and is not described herein again;
step 603: acquiring supervision algorithm configuration and current token bucket parameters of the queue according to the queue information of the message, adding tokens according to rules by combining the number of the tokens to be added obtained in the last step, wherein the value of the token bucket after addition cannot exceed the maximum capacity of the tokens;
step 604: and monitoring the message according to a monitoring algorithm configured by the queue, performing token consumption, and marking colors.
The detailed flow of network traffic supervision when the packet arrival time point jumps to the 4 th 1/4 scenario is shown in fig. 7:
the 4 th 1/4 jump scenario here represents the jump process where the current clock counter jumps from 11 to 00 at the high 2 bits.
Step 701: receiving a service message, acquiring queue information corresponding to the message, acquiring current clock time, and finding the situation that the 4 th 1/4 jump scene occurs in the current clock count, wherein the state information of a clock loop is updated by a second RAM in the scene, and the refreshing principle is that 01 is rewritten into 10, and 10 or 00 is maintained; the principle is the same as that of step 501, and is not described herein again;
step 702: adding a token according to the clock ferrule state information in the first RAM; reading the clock ferrule state information of the first RAM according to the queue information of the message, and if the clock ferrule state information is 10, performing a filling action on the token bucket according to a rule; 00, obtaining the last data packet arrival time of the current queue, calculating the time difference by combining the current clock time, and multiplying the time difference by the token adding speed to obtain the number of tokens to be added at this time; the principle is the same as that of step 402, and is not described herein again;
step 703: acquiring supervision algorithm configuration and current token bucket parameters of the queue according to the queue information of the message, adding tokens according to rules by combining the number of the tokens to be added obtained in the last step, wherein the value of the token bucket after addition cannot exceed the maximum capacity of the tokens;
step 704: and monitoring the message according to a monitoring algorithm configured by the queue, performing token consumption, and marking colors.
As shown in fig. 8, the token adding apparatus provided in the embodiment of the present invention includes: a setup module 81, a first operation module 82 and a second operation module 83; wherein:
the setting module 81: the clock cycle is divided into more than 1 sub-cycle, and a first operation is carried out at the end of each sub-cycle; presetting two RAMs, namely a first RAM and a second RAM, and setting that when one RAM is subjected to first operation, the other RAM is subjected to second operation;
here, the first operation is updating clock loop state information in the RAM, and the second operation is reading the clock loop state information in the RAM for calculating the number of tokens added to the token bucket; the clock period division and the RAM setting can be carried out in the network flow monitoring device; the clock cycle can be a clock cycle used for recording the arrival time of two successive data packets, and a clock counter can realize the clock cycle counting function; the clock period can be divided into more than 1 sub-period, and similar to recording clock ferrule state information when a clock counter appears in a ferrule in the prior art, the clock ferrule state information can be recorded in the RAM when one sub-period is finished; wherein the clock ferrule state information may include: initial state, half overflow and full overflow, the three clock ferrule state information can be represented in RAM by 00, 01 and 10 respectively, and can also be represented by other self-defined modes; the initial state, the half overflow and the full overflow can be used for recording the mark of the clock timer crossing the sub-period so as to be used as the basis for continuously adding the token;
two RAMs, namely a first RAM and a second RAM, can be arranged in the network flow monitoring device for recording the ferrule condition, and two RAMs of 1w1r can be respectively used as the first RAM and the second RAM; here, the first and second electrodes; the first RAM and the second RAM may be configured to: one of the RAMs is occupied with clock loop state information updates, and the other RAM provides the clock loop state information needed for current token additions.
Further, the clock cycle may be divided into a first sub-cycle, a second sub-cycle, a third sub-cycle, and a fourth sub-cycle, where 4 sub-cycles are equal; the first sub-period, the second sub-period, the third sub-period and the fourth sub-period may be 4 periods sequentially arranged in one clock period; the duration of each sub-period is greater than the full duration of the token bucket; the token bucket full time length refers to a time length from adding tokens to an empty token bucket at a predetermined token adding rate until the token bucket is full.
The first operation module 82 is configured to perform a first operation on the first RAM or the second RAM according to a first preset rule;
here, the first preset rule is a rule for updating the state information of the clock loop to the RAM, and may be determined according to the number of sub-cycles in the one clock cycle and a relationship between the sub-cycles and the token bucket full-time.
Further, the clock cycle may be divided into 4 sub-cycles with equal cycles, and the duration of each sub-cycle is greater than the token bucket full duration; in this case, the first preset rule may be: when the first sub-period and the second sub-period are finished, performing first operation on the first RAM; when the third sub-period and the fourth sub-period are finished, performing first operation on the second RAM;
specifically, the clock period is usually counted by a clock period clock counter, and the high 2 bits of the clock counter can reflect the condition of 4 sub-periods, for example, when the high 2 bits 00 jump to 01, the first sub-period ends, when the high 2 bits 01 jump to 10, the second sub-period ends, when the high 2 bits 10 jump to 11, the third sub-period ends, and when the high 2 bits 11 jump to 00, the fourth sub-period ends; here, the zero-crossing self-refresh scenario may be determined in a scenario where the high 2 bits 00 of the clock counter jump to 01, 01 jumps to 10, 10 jumps to 11, and 11 jumps to 00; performing first operation on the first RAM or the second RAM in a zero-crossing self-refresh scene; meanwhile, 00 hops 01 are determined as the 1 st 1/4 hopping scene, 01 hops 10 are determined as the 2 nd 1/4 hopping scene, 10 hops 11 are determined as the 3 rd 1/4 hopping scene, and 11 hops 00 are determined as the 4 th 1/4 hopping scene; in the 4 jumping scenes, updating the state information of the clock loop for each service flow; the number of service flows determines the time length for completing the updating of the state information of all clock ferrules, namely the time length of a hopping scene, for example, according to the prior art, 32K read-write cycles are required for updating the state information of the clock ferrules of 16K service flows.
At the end of the first sub-period, i.e. in the 1 st 1/4 jump scenario, performing a first operation on the first RAM, including: if the clock ferrule state information in the first RAM is in an initial state, setting the clock ferrule state information to be half-overflow; if the clock ferrule state information in the first RAM is full overflow, keeping the current clock ferrule state information in the first RAM; here, a half-overflow condition may indicate that the clock counter has experienced an 1/4 transition scenario, but cannot determine whether the clock counter has walked longer than 1 sub-cycle; the full overflow state represents that the clock counter has undergone 1/4 hopping scenes at least twice, and the two hopping scenes can ensure that the time length of the clock counter is greater than or equal to the sub-period, and the time length of the sub-period is greater than the time length of the full token bucket; therefore, the initial state, the half overflow state and the full overflow state can be used as the basis for continuously adding tokens;
specifically, when the current clock count has the 1 st 1/4 jump scene, the first RAM performs zero-crossing updating; here, 00, 01, and 10 are used in RAM to indicate clock-loop status information, respectively: initial state, half-spill and full-spill said three clock ferrule state information; in the 1 st 1/4 jump scenario, only 00 and 10 states exist for the first RAM, since the last first RAM update process has only two possibilities: the arrival of the data packet is updated to 00, or 10/00 keeps under the 2 nd 1/4 jump scene, or 01 jump is changed to 10; thus, at this time, the refresh of the first RAM is: if the clock ferrule state information in the first RAM is 00, rewriting to 01, otherwise, keeping 10;
and when the second sub-period is finished, performing a first operation on the first RAM, wherein the first operation comprises: if the clock ferrule state information in the first RAM is half-overflow, setting the clock ferrule state information to be full-overflow, otherwise, keeping the clock ferrule state information in the first RAM;
specifically, when the current clock count has the 2 nd 1/4 jump scenario, the first RAM performs zero-crossing update, and at this time, the state information of the clock loop in the first RAM may have three situations: when the arrival of the data packet is updated to 00, the 00 jumps to 01 when the 1 st 1/4 jumps, or the 10 keeps when the 1 st 1/4 jumps; at this time, the refresh of the first RAM is: if the clock-ring status information in the first RAM is 01, indicating that no packet arrived in this 1/4 cycles, the half overflow indicated by 01 needs to be rewritten to 10 indicating a full overflow; if the clock collar status information 10 or 00 in the first RAM remains unchanged.
At the end of the third sub-period, performing a first operation on the second RAM, including: if the clock ferrule state information in the second RAM is in the initial state, setting the clock ferrule state information to be half-overflow; if the clock ferrule state information in the second RAM is full overflow, keeping the current clock ferrule state information in the second RAM;
specifically, when the current clock count has the 3 rd 1/4 jump scene, the second RAM performs zero-crossing updating; in the 3 rd 1/4 jump scenario, only 00 and 10 states exist for the second RAM, since the last second RAM update process has only two possibilities: the arrival of the data packet is updated to 00, or 10/00 keeps under the 4 th 1/4 jump scene, or 01 jumps to 10; thus, at this time, the refresh to the second RAM is: if the clock collar status information in the second RAM is 00, then the rewrite is 01, otherwise, 10 is maintained.
At the end of the fourth sub-period, performing a first operation on the second RAM, including: if the clock ferrule state information in the second RAM is half-overflow, setting the clock ferrule state information to be full-overflow, otherwise, keeping the current clock ferrule state information in the second RAM;
specifically, when the 4 th 1/4 jump scenario occurs in the current clock count, the second RAM performs zero-crossing update, and at this time, the state information of the clock loop in the second RAM may have three situations: when the arrival of the data packet is updated to 00, the 00 jumps to 01 when the 3 rd 1/4 jumps, or the 10 keeps when the 3 rd 1/4 jumps; at this time, the refresh of the second RAM is: if the clock-ring status information in the second RAM is 01, indicating that no data packet arrives in 1/4 cycles, the half-overflow indicated by 01 needs to be rewritten to 10 to indicate a full overflow; if the clock collar status information in the second RAM is 10 or 00, it remains unchanged.
The second operation module 83 is configured to, when a data packet arrives, perform a second operation on the first RAM and/or the second RAM according to a second preset rule, and add a token to the token bucket according to a third preset rule according to a second operation result;
here, the second preset rule is a rule for reading the clock loop status information from the RAM, and may be determined according to the condition that the clock loop status information is updated in the RAM in the first preset rule; adding tokens to the token bucket is controlled based on determining a second operation result from the clock collar state information in the second RAM, such as when the first RAM performs a clock collar state information update.
Further, the second preset rule may be that when the arrival time point of the packet is within each sub-period, the first RAM and the second RAM are subjected to a second operation; when the clock ferrule state information read by the second operation in the first RAM and the second RAM is full overflow, determining a second operation result as full overflow; when the arrival time point of the data packet is in the first operation process after the first sub-period is finished or the first operation process after the second sub-period is finished, performing second operation on the second RAM; determining the clock ferrule state information in the second RAM read by the second operation as a second operation result; when the arrival time point of the data packet is in a third operation process after the third sub-period is finished or a first operation process after the fourth sub-period is finished, performing a second operation on the first RAM; determining the clock ferrule state information in the first RAM read by the second operation as a second operation result;
specifically, if the arrival time of the data packet is in each sub-period, that is, when the data packet is not in a scene where the high 2 bits of the clock counter jump from 00 to 01, or the 01 jump to 10, or the 10 jump to 11, or the 11 jump to 00, the state information of the clock ferrules in the first RAM and the second RAM can be read, and the result of the second operation is determined by combining the state information of the clock ferrules in the two RAMs; in a scene that the arrival time of the data packet is in each sub-period, when the state information of the clock ferrules in the first RAM and the second RAM is full overflow, determining a second operation result as full overflow; when the clock ferrule state information in the first RAM and the second RAM is not all full overflow, determining the second operation result as non-full overflow;
if the arrival time of the data packet is in a scene that the high 2 bits of the clock counter jump from 00 to 01 or 01 jumps to 10, namely a 1 st 1/4 jump scene and a 2 nd jump scene; according to the operation steps of the first operation module, at the moment, the first RAM is occupied by updating the state information of the clock ferrule; at this time, the clock collar status information in the second RAM may be determined as a second operation result;
if the arrival time of the data packet is in a scene that the high 2 bits of the clock counter are changed from 10 to 11 or 11 to 00, namely a 3 rd 1/4 jump scene and a 4 th jump scene; according to the operation steps of the first operation module, at the moment, the second RAM is occupied by updating the state information of the clock ferrule; at this point, the clock collar status information in the third RAM may be determined as the second operation result.
After a second operation result is determined, adding tokens into the token bucket according to a third preset rule; the third preset rule is used for determining a rule for adding tokens into the token bucket according to the clock ferrule state information; the token adding amount can be determined by filling the token bucket or according to the product of the token adding speed and the interval time difference between the previous data packet and the next data packet; here, the time length of each sub-period can be determined according to the relation between the time length of each sub-period and the time length of the full token bucket, the state indicated by the set clock ferrule state information, and the like; as the above 4 sub-period durations are all greater than the full token bucket adding duration, the full overflow state determined by the two 1/4 hopping scenarios can be ensured, and the token bucket can be filled if the two packet arrival time intervals are certainly greater than the full token bucket adding duration;
specifically, if the second operation result is full overflow, the token bucket is filled; otherwise, the time interval between the arrival of the two data packets before and after the arrival of the two data packets cannot be completely ensured to be longer than the time length of adding the full token bucket; accordingly, a time difference between a current packet and a last packet may be determined, and a product of the determined time difference multiplied by a preset token addition speed is determined as the number of tokens added to the token bucket. Here, the time difference between the current packet and the last packet may be determined by using the existing technology, recording the arrival global time when each packet arrives, and keeping in a preset memory or buffer, and when the time difference needs to be calculated, taking out the time values of the two previous and next packets and subtracting to obtain the time difference.
Further, if the second operation is performed on the first RAM or the second RAM, after the second operation result is obtained, the clock ferrule state information in the first RAM or the second RAM on which the second operation is performed is set to be in an initial state; if the first RAM and the second RAM are subjected to second operation, after a second operation result is obtained, setting the state information of the clock ferrules in the first RAM and the second RAM, which are subjected to the second operation, to be an initial state;
specifically, if the arrival time point of the data packet is within each sub-period, the clock loop status information of the first RAM and the second RAM may be set to 00 after determining the second operation result; if the arrival time of the data packet is in a scene that the high 2 bits of the clock counter are changed from 00 to 01 or 01 is changed to 10, namely a 1 st 1/4 jump scene and a 2 nd jump scene, the data packet is the second RAM in the second operation object, and therefore, the clock ferrule state information of the second RAM can be set to 00; if the arrival time of the data packet is in the first RAM at the scene that the high 2 bits of the clock counter are changed from 10 to 11 or 11 to 00, namely the 3 rd 1/4 jump scene and the 4 th jump scene, at this time, the data packet is the second operation object, therefore, the clock ring status information of the first RAM can be set to 00.
By adopting the device provided by the embodiment of the invention, two RAMs are alternately used, and when one RAM is occupied by updating the clock ferrule state information, the other RAM is used for providing the clock ferrule state information added by the token of the token bucket; the two RAMs respectively record the clock ring state information of two adjacent 1/4 hopping scenes, the interval duration of the two adjacent 1/4 hopping scenes is larger than the full duration of the token bucket, and the clock ring state information can be accurately provided.
In practical applications, the setting module 81, the first operating module 82, and the second operating module 83 may be implemented by a Central Processing Unit (CPU), a microprocessor unit (MPU), a Digital Signal Processor (DSP), or a Field Programmable Gate Array (FPGA), etc. in the network traffic monitoring device or system.
The storage medium provided by the embodiment of the invention is stored with an executable program, and the executable program realizes the step of operating the RAM in the token adding method when being executed by a processor;
the token adding method, as shown in fig. 1, includes:
step 101: presetting two RAMs, namely a first RAM and a second RAM, and performing second operation on one RAM in the two RAMs when performing first operation on the other RAM;
here, the first operation is updating clock loop state information in the RAM, and the second operation is reading the clock loop state information in the RAM for calculating the number of tokens added to the token bucket; setting of the RAM can be carried out in the network flow monitoring device; wherein the clock ferrule state information may include: initial state, half overflow and full overflow, the three clock ferrule state information can be represented in RAM by 00, 01 and 10 respectively, and can also be represented by other self-defined modes; the initial state, the half overflow and the full overflow can be used for recording the mark of the clock timer crossing the sub-period so as to be used as the basis for continuously adding the token;
two RAMs, namely a first RAM and a second RAM, can be arranged in the network flow monitoring device for recording the ferrule condition, and two RAMs of 1w1r can be respectively used as the first RAM and the second RAM; here, the first and second electrodes; the first RAM and the second RAM may be configured to: one of the RAMs is occupied with clock loop state information updates, and the other RAM provides the clock loop state information needed for current token additions.
Further, the clock period may be divided into 4 equal sub-periods of the first sub-period, the second sub-period, the third sub-period, and the fourth sub-period in the network traffic policing device; the clock cycle can be a clock cycle used for recording the arrival time of two successive data packets, and a clock counter can realize the clock cycle counting function; the clock period can be divided into more than 1 sub-period, and similar to recording clock ferrule state information when a clock counter appears in a ferrule in the prior art, the clock ferrule state information can be recorded in the RAM when one sub-period is finished; the first sub-period, the second sub-period, the third sub-period and the fourth sub-period may be 4 periods sequentially arranged in one clock period; the duration of each sub-period is greater than the full duration of the token bucket; the token bucket full time length refers to a time length from adding tokens to an empty token bucket at a predetermined token adding rate until the token bucket is full.
Step 102: performing first operation on the first RAM or the second RAM according to a first preset rule;
here, the first preset rule is a rule for updating the state information of the clock loop to the RAM, and may be determined according to the number of sub-cycles in the one clock cycle and a relationship between the sub-cycles and the token bucket full-time.
Further, the clock cycle may be divided into 4 sub-cycles with equal cycles, and the duration of each sub-cycle is greater than the token bucket full duration; in this case, the first preset rule may be: when the first sub-period and the second sub-period are finished, performing first operation on the first RAM; when the third sub-period and the fourth sub-period are finished, performing first operation on the second RAM;
specifically, the clock period is usually counted by a clock period clock counter, and the high 2 bits of the clock counter can reflect the condition of 4 sub-periods, for example, when the high 2 bits 00 jump to 01, the first sub-period ends, when the high 2 bits 01 jump to 10, the second sub-period ends, when the high 2 bits 10 jump to 11, the third sub-period ends, and when the high 2 bits 11 jump to 00, the fourth sub-period ends; here, the zero-crossing self-refresh scenario may be determined in a scenario where the high 2 bits 00 of the clock counter jump to 01, 01 jumps to 10, 10 jumps to 11, and 11 jumps to 00; performing first operation on the first RAM or the second RAM in a zero-crossing self-refresh scene; meanwhile, 00 hops 01 are determined as the 1 st 1/4 hopping scene, 01 hops 10 are determined as the 2 nd 1/4 hopping scene, 10 hops 11 are determined as the 3 rd 1/4 hopping scene, and 11 hops 00 are determined as the 4 th 1/4 hopping scene; in the 4 jumping scenes, updating the state information of the clock loop for each service flow; the number of service flows determines the time length for completing the updating of the state information of all clock ferrules, namely the time length of a hopping scene, for example, according to the prior art, 32K read-write cycles are required for updating the state information of the clock ferrules of 16K service flows.
At the end of the first sub-period, i.e. in the 1 st 1/4 jump scenario, performing a first operation on the first RAM, including: if the clock ferrule state information in the first RAM is in an initial state, setting the clock ferrule state information to be half-overflow; if the clock ferrule state information in the first RAM is full overflow, keeping the current clock ferrule state information in the first RAM; here, a half-overflow condition may indicate that the clock counter has experienced an 1/4 transition scenario, but cannot determine whether the clock counter has walked longer than 1 sub-cycle; the full overflow state represents that the clock counter has undergone 1/4 hopping scenes at least twice, and the two hopping scenes can ensure that the time length of the clock counter is greater than or equal to the sub-period, and the time length of the sub-period is greater than the time length of the full token bucket; therefore, the initial state, the half overflow state and the full overflow state can be used as the basis for continuously adding tokens;
specifically, when the current clock count has the 1 st 1/4 jump scene, the first RAM performs zero-crossing updating; here, 00, 01, and 10 are used in RAM to indicate clock-loop status information, respectively: initial state, half-spill and full-spill said three clock ferrule state information; in the 1 st 1/4 jump scenario, only 00 and 10 states exist for the first RAM, since the last first RAM update process has only two possibilities: the arrival of the data packet is updated to 00, or 10/00 keeps under the 2 nd 1/4 jump scene, or 01 jump is changed to 10; thus, at this time, the refresh of the first RAM is: if the clock ferrule state information in the first RAM is 00, rewriting to 01, otherwise, keeping 10;
and when the second sub-period is finished, performing a first operation on the first RAM, wherein the first operation comprises: if the clock ferrule state information in the first RAM is half-overflow, setting the clock ferrule state information to be full-overflow, otherwise, keeping the clock ferrule state information in the first RAM;
specifically, when the current clock count has the 2 nd 1/4 jump scenario, the first RAM performs zero-crossing update, and at this time, the state information of the clock loop in the first RAM may have three situations: when the arrival of the data packet is updated to 00, the 00 jumps to 01 when the 1 st 1/4 jumps, or the 10 keeps when the 1 st 1/4 jumps; at this time, the refresh of the first RAM is: if the clock-ring status information in the first RAM is 01, indicating that no packet arrived in this 1/4 cycles, the half overflow indicated by 01 needs to be rewritten to 10 indicating a full overflow; if the clock collar status information 10 or 00 in the first RAM remains unchanged.
At the end of the third sub-period, performing a first operation on the second RAM, including: if the clock ferrule state information in the second RAM is in the initial state, setting the clock ferrule state information to be half-overflow; if the clock ferrule state information in the second RAM is full overflow, keeping the current clock ferrule state information in the second RAM;
specifically, when the current clock count has the 3 rd 1/4 jump scene, the second RAM performs zero-crossing updating; in the 3 rd 1/4 jump scenario, only 00 and 10 states exist for the second RAM, since the last second RAM update process has only two possibilities: the arrival of the data packet is updated to 00, or 10/00 keeps under the 4 th 1/4 jump scene, or 01 jumps to 10; thus, at this time, the refresh to the second RAM is: if the clock collar status information in the second RAM is 00, then the rewrite is 01, otherwise, 10 is maintained.
At the end of the fourth sub-period, performing a first operation on the second RAM, including: if the clock ferrule state information in the second RAM is half-overflow, setting the clock ferrule state information to be full-overflow, otherwise, keeping the current clock ferrule state information in the second RAM;
specifically, when the 4 th 1/4 jump scenario occurs in the current clock count, the second RAM performs zero-crossing update, and at this time, the state information of the clock loop in the second RAM may have three situations: when the arrival of the data packet is updated to 00, the 00 jumps to 01 when the 3 rd 1/4 jumps, or the 10 keeps when the 3 rd 1/4 jumps; at this time, the refresh of the second RAM is: if the clock-ring status information in the second RAM is 01, indicating that no data packet arrives in 1/4 cycles, the half-overflow indicated by 01 needs to be rewritten to 10 to indicate a full overflow; if the clock collar status information in the second RAM is 10 or 00, it remains unchanged.
Step 103: when the data packet arrives, performing second operation on the first RAM and/or the second RAM according to a second preset rule, and adding tokens into the token bucket according to a third preset rule according to a second operation result;
here, the second preset rule is a rule for reading the clock loop status information from the RAM, and may be determined according to the condition that the clock loop status information is updated in the RAM in the first preset rule; adding tokens to the token bucket is controlled based on determining a second operation result from the clock collar state information in the second RAM, such as when the first RAM performs a clock collar state information update.
Further, the second preset rule may be that when the arrival time point of the packet is within each sub-period, the first RAM and the second RAM are subjected to a second operation; when the clock ferrule state information read by the second operation in the first RAM and the second RAM is full overflow, determining a second operation result as full overflow; when the arrival time point of the data packet is in the first operation process after the first sub-period is finished or the first operation process after the second sub-period is finished, performing second operation on the second RAM; determining the clock ferrule state information in the second RAM read by the second operation as a second operation result; when the arrival time point of the data packet is in a third operation process after the third sub-period is finished or a first operation process after the fourth sub-period is finished, performing a second operation on the first RAM; determining the clock ferrule state information in the first RAM read by the second operation as a second operation result;
specifically, if the arrival time of the data packet is in each sub-period, that is, when the data packet is not in a scene where the high 2 bits of the clock counter jump from 00 to 01, or the 01 jump to 10, or the 10 jump to 11, or the 11 jump to 00, the state information of the clock ferrules in the first RAM and the second RAM can be read, and the result of the second operation is determined by combining the state information of the clock ferrules in the two RAMs; in a scene that the arrival time of the data packet is in each sub-period, when the state information of the clock ferrules in the first RAM and the second RAM is full overflow, determining a second operation result as full overflow; when the clock ferrule state information in the first RAM and the second RAM is not all full overflow, determining the second operation result as non-full overflow;
if the arrival time of the data packet is in a scene that the high 2 bits of the clock counter jump from 00 to 01 or 01 jumps to 10, namely a 1 st 1/4 jump scene and a 2 nd jump scene; according to step 102, at this time, the first RAM is occupied by clock ferrule status information updates; at this time, the clock collar status information in the second RAM may be determined as a second operation result;
if the arrival time of the data packet is in a scene that the high 2 bits of the clock counter are changed from 10 to 11 or 11 to 00, namely a 3 rd 1/4 jump scene and a 4 th jump scene; according to step 102, at this time, the second RAM is occupied by clock ferrule status information updates; at this point, the clock collar status information in the third RAM may be determined as the second operation result.
After a second operation result is determined, adding tokens into the token bucket according to a third preset rule; the third preset rule is used for determining a rule for adding tokens into the token bucket according to the clock ferrule state information; the token adding amount can be determined by filling the token bucket or according to the product of the token adding speed and the interval time difference between the previous data packet and the next data packet; here, the time length of each sub-period can be determined according to the relation between the time length of each sub-period and the time length of the full token bucket, the state indicated by the set clock ferrule state information, and the like; as the above 4 sub-period durations are all greater than the full token bucket adding duration, the full overflow state determined by the two 1/4 hopping scenarios can be ensured, and the token bucket can be filled if the two packet arrival time intervals are certainly greater than the full token bucket adding duration;
specifically, if the second operation result is full overflow, the token bucket is filled; otherwise, the time interval between the arrival of the two data packets before and after the arrival of the two data packets cannot be completely ensured to be longer than the time length of adding the full token bucket; accordingly, a time difference between a current packet and a last packet may be determined, and a product of the determined time difference multiplied by a preset token addition speed is determined as the number of tokens added to the token bucket. Here, the time difference between the current packet and the last packet may be determined by using the existing technology, recording the arrival global time when each packet arrives, and keeping in a preset memory or buffer, and when the time difference needs to be calculated, taking out the time values of the two previous and next packets and subtracting to obtain the time difference.
Further, if the second operation is performed on the first RAM or the second RAM, after the second operation result is obtained, the clock ferrule state information in the first RAM or the second RAM on which the second operation is performed is set to be in an initial state; if the first RAM and the second RAM are subjected to second operation, after a second operation result is obtained, setting the state information of the clock ferrules in the first RAM and the second RAM, which are subjected to the second operation, to be an initial state;
specifically, if the arrival time point of the data packet is within each sub-period, the clock loop status information of the first RAM and the second RAM may be set to 00 after determining the second operation result; if the arrival time of the data packet is in a scene that the high 2 bits of the clock counter are changed from 00 to 01 or 01 is changed to 10, namely a 1 st 1/4 jump scene and a 2 nd jump scene, the data packet is the second RAM in the second operation object, and therefore, the clock ferrule state information of the second RAM can be set to 00; if the arrival time of the data packet is in the first RAM at the scene that the high 2 bits of the clock counter are changed from 10 to 11 or 11 to 00, namely the 3 rd 1/4 jump scene and the 4 th jump scene, at this time, the data packet is the second operation object, therefore, the clock ring status information of the first RAM can be set to 00.
By adopting the method provided by the embodiment of the invention, two RAMs are alternately used, and when one RAM is occupied by updating the clock ferrule state information, the other RAM is used for providing the clock ferrule state information added by the token of the token bucket; the two RAMs respectively record the clock ring state information of two adjacent 1/4 hopping scenes, the interval duration of the two adjacent 1/4 hopping scenes is larger than the full duration of the token bucket, and the clock ring state information can be accurately provided.
The embodiment of the invention provides an information processing device, which comprises a memory, a processor and an executable program, wherein the executable program is stored on the memory and can be run by the processor; the information processing device also comprises two RAMs for storing the state information of the clock ferrule; when the processor runs the executable program, executing the step of operating the RAM in the token adding method;
the token adding method, as shown in fig. 1, includes:
step 101: presetting two RAMs, namely a first RAM and a second RAM, and performing second operation on one RAM in the two RAMs when performing first operation on the other RAM;
here, the first operation is updating clock loop state information in the RAM, and the second operation is reading the clock loop state information in the RAM for calculating the number of tokens added to the token bucket; setting of the RAM can be carried out in the network flow monitoring device; wherein the clock ferrule state information may include: initial state, half overflow and full overflow, the three clock ferrule state information can be represented in RAM by 00, 01 and 10 respectively, and can also be represented by other self-defined modes; the initial state, the half overflow and the full overflow can be used for recording the mark of the clock timer crossing the sub-period so as to be used as the basis for continuously adding the token;
two RAMs, namely a first RAM and a second RAM, can be arranged in the network flow monitoring device for recording the ferrule condition, and two RAMs of 1w1r can be respectively used as the first RAM and the second RAM; here, the first and second electrodes; the first RAM and the second RAM may be configured to: one of the RAMs is occupied with clock loop state information updates, and the other RAM provides the clock loop state information needed for current token additions.
Further, the clock period may be divided into 4 equal sub-periods of the first sub-period, the second sub-period, the third sub-period, and the fourth sub-period in the network traffic policing device; the clock cycle can be a clock cycle used for recording the arrival time of two successive data packets, and a clock counter can realize the clock cycle counting function; the clock period can be divided into more than 1 sub-period, and similar to recording clock ferrule state information when a clock counter appears in a ferrule in the prior art, the clock ferrule state information can be recorded in the RAM when one sub-period is finished; the first sub-period, the second sub-period, the third sub-period and the fourth sub-period may be 4 periods sequentially arranged in one clock period; the duration of each sub-period is greater than the full duration of the token bucket; the token bucket full time length refers to a time length from adding tokens to an empty token bucket at a predetermined token adding rate until the token bucket is full.
Step 102: performing first operation on the first RAM or the second RAM according to a first preset rule;
here, the first preset rule is a rule for updating the state information of the clock loop to the RAM, and may be determined according to the number of sub-cycles in the one clock cycle and a relationship between the sub-cycles and the token bucket full-time.
Further, the clock cycle may be divided into 4 sub-cycles with equal cycles, and the duration of each sub-cycle is greater than the token bucket full duration; in this case, the first preset rule may be: when the first sub-period and the second sub-period are finished, performing first operation on the first RAM; when the third sub-period and the fourth sub-period are finished, performing first operation on the second RAM;
specifically, the clock period is usually counted by a clock period clock counter, and the high 2 bits of the clock counter can reflect the condition of 4 sub-periods, for example, when the high 2 bits 00 jump to 01, the first sub-period ends, when the high 2 bits 01 jump to 10, the second sub-period ends, when the high 2 bits 10 jump to 11, the third sub-period ends, and when the high 2 bits 11 jump to 00, the fourth sub-period ends; here, the zero-crossing self-refresh scenario may be determined in a scenario where the high 2 bits 00 of the clock counter jump to 01, 01 jumps to 10, 10 jumps to 11, and 11 jumps to 00; performing first operation on the first RAM or the second RAM in a zero-crossing self-refresh scene; meanwhile, 00 hops 01 are determined as the 1 st 1/4 hopping scene, 01 hops 10 are determined as the 2 nd 1/4 hopping scene, 10 hops 11 are determined as the 3 rd 1/4 hopping scene, and 11 hops 00 are determined as the 4 th 1/4 hopping scene; in the 4 jumping scenes, updating the state information of the clock loop for each service flow; the number of service flows determines the time length for completing the updating of the state information of all clock ferrules, namely the time length of a hopping scene, for example, according to the prior art, 32K read-write cycles are required for updating the state information of the clock ferrules of 16K service flows.
At the end of the first sub-period, i.e. in the 1 st 1/4 jump scenario, performing a first operation on the first RAM, including: if the clock ferrule state information in the first RAM is in an initial state, setting the clock ferrule state information to be half-overflow; if the clock ferrule state information in the first RAM is full overflow, keeping the current clock ferrule state information in the first RAM; here, a half-overflow condition may indicate that the clock counter has experienced an 1/4 transition scenario, but cannot determine whether the clock counter has walked longer than 1 sub-cycle; the full overflow state represents that the clock counter has undergone 1/4 hopping scenes at least twice, and the two hopping scenes can ensure that the time length of the clock counter is greater than or equal to the sub-period, and the time length of the sub-period is greater than the time length of the full token bucket; therefore, the initial state, the half overflow state and the full overflow state can be used as the basis for continuously adding tokens;
specifically, when the current clock count has the 1 st 1/4 jump scene, the first RAM performs zero-crossing updating; here, 00, 01, and 10 are used in RAM to indicate clock-loop status information, respectively: initial state, half-spill and full-spill said three clock ferrule state information; in the 1 st 1/4 jump scenario, only 00 and 10 states exist for the first RAM, since the last first RAM update process has only two possibilities: the arrival of the data packet is updated to 00, or 10/00 keeps under the 2 nd 1/4 jump scene, or 01 jump is changed to 10; thus, at this time, the refresh of the first RAM is: if the clock ferrule state information in the first RAM is 00, rewriting to 01, otherwise, keeping 10;
and when the second sub-period is finished, performing a first operation on the first RAM, wherein the first operation comprises: if the clock ferrule state information in the first RAM is half-overflow, setting the clock ferrule state information to be full-overflow, otherwise, keeping the clock ferrule state information in the first RAM;
specifically, when the current clock count has the 2 nd 1/4 jump scenario, the first RAM performs zero-crossing update, and at this time, the state information of the clock loop in the first RAM may have three situations: when the arrival of the data packet is updated to 00, the 00 jumps to 01 when the 1 st 1/4 jumps, or the 10 keeps when the 1 st 1/4 jumps; at this time, the refresh of the first RAM is: if the clock-ring status information in the first RAM is 01, indicating that no packet arrived in this 1/4 cycles, the half overflow indicated by 01 needs to be rewritten to 10 indicating a full overflow; if the clock collar status information 10 or 00 in the first RAM remains unchanged.
At the end of the third sub-period, performing a first operation on the second RAM, including: if the clock ferrule state information in the second RAM is in the initial state, setting the clock ferrule state information to be half-overflow; if the clock ferrule state information in the second RAM is full overflow, keeping the current clock ferrule state information in the second RAM;
specifically, when the current clock count has the 3 rd 1/4 jump scene, the second RAM performs zero-crossing updating; in the 3 rd 1/4 jump scenario, only 00 and 10 states exist for the second RAM, since the last second RAM update process has only two possibilities: the arrival of the data packet is updated to 00, or 10/00 keeps under the 4 th 1/4 jump scene, or 01 jumps to 10; thus, at this time, the refresh to the second RAM is: if the clock collar status information in the second RAM is 00, then the rewrite is 01, otherwise, 10 is maintained.
At the end of the fourth sub-period, performing a first operation on the second RAM, including: if the clock ferrule state information in the second RAM is half-overflow, setting the clock ferrule state information to be full-overflow, otherwise, keeping the current clock ferrule state information in the second RAM;
specifically, when the 4 th 1/4 jump scenario occurs in the current clock count, the second RAM performs zero-crossing update, and at this time, the state information of the clock loop in the second RAM may have three situations: when the arrival of the data packet is updated to 00, the 00 jumps to 01 when the 3 rd 1/4 jumps, or the 10 keeps when the 3 rd 1/4 jumps; at this time, the refresh of the second RAM is: if the clock-ring status information in the second RAM is 01, indicating that no data packet arrives in 1/4 cycles, the half-overflow indicated by 01 needs to be rewritten to 10 to indicate a full overflow; if the clock collar status information in the second RAM is 10 or 00, it remains unchanged.
Step 103: when the data packet arrives, performing second operation on the first RAM and/or the second RAM according to a second preset rule, and adding tokens into the token bucket according to a third preset rule according to a second operation result;
here, the second preset rule is a rule for reading the clock loop status information from the RAM, and may be determined according to the condition that the clock loop status information is updated in the RAM in the first preset rule; adding tokens to the token bucket is controlled based on determining a second operation result from the clock collar state information in the second RAM, such as when the first RAM performs a clock collar state information update.
Further, the second preset rule may be that when the arrival time point of the packet is within each sub-period, the first RAM and the second RAM are subjected to a second operation; when the clock ferrule state information read by the second operation in the first RAM and the second RAM is full overflow, determining a second operation result as full overflow; when the arrival time point of the data packet is in the first operation process after the first sub-period is finished or the first operation process after the second sub-period is finished, performing second operation on the second RAM; determining the clock ferrule state information in the second RAM read by the second operation as a second operation result; when the arrival time point of the data packet is in a third operation process after the third sub-period is finished or a first operation process after the fourth sub-period is finished, performing a second operation on the first RAM; determining the clock ferrule state information in the first RAM read by the second operation as a second operation result;
specifically, if the arrival time of the data packet is in each sub-period, that is, when the data packet is not in a scene where the high 2 bits of the clock counter jump from 00 to 01, or the 01 jump to 10, or the 10 jump to 11, or the 11 jump to 00, the state information of the clock ferrules in the first RAM and the second RAM can be read, and the result of the second operation is determined by combining the state information of the clock ferrules in the two RAMs; in a scene that the arrival time of the data packet is in each sub-period, when the state information of the clock ferrules in the first RAM and the second RAM is full overflow, determining a second operation result as full overflow; when the clock ferrule state information in the first RAM and the second RAM is not all full overflow, determining the second operation result as non-full overflow;
if the arrival time of the data packet is in a scene that the high 2 bits of the clock counter jump from 00 to 01 or 01 jumps to 10, namely a 1 st 1/4 jump scene and a 2 nd jump scene; according to step 102, at this time, the first RAM is occupied by clock ferrule status information updates; at this time, the clock collar status information in the second RAM may be determined as a second operation result;
if the arrival time of the data packet is in a scene that the high 2 bits of the clock counter are changed from 10 to 11 or 11 to 00, namely a 3 rd 1/4 jump scene and a 4 th jump scene; according to step 102, at this time, the second RAM is occupied by clock ferrule status information updates; at this point, the clock collar status information in the third RAM may be determined as the second operation result.
After a second operation result is determined, adding tokens into the token bucket according to a third preset rule; the third preset rule is used for determining a rule for adding tokens into the token bucket according to the clock ferrule state information; the token adding amount can be determined by filling the token bucket or according to the product of the token adding speed and the interval time difference between the previous data packet and the next data packet; here, the time length of each sub-period can be determined according to the relation between the time length of each sub-period and the time length of the full token bucket, the state indicated by the set clock ferrule state information, and the like; as the above 4 sub-period durations are all greater than the full token bucket adding duration, the full overflow state determined by the two 1/4 hopping scenarios can be ensured, and the token bucket can be filled if the two packet arrival time intervals are certainly greater than the full token bucket adding duration;
specifically, if the second operation result is full overflow, the token bucket is filled; otherwise, the time interval between the arrival of the two data packets before and after the arrival of the two data packets cannot be completely ensured to be longer than the time length of adding the full token bucket; accordingly, a time difference between a current packet and a last packet may be determined, and a product of the determined time difference multiplied by a preset token addition speed is determined as the number of tokens added to the token bucket. Here, the time difference between the current packet and the last packet may be determined by using the existing technology, recording the arrival global time when each packet arrives, and keeping in a preset memory or buffer, and when the time difference needs to be calculated, taking out the time values of the two previous and next packets and subtracting to obtain the time difference.
Further, if the second operation is performed on the first RAM or the second RAM, after the second operation result is obtained, the clock ferrule state information in the first RAM or the second RAM on which the second operation is performed is set to be in an initial state; if the first RAM and the second RAM are subjected to second operation, after a second operation result is obtained, setting the state information of the clock ferrules in the first RAM and the second RAM, which are subjected to the second operation, to be an initial state;
specifically, if the arrival time point of the data packet is within each sub-period, the clock loop status information of the first RAM and the second RAM may be set to 00 after determining the second operation result; if the arrival time of the data packet is in a scene that the high 2 bits of the clock counter are changed from 00 to 01 or 01 is changed to 10, namely a 1 st 1/4 jump scene and a 2 nd jump scene, the data packet is the second RAM in the second operation object, and therefore, the clock ferrule state information of the second RAM can be set to 00; if the arrival time of the data packet is in the first RAM at the scene that the high 2 bits of the clock counter are changed from 10 to 11 or 11 to 00, namely the 3 rd 1/4 jump scene and the 4 th jump scene, at this time, the data packet is the second operation object, therefore, the clock ring status information of the first RAM can be set to 00.
By adopting the method provided by the embodiment of the invention, two RAMs are alternately used, and when one RAM is occupied by updating the clock ferrule state information, the other RAM is used for providing the clock ferrule state information added by the token of the token bucket; the two RAMs respectively record the clock ring state information of two adjacent 1/4 hopping scenes, the interval duration of the two adjacent 1/4 hopping scenes is larger than the full duration of the token bucket, and the clock ring state information can be accurately provided.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the scope of the present invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (16)

1. A token adding method is characterized in that two RAMs, namely a first RAM and a second RAM, are preset, and when one RAM in the two RAMs is subjected to first operation, the other RAM is subjected to second operation; the method further comprises the following steps:
performing first operation on the first RAM or the second RAM according to a first preset rule;
when the data packet arrives, performing second operation on the first RAM and/or the second RAM according to a second preset rule, and adding tokens into the token bucket according to a third preset rule according to a second operation result;
the method further comprises the following steps: dividing a clock period into more than 1 sub-period, and performing a first operation when each sub-period is finished; the duration of each sub-period is greater than the token bucket full duration;
the first operation is updating the state information of the clock ferrule in the RAM, and the second operation is reading the state information of the clock ferrule in the RAM; the first preset rule is a rule for updating clock loop state information of the RAM, and the clock loop state information is used for recording a mark of a clock timer crossing a sub-period; the second preset rule is a rule for reading clock ferrule state information from the RAM, and the third preset rule is a rule for determining to add tokens to the token bucket according to the clock ferrule state information.
2. The method of claim 1, wherein the dividing the clock cycle into more than 1 sub-cycle, and wherein performing the first operation at the end of each sub-cycle comprises: dividing a clock cycle into four sub-cycles with equal duration, namely a first sub-cycle, a second sub-cycle, a third sub-cycle and a fourth sub-cycle, and performing a first operation when each sub-cycle is finished;
the clock ferrule state information includes: initial state, half overflow and full overflow.
3. The method according to claim 2, wherein the performing the first operation on the first RAM or the second RAM according to the first preset rule comprises:
when the first sub-period and the second sub-period are finished, performing first operation on the first RAM;
and performing the first operation on the second RAM at the end of the third sub-period and the fourth sub-period.
4. The method of claim 3,
at the end of the first sub-period, performing a first operation on the first RAM, including: if the clock ferrule state information in the first RAM is in an initial state, setting the clock ferrule state information to be half-overflow; if the clock ferrule state information in the first RAM is full overflow, keeping the current clock ferrule state information in the first RAM;
and when the second sub-period is finished, performing a first operation on the first RAM, wherein the first operation comprises: if the clock ferrule state information in the first RAM is half-overflow, setting the clock ferrule state information to be full-overflow, otherwise, keeping the clock ferrule state information in the first RAM;
at the end of the third sub-period, performing a first operation on the second RAM, including: if the clock ferrule state information in the second RAM is in the initial state, setting the clock ferrule state information to be half-overflow; if the clock ferrule state information in the second RAM is full overflow, keeping the current clock ferrule state information in the second RAM;
at the end of the fourth sub-period, performing a first operation on the second RAM, including: and if the clock ferrule state information in the second RAM is half-overflow, setting the clock ferrule state information to be full-overflow, and otherwise, keeping the current clock ferrule state information in the second RAM.
5. The method according to claim 2, wherein performing the second operation on the first RAM and/or the second RAM according to the second preset rule comprises:
when the arrival time point of the data packet is in each sub-period, performing second operation on the first RAM and the second RAM; when the clock ferrule state information read by the second operation in the first RAM and the second RAM is full overflow, determining a second operation result as full overflow;
when the arrival time point of the data packet is in the first operation process after the first sub-period is finished or the first operation process after the second sub-period is finished, performing second operation on the second RAM; determining the clock ferrule state information in the second RAM read by the second operation as a second operation result;
when the arrival time point of the data packet is in the first operation process after the third sub-period is finished or the first operation process after the fourth sub-period is finished, performing second operation on the first RAM; and determining the clock ferrule state information read by the second operation in the first RAM as a second operation result.
6. The method of claim 5, wherein adding tokens to the token bucket according to a third preset rule based on the second operation result comprises:
if the second operation result is full overflow, filling the token bucket; otherwise, determining the time difference between the current data packet and the last data packet, and determining the product of the determined time difference and the preset token adding speed as the number of tokens added to the token bucket.
7. The method according to any one of claims 1 to 6, further comprising:
if the first RAM or the second RAM is subjected to second operation, after the second operation result is obtained, setting the state information of the clock ferrule in the first RAM or the second RAM subjected to the second operation to be in an initial state;
and if the first RAM and the second RAM are subjected to second operation, setting the state information of the clock ferrules in the first RAM and the second RAM subjected to the second operation to be in an initial state after the second operation result is obtained.
8. A token adding apparatus, the apparatus comprising: the device comprises a setting module, a first operation module and a second operation module; wherein:
the setting module: the method comprises the steps that two RAMs, namely a first RAM and a second RAM are preset, and when one RAM in the two RAMs is subjected to first operation, the other RAM is subjected to second operation;
the first operation module is used for performing first operation on the first RAM or the second RAM according to a first preset rule;
the second operation module is used for performing second operation on the first RAM and/or the second RAM according to a second preset rule when a data packet arrives, and adding tokens into the token bucket according to a third preset rule according to a second operation result;
the setting module is further configured to: dividing a clock period into more than 1 sub-period, and performing a first operation when each sub-period is finished; the duration of each sub-period is greater than the token bucket full duration;
the first operation is updating the state information of the clock ferrule in the RAM, and the second operation is reading the state information of the clock ferrule in the RAM; the first preset rule is a rule for updating clock loop state information of the RAM, and the clock loop state information is used for recording a mark of a clock timer crossing a sub-period; the second preset rule is a rule for reading clock ferrule state information from the RAM, and the third preset rule is a rule for determining to add tokens to the token bucket according to the clock ferrule state information.
9. The apparatus according to claim 8, wherein the setting module is specifically configured to:
dividing a clock cycle into four sub-cycles with equal duration, namely a first sub-cycle, a second sub-cycle, a third sub-cycle and a fourth sub-cycle, and performing a first operation when each sub-cycle is finished;
the clock ferrule state information includes: initial state, half overflow and full overflow.
10. The apparatus of claim 9, wherein the first operating module is specifically configured to:
when the first sub-period and the second sub-period are finished, performing first operation on the first RAM;
and performing the first operation on the second RAM at the end of the third sub-period and the fourth sub-period.
11. The apparatus according to claim 10, wherein the first operating module is specifically configured to:
when the first sub-period is finished, if the clock ferrule state information in the first RAM is in an initial state, setting the clock ferrule state information to be half-overflow; if the clock ferrule state information in the first RAM is full overflow, keeping the current clock ferrule state information in the first RAM;
when the second sub-period is over, if the state information of the clock ferrule in the first RAM is half-overflow, setting the state information of the clock ferrule to be full-overflow, otherwise, keeping the state information of the clock ferrule in the first RAM;
when the third sub-period is finished, if the clock ferrule state information in the second RAM is in an initial state, setting the clock ferrule state information to be half-overflow; if the clock ferrule state information in the second RAM is full overflow, keeping the current clock ferrule state information in the second RAM;
and when the fourth sub-period is finished, if the clock ferrule state information in the second RAM is half-overflow, setting the clock ferrule state information to be full-overflow, and otherwise, keeping the current clock ferrule state information in the second RAM.
12. The apparatus according to claim 9, wherein the second operating module is specifically configured to:
when the arrival time point of the data packet is in each sub-period, performing second operation on the first RAM and the second RAM, and when the clock ferrule state information read by the second operation in the first RAM and the second RAM is full overflow, determining a second operation result as full overflow;
when the arrival time point of the data packet is in the first operation process after the first sub-period is finished or the first operation process after the second sub-period is finished, performing second operation on the second RAM; determining the clock ferrule state information in the second RAM read by the second operation as a second operation result;
when the arrival time point of the data packet is in the first operation process after the third sub-period is finished or the first operation process after the fourth sub-period is finished, performing second operation on the first RAM; and determining the clock ferrule state information read by the second operation in the first RAM as a second operation result.
13. The apparatus according to claim 12, wherein the second operating module is specifically configured to:
if the second operation result is full overflow, filling the token bucket; otherwise, determining the time difference between the current data packet and the last data packet, and determining the product of the determined time difference and the preset token adding speed as the number of tokens added to the token bucket.
14. The apparatus of any one of claims 8 to 13, wherein the second operating module is further configured to:
if the first RAM or the second RAM is subjected to second operation, after the second operation result is obtained, setting the state information of the clock ferrule in the first RAM or the second RAM subjected to the second operation to be in an initial state;
and if the first RAM and the second RAM are subjected to second operation, setting the state information of the clock ferrules in the first RAM and the second RAM subjected to the second operation to be in an initial state after the second operation result is obtained.
15. A storage medium having stored thereon an executable program, characterized in that the executable program, when executed by a processor, implements the method according to any one of claims 1 to 7.
16. An information processing apparatus comprising a memory, a processor and an executable program stored on the memory and capable of being executed by the processor, characterized in that the apparatus further comprises two RAMs for storing clock ferrule state information; the processor, when running the executable program, performs the method of any of claims 1 to 7.
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