CN109033480A - Domain and chip - Google Patents
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- CN109033480A CN109033480A CN201710426455.3A CN201710426455A CN109033480A CN 109033480 A CN109033480 A CN 109033480A CN 201710426455 A CN201710426455 A CN 201710426455A CN 109033480 A CN109033480 A CN 109033480A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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Abstract
A kind of domain and chip, domain include multiple gate array stand-by units, and each gate array stand-by unit includes at least a pair of pmos transistor and nmos transistor；Between the different gate array stand-by units, the active area of the pmos transistor is mutually independent, and the active area of the nmos transistor is mutually independent.Domain of the invention can only modify the connection type of the gate array stand-by unit metal layer, can be transformed into any functional unit, not limited by placement position, save the time, improve efficiency.
Description
Technical field
The present invention relates to integrated circuit (IC) more particularly to a kind of domains and chip.
Background technique
Modern IC designs are fast-developing, and complexity is also continuously improved, whenever change in the work instructs (engineering
change order；When ECO), low cost and short time are increasingly required.Existing way is after design, remaining empty
Between put some standard blocks (standard cell), the input of standard block terminate to input voltage (vdd) or ground connection
(gnd) it prevents from leaking electricity.But such way is often limited to the type and distributing position of standard block.Many times need
Standard block is placed on distant location, and when ECO will cause the difficulty of line, or even cause the violation of a succession of timing
(timing violation).Existing modification can only manual modification.And it does not have temporal model (timing model) to retouch
Timing (timing) situation of this unit (cell) is stated, so the domain that last modification comes out can not accurately estimate timing mould
Type.
Summary of the invention
Technical problem to be solved by the present invention lies in, overcome problems of the prior art, provide a kind of domain and
Chip can only modify the connection type of the gate array stand-by unit metal layer, can be transformed into any functional unit, not by
The limitation of placement position.
The present invention provides a kind of domain, including multiple gate array stand-by units, and each gate array stand-by unit includes
At least a pair of pmos transistor and nmos transistor；Between the different gate array stand-by units, the pmos transistor
Active area it is mutually independent, the active area of the nmos transistor is mutually independent.
Further, in the domain, at least partly described gate array stand-by unit passes through one or more layers metal layer
Different connections, to form different functional units.
Further, in the domain, the gate array stand-by unit is connected by the different of first layer metal layer, with
Form different functional units.
Further, in the domain, the multiple adjacent or non-adjacent gate array stand-by unit by one layer or
The same connection of more metal layers forms a functional unit；Or/and a gate array stand-by unit passes through one layer or more
The same connection of layer metal layer, forms a functional unit.
Further, in the domain, when not in use, the gate array stand-by unit passes through one or more layers metal
Layer connects into capacitor, or does not do the connection of metal layer.
Further, in the domain, in a gate array stand-by unit, the pmos transistor is located at one
Row, the nmos transistor are located at another row；And/or in a gate array stand-by unit, including 2 pairs or more
Pmos transistor and nmos transistor, the adjacent pmos transistor share same active area, the adjacent nmos crystal
Pipe shares same active area.
Further, in the domain, the pmos transistor in at least partly described gate array stand-by unit and
The number of nmos transistor is identical；And/or the pmos transistor and nmos in at least partly described gate array stand-by unit
The number of transistor is different.
Further, in the domain, multiple gate array stand-by units be arranged in it is multiple rows of, every row have multiple institutes
State gate array stand-by unit；And/or all pmos transistors and nmos transistor are all fixed dimensions.
Further, in the domain, the domain further includes being mostly used spare standard block, and the gate array is spare
Unit and the interspersed arrangement of the standard block；And/or each gate array stand-by unit include two pairs of pmos transistors and
Nmos transistor or four pairs of pmos transistors and nmos transistor.
Another side according to the present invention provides a kind of chip, is prepared according to domain described in any one as above.
The present invention provides a kind of domain, including multiple gate array stand-by units, and each gate array stand-by unit includes
At least a pair of pmos transistor and nmos transistor；Between the different gate array stand-by units, the pmos transistor
Active area it is mutually independent, the active area of the nmos transistor is mutually independent.When the domain is modified, can by one or
Multiple adjacent preset gate array stand-by units replace with the functional unit, it is thus only necessary to change metal layer
Connection type may be implemented to replace automatically.Being not only restricted to early stage is laid out, can be with arbitrary placement, and when use can change into any
Different functional units is saved the time, is improved efficiency.
Detailed description of the invention
The following describes the present invention in detail with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the schematic diagram for indicating gate array standard block according to an embodiment of the invention.
Fig. 2 is the schematic diagram for indicating gate array stand-by unit arrangement according to an embodiment of the invention.
Fig. 3 indicates according to an embodiment of the invention and gate array stand-by unit is replaced with gate array standard block
Schematic diagram.
Fig. 4 is to indicate the different connection types in accordance with another embodiment of the present invention by metal layer, described in one
Gate array stand-by unit forms different functional units.
Fig. 5 is to indicate the different connection types in accordance with another embodiment of the present invention by metal layer, will be multiple described
Gate array stand-by unit forms different functional units.
Fig. 6 is when indicating PR according to an embodiment of the invention (place and route, placement-and-routing) with the machine transplanting of rice
The gate array stand-by unit entered.
Fig. 7 is the flow diagram for indicating design method according to an embodiment of the invention.
Specific embodiment
In order to be easy to understand the technical means, the creative features, the aims and the efficiencies achieved by the present invention, tie below
Conjunction is specifically illustrating, and the present invention is further explained.
In order to realize low cost and the short time of ECO, a kind of method is to put one in remaining space after layout-design
A little standard blocks (standard cell), and the structure of the standard block and position be it is fixed, generally multiple grids are put
In a row, in each row, the active area between grid is shared.These functional units for modifying out have very much first
Limit, cannot be modified as the higher unit of complexity or can only manual modification, in addition manual line, needs the plenty of time, efficiency
It is beneath.Secondly it needs not necessarily to have required amount of Gate arrangement around the region modified, is not enough barricaded as required unit.Because
Different grids adds different functional unit situations very more, so can not provide too many kind of feelings in the library that wafer factory provides
Condition, it is most of still to want client's manual modification.The timing condition that it does not have temporal model to describe this unit again, so finally
The domain that modification comes out can not accurately estimate temporal model.
Proposed by the present invention is that a kind of modular gate array stand-by unit with timing is arranged in domain, be can be set
With the matched gate array standard cell lib of the gate array stand-by unit, when the gate array stand-by unit in domain with
In the case that machine is distributed, the level in domain more than metal layer can be only modified, by modifying network mark, utilizes EDA (Electronic Design
Automation, Electronics Design Automation) tool replaces and is laid out automatically.The gate array standard cell lib
In functional unit can replace the gate array stand-by unit in domain, and in the gate array standard cell lib include function
The accurate control sequential of tool or driving capability of EDA can be used in the temporal model of unit.
Gate array standard cell lib of the invention is using gate array standard block as basic unit, the gate array standard block
Library includes multiple gate array standard blocks, and Fig. 1 is to indicate showing for gate array standard block according to an embodiment of the invention
It is intended to.In one embodiment, each gate array standard block 100 includes two pairs of pmos transistors and nmos transistor,
And metal layer.As shown in Figure 1, the gate array standard block 100 includes pmos transistor area 110 and nmos transistor
120, the pmos transistor area 110 includes two grids 111 and active area 112, to form two pmos transistors；Institute
Stating nmos transistor area 120 includes two grids 121 and active area 122, to form two nmos transistors.
The grid 111 and active area 112 of two pmos transistors are arranged in a row, 121 He of grid of two nmos transistors
Active area 122 lines up another row, and the pmos transistor is located at a row, and the nmos transistor is located at another row.In an institute
It states in gate array standard block, the adjacent pmos transistor shares same active area 112, the adjacent nmos transistor
Share same active area 122.It will be understood by those skilled in the art that the active area 112 includes source electrode and drain electrode,
This is not repeated them here.Between the different gate array standard blocks, the active area of the pmos transistor is mutually indepedent, described
The active area of nmos transistor is mutually indepedent, i.e., between the different gate array standard blocks, active area is mutually not connected to.
In Fig. 1, the metal layer 130 is the first metal layer, and in other embodiments, the metal layer 130 can be with
For one layer or several layers of of combination in the first metal layer, second metal layer, third metal layer etc..Wherein, multiple gate arrays
Stand-by unit 100 forms different functional units by the different connections of one or more layers metal layer；An or gate array
Stand-by unit 100 forms different functional units by the different connections of one or more layers metal layer.The i.e. described functional unit can
It connects to be formed with the metal layer by one or more gate array stand-by units 100, to realize different functions.
Specifically, the modification of domain can be carried out in chip designing system.For example, the chip designing system can be
Various eda tools.The gate array standard cell lib, and the chip design department can be imported in the chip designing system
There is domain in system.
In the design layout of domain, it is standby that gate array corresponding with the gate array stand-by unit 100 is set in domain
Use unit.As shown in Fig. 2, GA2 is a gate array stand-by unit, the gate array stand-by unit GA2 and the gate array mark
The structure of the transistor part of quasi- unit 100 is identical, in each gate array stand-by unit GA2 pmos transistor and
Pmos transistor and nmos crystal in structure, quantity and the arrangement mode of nmos transistor and the gate array standard block 100
The structure of pipe, quantity and arrangement mode are all the same.That is, the gate array stand-by unit GA2 and the gate array standard block 100
It is identical with the design structure of grid layer in substrate layer, only in metal layer and with the possible difference of the design structure on upper layer.
In the domain, multiple gate array stand-by unit GA2 are arranged in an at least row, and every row includes multiple described
Gate array stand-by unit.For example, in the first row, a gate array stand-by unit GA2 is arranged in a row in Fig. 2；?
In second row, two gate array stand-by unit GA2 are arranged in a row, and form a GA4；In third row, described in three
Gate array stand-by unit GA2 is arranged in a row, and forms a GA6；In the 4th row, four gate array stand-by unit GA2
It is arranged in a row, forms GA8, etc., so that every row, which is used for spare unit modules, turns at least one described door
Array stand-by unit facilitates replacement.
In other embodiments, the quantity of the pmos transistor in the gate array stand-by unit and nmos transistor may be used also
Think 3 pairs, 4 pairs, 5 pairs etc..The gate array stand-by unit is connected into capacitor when not in use, can not also connect.The door
Cabling space as much as possible has been stayed inside array stand-by unit, can be convenient be modified as other functional units in this way.
The gate array stand-by unit is modified as function list different in the gate array standard cell lib in which can be convenient
Member.According to one embodiment of present invention, N number of gate array stand-by unit is made into array (array) and is placed on a row.In this way
Benefit be the function that user can arrange a row array that some described gate array stand-by unit in (array) is substituted for needs
It can unit.Fig. 3 be indicate it is according to an embodiment of the invention the gate array stand-by unit is made into array after replace wherein
The schematic diagram of any one.In Fig. 3, such as the third gate array stand-by units several from left to right replaced with INV1 function
The 7th gate array stand-by unit of number from left to right is replaced with NOR2 functional unit by energy unit.
According to one embodiment of present invention, the gate array standard cell lib is established with standard block (standard
Cell) difference in library is: each pmos transistor and nmos transistor in the gate array standard block are fixed dimensions,
Different logical combinations is realized by the different connections of first layer metal (metal 1), without being modified to other levels.
For example, we can establish gate array with two different methods for more complicated circuits such as triggers
The library (gate array).1, it is assumed that there are enough pmos and nmos transistors in the place for needing to modify.As general circuit, benefit
Different transistors is linked up with first layer metal layer (metal 1), function required for being formed.Based in the gate array
The confined space in stand-by unit, part route may not be able to complete line in the gate array stand-by unit, we just want
It modifies netlist (netlist) and the connector of these lines is done into ECO line to eda tool.2, in the place for needing to increase trigger,
If not having the sufficient gate array stand-by unit in domain to replace, we can be being placed in described in different location
Gate array stand-by unit connects composition trigger.We also need to only modify netlist, then do line by eda tool.But
It is in this way since the load of line (loading) is uncertain, we provide optimal cases (best) and worst condition (worst) two
The temporal model (timing model) of kind situation.
In the gate array standard cell lib, the gate array stand-by unit passes through the connection formation and standard of metal layer
A series of functional units of the inner the same function of unit (standard cell).Fig. 4 indicates that another is implemented according to the present invention
The functional unit of example only listed in some gate array standard cell libs.As shown in figure 4, in another embodiment, the door
Array stand-by unit includes 4 pairs of pmos transistors and nmos transistor, in a gate array standard block, adjacent institute
It states pmos transistor and shares same active area, the adjacent nmos transistor shares same active area.In the different doors
Between array standard block, active area is mutually not connected to.In Fig. 4, pass through the different connection sides of first layer metal layer (metal 1)
One gate array stand-by unit is formed different functional unit: functional unit INV, functional unit NAND2, function by formula
Unit NAND3, functional unit NAND4, functional unit NAND21, functional unit NAND31, functional unit AND2, functional unit
AND3, functional unit BUF, functional unit NOR2, functional unit NOR3, functional unit NOR4, functional unit NOR21, function list
First NOR31, functional unit OR2, functional unit OR3, functional unit AOI21, functional unit AOI211, functional unit OAI21, function
Energy unit OAI211 etc..
Even more complex d type flip flop (D flip flop) also may be implemented.When a gate array standard block not
When enough, multiple gate array standard blocks can be used to combine.Fig. 5 is to indicate according to an embodiment of the invention to incite somebody to action
Multiple gate array stand-by units form functional unit D by the different connection types of metal layer (such as first layer metal layer)
Trigger (D flip flop).As shown in figure 5, DF is simplest d type flip flop (d flip flop), DFS band set signal,
DFR band reset signal, DFSR band set and reset signal.
As shown in figure 5, in another embodiment, the gate array stand-by unit includes 4 pairs of pmos transistors and nmos brilliant
Body pipe, in a gate array standard block, the adjacent pmos transistor shares same active area, and adjacent is described
Nmos transistor shares same active area.Between the different gate array standard blocks, active area is mutually not connected to.
3 gate array stand-by units are connected to form DF functional unit by metal layer, 4 gate arrays are standby
It connects to form DFS functional unit by metal layer with unit, 5 gate array stand-by units is connected to be formed by metal layer
5 gate array stand-by units are connected to form DFSR functional unit by metal layer by DFR functional unit.Scanning element
(scan cell) and other complicated functional units are also similarly.And this multiple described gate array stand-by unit is not necessarily intended to
Together, it can be connected pendulum in random layout.This is equivalent to a modular concept, circuit and layout
(layout) it is divided into module, is put into different positions, then connect by metal layer, forms a functional unit.
According to one embodiment of present invention, the gate array standard cell lib further includes temporal model (timing
Model), the temporal model includes the timing of the functional unit, further include in design method to the temporal model into
Row matching, these temporal models are for eda tool reading.Eda tool can be RC and extract (RC extraction) clock synchronization afterwards in this way
Sequence (timing) has good control.Specifically, the temporal model is placed in ECO module, NAND gate functional unit correspondence is more
The functional unit of a timing: NAND2, NAND3, NAND4 etc., the temporal model be include NAND2, NAND3, NAND4 when
Sequence, when needing the gate array stand-by unit being revised as NAND gate functional unit, eda tool chooses appropriate sequential automatically
NAND gate functional unit, such as choose NAND3.If eda tool is impossible to have timing (timing) without temporal model
Control, it is possible to will cause driving capability deficiency.
In addition in the domain, these described gate array stand-by units are not necessarily intended to be placed on same row, in cell layout
When the gate array stand-by unit as fills unit (filler cell) equally radom insertion in various standard blocks
(standard cell) is intermediate, has no effect on its replacement (replacing with functional unit) and connection when in use.Fig. 6 is to indicate
The gate array stand-by unit of radom insertion when PR according to an embodiment of the invention.As shown in fig. 6, in bold box
It is the gate array stand-by unit being inserted into standard block (standard cell).It can be seen that random position, not
Can have an impact to the combination of logic gate or d type flip flop (d flip flop).
According to one embodiment of present invention, the gate array stand-by unit and gate array standard block is 2 to 4 pairs
Nmos and Pmos.In other embodiments of the invention, if be substituted for other Nmos with Pmos quantity be also as principle.Root
According to one embodiment of the present of invention, connect (cont) layer be it is fixed, only by the 1st layer of metal layer (metal 1) of modification come reality
It is existing.And in other embodiments of the invention, also can be made can modify articulamentum and the above level, or can modify the 2nd gold medal
Belong to layer (metal2) and the above level to realize.
According to one embodiment of present invention, the technique of painting of layout (layout) or domain is improved, in domain
Stand-by unit (for spare unit) module turn to the gate array stand-by unit small one by one, when needing using spare
When unit, the module (i.e. a gate array stand-by unit) that wherein any one is small can be only replaced.And the door
There is the functional unit for realizing preset function, it is only necessary to by one or several gate arrays when needing in array standard cell lib
Column stand-by unit replaces with the functional unit, is not required to user and voluntarily modifies, and replaces flexible and convenient.
In addition, the present invention and having done temporal model (timing model) to the modification of these functional units.When using
There is physical layout supporting paper (lef), has temporal model (timing model), there can be accurate control to timing.
Domain provided by the invention and the gate array stand-by unit, being not only restricted to early stage is laid out, and when use can be convenient
Ground is changed to a variety of different functional units, realizes automatic modification, improves working efficiency.Core can be prepared according to the domain
Piece advantageously reduces the duty cycle, economizes on resources, and improves efficiency.
Fig. 7 is the flow diagram for indicating design method according to an embodiment of the invention.As shown in fig. 7, according to this
One embodiment of invention, design method the following steps are included:
Step S701 provides gate array standard cell lib as described above；
Step S702 provides a domain, and the domain includes multiple gate array stand-by units, and each gate array is spare
The structure of pmos transistor and nmos transistor, quantity and arrangement mode and pmos in the gate array standard block are brilliant in unit
The structure of body pipe and nmos transistor, quantity and arrangement mode are all the same.
Gate array stand-by unit arbitrary placement in the domain.
Each pmos and nmos in the gate array stand-by unit are fixed dimensions.It is connected into capacitor when not in use,
It can not connect.
One or more adjacent gate array stand-by units are replaced with the functional unit by step S703.
It can use metal layer to link up the transistor of the gate array stand-by unit, form functional unit, realize institute
The function of needing.Wherein, the gate array stand-by unit for being placed in different location, which can connect, collectively forms a function
It can unit.
The box-like difference by the 1st metal layer (metal1) of different logical groups connects to realize.
According to one embodiment of present invention, connection (cont) layer is fixed, only passes through the 1st metal layer of modification
(metal1 layers) are realized.And in other embodiments of the invention, also can be made can modify articulamentum and the above level, or
Person can modify the 2nd metal layer (metal2) and the above level to realize.
Wherein, the gate array standard cell lib has done temporal model.The temporal model is for eda tool reading.
The gate array stand-by unit of the invention, can only modify the connection type of metal layer, can be transformed into any
Functional unit or even trigger, the complex units such as scanning element (scan cell).It can not be limited by placement position,
It can be with arbitrary placement.It has built-in temporal model (timing model), and accurate timing can be adjusted to by eda tool
(timing), to meet the demand of ECO.
The basic principles, main features and advantages of the present invention have been shown and described above.The technology of the industry
Personnel only illustrate the present invention it should be appreciated that the present invention is not limited by examples detailed above described in examples detailed above and specification
Principle, various changes and improvements may be made to the invention without departing from the spirit and scope of the present invention, these variation and
Improvement all fall within the protetion scope of the claimed invention.The claimed scope of the invention is by appended claims and its is equal
Object defines.
Claims (10)
1. a kind of domain, which is characterized in that including multiple gate array stand-by units, each gate array stand-by unit includes extremely
Few a pair of pmos transistor and nmos transistor；Between the different gate array stand-by units, the pmos transistor
Active area is mutually independent, and the active area of the nmos transistor is mutually independent.
2. domain as described in claim 1, which is characterized in that at least partly described gate array stand-by unit passes through one layer or more
The different connections of layer metal layer, to form different functional units.
3. domain as claimed in claim 2, which is characterized in that the gate array stand-by unit passes through first layer metal layer not
With connection, to form different functional units.
4. domain as described in claim 1, which is characterized in that the multiple adjacent or non-adjacent gate array stand-by unit is logical
The same connection for crossing one or more layers metal layer forms a functional unit；Or/and a gate array stand-by unit passes through
The same connection of one or more layers metal layer forms a functional unit.
5. the domain as described in any one of Claims 1-4, which is characterized in that when not in use, the gate array is spare
Unit connects into capacitor by one or more layers metal layer, or does not do the connection of metal layer；And/or each gate array is standby
It include two pairs of pmos transistors and nmos transistor or four pairs of pmos transistors and nmos transistor with unit.
6. domain as described in claim 1, which is characterized in that in a gate array stand-by unit, the pmos is brilliant
Body pipe is located at a row, and the nmos transistor is located at another row；And/or in a gate array stand-by unit, including 2
To above pmos transistor and nmos transistor, the adjacent pmos transistor shares same active area, and adjacent is described
Nmos transistor shares same active area.
7. domain as described in claim 1, which is characterized in that the pmos in at least partly described gate array stand-by unit
Transistor is identical with the number of nmos transistor；And/or the pmos crystal in at least partly described gate array stand-by unit
It manages different with the number of nmos transistor.
8. domain as described in claim 1, which is characterized in that multiple gate array stand-by units are arranged in multiple rows of, every row
With multiple gate array stand-by units；And/or all pmos transistors and nmos transistor are all fixed rulers
It is very little.
9. domain as described in claim 1, which is characterized in that the domain further includes multiple spare standard blocks, described
Gate array stand-by unit and the interspersed arrangement of the standard block；And/or multiple gate array stand-by units are arranged at least one
Row, every row includes multiple gate array stand-by units.
10. a kind of chip, which is characterized in that be prepared according to the domain as described in any one of claim 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710426455.3A CN109033480A (en) | 2017-06-08 | 2017-06-08 | Domain and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710426455.3A CN109033480A (en) | 2017-06-08 | 2017-06-08 | Domain and chip |
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| CN109033480A true CN109033480A (en) | 2018-12-18 |
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| CN201710426455.3A Pending CN109033480A (en) | 2017-06-08 | 2017-06-08 | Domain and chip |
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Application publication date: 20181218 |