CN109032833B - Correction method, device, equipment and storage medium for multi-bit error data - Google Patents
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Abstract
The invention is applicable to the technical field of computers and provides a method, a device, equipment and a storage medium for correcting multi-bit error data, wherein the method comprises the following steps: reading target data and diagonal elements associated with the target data from a memory, calculating an inner product matrix and a class inner product matrix of the target matrix, determining whether the read target data is wrong according to the diagonal elements associated with the target data and the inner product matrix of the target data, a first diagonal element and a second diagonal element of the class inner product matrix, determining each possible wrong position in the target data when the read target data is wrong, determining a final wrong position in the possible wrong positions, calculating error deviation amounts corresponding to error data at each final wrong position to perform error correction, and therefore positioning and correcting multi-bit error data in the data read from the memory are achieved, hardware cost for positioning and correcting the multi-bit error data is effectively reduced, and accuracy and efficiency of positioning and correcting the multi-bit error data are improved.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a storage medium for correcting multi-bit error data.
Background
The integrated circuit technology driven by moore's law not only increases the integration density of the memory, but also reduces the working voltage and the node capacitance of the memory, and greatly reduces the critical charge required by node inversion. Alpha particles in the ground environment, neutrons or heavy ions in the radiation environment, protons, which upon impact with the memory surface will generate a large number of electron-hole pairs in a direct or indirect ionization manner, which once collected electron-hole pairs exceed the critical charge of the node, cause a flipping of the node content, causing memory SEU or MBU. In addition to physical defense and circuit-based reinforcement, triple Modular Redundancy (TMR) and Error Correction Code (ECC) techniques are the two most common approaches to the SEU problem of memory.
The triple modular redundancy method can correct each bit error, even one data error, and can obtain correct results, and the triple modular redundancy method is fast and has more added hardware. Error detection and correction code (ECC) techniques include a variety of encoding techniques, with different encoding techniques having different error detection and correction capabilities. For example, parity codes can only detect one bit or an odd number of bits in a codeword, but cannot locate errors and thus cannot correct errors; the hamming code can correct any bit error in one codeword and detect two bit errors. There are also many higher-order ECC encoding algorithms, such as BCH codes, RS codes, etc., that can detect and correct multi-bit errors in one codeword, but the algorithms are complex, the area and delay overhead are also larger, and the higher-order encoding techniques cannot guarantee accurate positioning of the error location when consecutive multi-bit errors like MBU occur.
In addition, current error correction methods are bit-wise positioning and error correction, and for many applications, the data being manipulated is matrix-wise, with many data often being simultaneously corrupted in matrix data, and each erroneous data may in turn be caused by a multi-bit error. In this case, the conventional error correction method cannot cope with multi-bit errors in the same data, and cannot efficiently correct the data in matrix units.
Disclosure of Invention
The invention aims to provide a method, a device, equipment and a storage medium for correcting multi-bit error data, which aim to solve the problems that the multi-bit error in the same data in a memory is difficult to position and correct, the accuracy of positioning and correcting the multi-bit error in the same data in the memory is low, the efficiency is low and the hardware cost is high in the prior art.
In one aspect, the present invention provides a method of correcting multi-bit erroneous data, the method comprising the steps of:
when a data reading instruction is received, reading target data and diagonal elements associated with the target data from a memory, wherein the diagonal elements associated with the target data comprise first diagonal elements and second diagonal elements of an original data inner product matrix and a quasi inner product matrix corresponding to the target data;
calculating an inner product matrix and a class inner product matrix of the target data, and determining whether the read target data is in error or not according to diagonal elements associated with the target data, and first diagonal elements and second diagonal elements of the inner product matrix and the class inner product matrix of the target data;
when the read target data is determined to be in error, determining each possible error position in the target data according to diagonal elements associated with the target data and first diagonal elements of the inner product matrix and the inner product matrix of the target data;
determining a final error position and an error deviation amount corresponding to the final error position in all possible error positions according to diagonal elements associated with the target data and second diagonal elements of the inner product matrix and the inner product matrix of the target data;
and correcting the error data at the final error position in the target data according to the error deviation amount corresponding to the final error position.
In another aspect, the present invention provides a correction apparatus for multi-bit erroneous data, the apparatus comprising:
the data reading unit is used for reading target data and diagonal elements associated with the target data from a memory when a data reading instruction is received, wherein the diagonal elements associated with the target data comprise first diagonal elements and second diagonal elements of an inner product matrix and a similar inner product matrix of original data corresponding to the target data;
the error judging unit is used for calculating an inner product matrix and a class inner product matrix of the target data and determining whether the read target data is in error or not according to diagonal elements associated with the target data, and first diagonal elements and second diagonal elements of the inner product matrix and the class inner product matrix of the target data;
a possible position determining unit, configured to determine, when it is determined that the read target data is in error, each possible error position in the target data according to a diagonal element associated with the target data and a first diagonal element of the inner product matrix and the inner product matrix of the target data;
a final error positioning unit, configured to determine a final error position and an error deviation amount corresponding to the final error position in all the possible error positions according to the diagonal elements associated with the target data and the second diagonal elements of the inner product matrix and the inner product matrix of the target data; and
and the error correction unit is used for correcting the error data at the final error position in the target data according to the error deviation amount corresponding to the final error position.
In another aspect, the present invention also provides a computing device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor implementing the steps described above for the method of correcting multi-bit error data when the computer program is executed.
In another aspect, the present invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of the method for correcting multi-bit error data described above.
According to the invention, target data and diagonal elements associated with the target data are read from a memory, the diagonal elements associated with the target data comprise an original data inner product matrix corresponding to the target data, a first diagonal element and a second diagonal element of an inner product matrix, and according to the diagonal elements associated with the target data, the target data inner product matrix, the first diagonal element and the second diagonal element of the inner product matrix, whether the read target data are in error or not is determined, when the target data are in error, each possible error position in the target data is determined, a final error position is determined at the possible error positions, and error correction is carried out on the target data according to error deviation amounts corresponding to the final error positions, so that the multi-bit error data in the data read from the memory are positioned and corrected, the hardware cost for positioning and correcting the multi-bit error data is reduced, and the accuracy and the efficiency for positioning and correcting the multi-bit error data are improved.
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FIG. 1 is a flow chart of a method for correcting multi-bit error data according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a multi-bit error data correction device according to a second embodiment of the present invention;
FIG. 3 is a schematic diagram of a preferred structure of a multi-bit error data correction device according to a second embodiment of the present invention; and
fig. 4 is a schematic structural diagram of a computing device according to a third embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The following describes in detail the implementation of the present invention in connection with specific embodiments:
embodiment one:
fig. 1 shows a flow of implementation of the method for correcting multi-bit error data according to the first embodiment of the present invention, and for convenience of explanation, only the parts related to the embodiment of the present invention are shown, which is described in detail below:
in step S101, when a data reading instruction is received, target data and diagonal elements associated with the target data are read from a memory, where the diagonal elements associated with the target data include a first diagonal element and a second diagonal element of an inner product matrix and a class inner product matrix of original data corresponding to the target data.
The present invention is applicable to memories from which data specified in instructions are read when a data read instruction of a processor is received, which data is referred to herein as target data for ease of description. And reading target data and simultaneously reading diagonal elements associated with the target data from a memory, wherein the diagonal elements associated with the target data comprise a first diagonal element and a second diagonal element of an inner product matrix of original data and the first diagonal element and the second diagonal element of an inner product matrix of an original data class, and the original data is data stored in the memory by a data storage user, namely storage data corresponding to the target data. Since the read target data may have errors (i.e., the read target data differs from the corresponding original data in the memory), the diagonal elements associated with the target data may be used for locating and correcting the erroneous data in the subsequent target data. The first diagonal line element is a main diagonal line element, and the second diagonal line element is a diagonal line element on the upper side of the main diagonal line.
Preferably, when the data storage instruction is received, data to be stored in the data storage instruction is acquired, an inner product matrix and an inner product-like matrix of the data to be stored are calculated, and when the data to be stored is written into the memory, a first diagonal element and a second diagonal element of the inner product matrix of the data to be stored and the first diagonal element and the second diagonal element of the inner product-like matrix of the data to be stored are written into the memory, so that the calculated amount for positioning and correcting multi-bit error data in the target data is effectively reduced when the target data is read from the memory later.
In step S102, an inner product matrix and an inner product matrix of the target data are calculated, and whether the read target data is in error is determined according to the diagonal elements associated with the target data and the first diagonal element and the second diagonal element of the inner product matrix and the inner product matrix of the target data.
In the embodiment of the invention, an inner product matrix and a class inner product matrix of target data are calculated. Preferably, the inner product matrix calculation formula of the target data is:
C'=X' t * X ', wherein X ' is the read target data, X ' t The transposed matrix of X 'and the inner product matrix of the target data are C';
the calculation formula of the inner product matrix of the class of the target data is as follows:
S'=X'*X' t wherein S' is an inner product matrix of the class of the target data.
In the embodiment of the present invention, the original data corresponding to the target data may be represented as X, and the inner product matrix of the original data may be represented as C, S, respectively, where X is a matrix with m X n size,C=X t *X,S=X*X t . If the multi-bit data in the read target data is wrong, for example, the data at the positions (i, j) and (p, q) are wrong, the inner product matrix of the target data is subtracted from the inner product matrix of the original data, the obtained matrix is zero except the jth row, the jth column, the qth row and the qth column, the data of other rows and columns are zero, the obtained matrix is subtracted from the inner product matrix of the original data, and the obtained matrix is zero except the ith row, the ith column, the p row and the p column, so that whether the target data is wrong or not can be determined according to the inner product matrix of the target data, the inner product matrix of the original data and the inner product matrix of the class, and the possible error position in the target data can be determined.
Preferably, since only the first diagonal element and the second diagonal element of the original data inner product matrix and the first diagonal element and the second diagonal element of the original data inner product matrix are stored in the memory, when judging whether the read target data is wrong, whether the first diagonal element and the second diagonal element of the target data inner product matrix are consistent with the first diagonal element and the second diagonal element of the original data inner product matrix respectively or whether the first diagonal element and the second diagonal element of the target data inner product matrix are consistent with the first diagonal element and the second diagonal element of the original data inner product matrix respectively is compared, and therefore the operation complexity of judging whether the read target data is wrong is effectively reduced.
In step S103, when it is determined that the read target data is erroneous, each possible erroneous position in the target data is determined based on the diagonal element associated with the target data and the first diagonal element of the inner product matrix, the inner product matrix of the target data.
In the embodiment of the invention, after determining that the read target data is in error, the position of the first diagonal element of the inner product matrix of the target data, which is different from the element value in the first diagonal element of the inner product matrix of the original data, can be set as the column coordinate of the possible error position in the target data, the position of the first diagonal element of the inner product matrix of the target data, which is different from the element value in the first diagonal element of the inner product matrix of the original data, can be set as the row coordinate of the possible error position in the target data, and all the possible error positions in the target data can be obtained by combining the column coordinates with the row coordinates one by one.
As an example, when the element values at the (j, j), (q, q) positions in the first diagonal element of the inner product matrix of the target data are different from the element values at the (j, j), (q, q) positions in the first diagonal element of the inner product matrix of the original data, j, q are set as column coordinates of the possible erroneous positions in the target data, and when the element values at the (i, i), (p, p) positions in the first diagonal element of the inner product matrix of the target data class are different from the element values at the (i, i), (p, p) positions in the first diagonal element of the inner product matrix of the original data, i, p are set as row coordinates of the possible erroneous positions in the target data, and these column coordinates are combined with the row coordinates, the possible erroneous positions in the target data are obtained as (i, j), (i, q), (p, j), (p, q).
In step S104, from the diagonal elements associated with the target data and the second diagonal elements of the target data inner product matrix and the class inner product matrix, the final error position and the error deviation amount corresponding to the final error position are determined in all possible error positions.
In the embodiment of the present invention, after all possible error positions in the target data are obtained, a first error deviation amount corresponding to each possible error position is calculated according to the second diagonal element of the inner product matrix of the target data and the second diagonal element of the inner product matrix of the original data, and then a second error deviation amount corresponding to each possible error position is calculated according to the second diagonal element of the inner product matrix of the target matrix class and the second diagonal element of the inner product matrix of the original matrix class, and the possible error position with the value identical to the value of the first error deviation amount and the second error deviation amount in the possible error positions is set as the final error position. Since the first error deviation amount and the second error deviation amount corresponding to the final error position are the same, the first error deviation amount or the second error deviation amount corresponding to the final error position may be set as the error deviation amount of the final error position.
In the embodiment of the present invention, assuming that the possible error positions in the target data are respectively represented as (i, j), (i, q), (p, j), (p, q), preferably, when calculating the first error deviation amount corresponding to each possible error position, calculating the element C 'on the second diagonal element of the inner product matrix of the target data' j(j+1) 、C' q(q+1) Element C on the second diagonal element of the inner product matrix of the original data respectively j(j+1) 、C q(q+1) Is C' j(j+1) And C j(j+1) The calculation formula of the difference value is as follows:
wherein x is ij '=x ij +ΔE ij ,ΔE ij Data x at a potentially erroneous location (i, j) for target data ij ' data x at position (i, j) relative to the original data ij The first error deviation of (2) and thus +.>Similarly, the first error deviation amounts corresponding to the possible error positions (i, q), (p, j), (p, q) of the target data are respectively:
it is also preferable that, in calculating the second error deviation amounts respectively corresponding to each of the possible error positions, the element S 'on the second diagonal element of the inner product matrix of the target class of data is calculated' i(i+1) 、S' p(p+1) Element S on the second diagonal element of the inner product matrix of the original data respectively i(i+1) 、S p(p+1) Is S' j(j+1) And S is equal to j(j+1) The calculation formula of the difference value is as follows:
x ij '=x ij +ΔK ij ,ΔK ij data x at a potentially erroneous location (i, j) for target data ij Data x at' possible error location (i, j) relative to the original data ij A second error deviation of (2) to obtainSimilarly, the second error deviation amounts corresponding to the possible error positions (i, q), (p, j), (p, q) of the target data are respectively:
in step S105, error data at the final error position in the target data is corrected according to the error deviation amount corresponding to the final error position.
In the embodiment of the invention, the error data at the final error position in the target data can be corrected by subtracting the corresponding error deviation amount from the error data at the final error position in the target data.
In the embodiment of the invention, the target data and the diagonal elements associated with the target data are read from the memory, whether the target data is in error or not is determined according to the diagonal elements associated with the target data, the inner product matrix of the target data, the first diagonal elements and the second diagonal elements of the inner product matrix of the target data, and when the target data is in error, each possible error position in the target data is determined, the final error position is determined at the possible error positions, and error data at the final error position is corrected, so that multi-bit error data in the data read from the memory are positioned and corrected, the hardware cost for positioning and correcting the multi-bit error data is reduced, and the accuracy and the efficiency for positioning and correcting the multi-bit error data are improved.
Embodiment two:
fig. 2 shows a structure of a multi-bit error data correction device according to a second embodiment of the present invention, and for convenience of explanation, only a portion related to the embodiment of the present invention is shown, including:
the data reading unit 21 is configured to, when receiving a data reading instruction, read target data and diagonal elements associated with the target data from a memory, where the diagonal elements associated with the target data include a first diagonal element and a second diagonal element of an inner product matrix and a class inner product matrix of original data corresponding to the target data.
In the embodiment of the invention, when a data reading instruction of a processor is received, target data is read from a memory, and because the target data obtained by reading may have errors, diagonal elements associated with the target data need to be read from the memory at the same time, wherein the diagonal elements associated with the target data comprise a first diagonal element and a second diagonal element of an inner product matrix of original data, and the first diagonal element and the second diagonal element of an inner product matrix of original data, the original data are data stored in the memory by a data storage user, namely storage data corresponding to the target data, and the diagonal elements associated with the target data can be used for positioning and correcting error data in subsequent target data.
Preferably, when the data storage instruction is received, data to be stored in the data storage instruction is acquired, an inner product matrix and an inner product-like matrix of the data to be stored are calculated, and when the data to be stored is written into the memory, a first diagonal element and a second diagonal element of the inner product matrix of the data to be stored and the first diagonal element and the second diagonal element of the inner product-like matrix of the data to be stored are written into the memory, so that the calculated amount for positioning and correcting multi-bit error data in the target data is effectively reduced when the target data is read from the memory later.
The error judging unit 22 is configured to calculate an inner product matrix and an inner product-like matrix of the target data, and determine whether the read target data is in error according to the diagonal elements associated with the target data and the first diagonal element and the second diagonal element of the inner product-like matrix and the target data.
In the embodiment of the invention, an inner product matrix and a class inner product matrix of target data are calculated. Preferably, the inner product matrix calculation formula of the target data is:
C'=X' t * X ', wherein X ' is the read target data, X ' t The transposed matrix of X 'and the inner product matrix of the target data are C';
the calculation formula of the inner product matrix of the class of the target data is as follows:
S'=X'*X' t wherein S' is an inner product matrix of the class of the target data.
In the embodiment of the present invention, the original data corresponding to the target data may be represented as X, and the inner product matrix of the original data may be represented as C, S, respectively, where X is a matrix with m X n size,C=X t *X,S=X*X t . If the multi-bit data in the read target data is wrong, for example, the data at the positions (i, j) and (p, q) are wrong, the inner product matrix of the target data is subtracted from the inner product matrix of the original data, the obtained matrix is zero except the jth row, the jth column, the qth row and the qth column, the data of other rows and columns are zero, the obtained matrix is subtracted from the inner product matrix of the original data, and the obtained matrix is zero except the ith row, the ith column, the p row and the p column, so that whether the target data is wrong or not can be determined according to the inner product matrix of the target data, the inner product matrix of the original data and the inner product matrix of the class, and the possible error position in the target data can be determined.
Preferably, since only the original data, the first diagonal element and the second diagonal element of the original data inner product matrix, and the first diagonal element and the second diagonal element of the original data inner product matrix are stored in the memory, when judging whether the read target data is wrong, whether the first diagonal element and the second diagonal element of the target data inner product matrix are consistent with the first diagonal element and the second diagonal element of the original data inner product matrix respectively, or whether the first diagonal element and the second diagonal element of the target data inner product matrix are consistent with the first diagonal element and the second diagonal element of the original data inner product matrix respectively is compared, so that the operation complexity of judging whether the read target data is wrong is effectively reduced.
The possible position determining unit 23 is configured to determine, when determining that the read target data is in error, each possible error position in the target data according to the diagonal element associated with the target data and the first diagonal element of the inner product matrix and the inner product matrix of the target data.
In the embodiment of the invention, after determining that the read target data is in error, the position of the first diagonal element of the inner product matrix of the target data, which is different from the element value in the first diagonal element of the inner product matrix of the original data, can be set as the column coordinate of the possible error position in the target data, the position of the first diagonal element of the inner product matrix of the target data, which is different from the element value in the first diagonal element of the inner product matrix of the original data, can be set as the row coordinate of the possible error position in the target data, and the column coordinates and the row coordinates are combined one by one to obtain all the possible error positions in the target data.
And a final error positioning unit 24, configured to determine a final error position and an error deviation amount corresponding to the final error position from all possible error positions according to the diagonal element associated with the target data and the second diagonal element of the target data inner product matrix and the class inner product matrix.
In the embodiment of the present invention, after all possible error positions in the target data are obtained, a first error deviation amount corresponding to each possible error position is calculated according to the second diagonal element of the inner product matrix of the target data and the second diagonal element of the inner product matrix of the original data, and then a second error deviation amount corresponding to each possible error position is calculated according to the second diagonal element of the inner product matrix of the target matrix class and the second diagonal element of the inner product matrix of the original matrix class, and the possible error position with the first error deviation amount being consistent with the second error deviation amount value in the possible error positions is set as the final error position. Since the first error deviation amount and the second error deviation amount corresponding to the final error position are the same, the first error deviation amount or the second error deviation amount corresponding to the final error position may be set as the error deviation amount of the final error position.
In the embodiment of the present invention, assuming that the possible error positions in the target data are respectively represented as (i, j), (i, q), (p, j), (p, q), preferably, when calculating the first error deviation amount corresponding to each possible error position, calculating the element C 'on the second diagonal element of the inner product matrix of the target data' j(j+1) 、C' q(q+1) Element C on the second diagonal element of the inner product matrix of the original data respectively j(j+1) 、C q(q+1) Is C' j(j+1) And C j(j+1) The calculation formula of the difference value is as follows:
wherein x is ij '=x ij +ΔE ij ,ΔE ij Data x at a potentially erroneous location (i, j) for target data ij ' data x at position (i, j) relative to the original data ij The first error deviation of (2) and thus +.>Similarly, the first error deviation amounts corresponding to the possible error positions (i, q), (p, j), (p, q) of the target data are respectively:
it is also preferable that, in calculating the second error deviation amounts respectively corresponding to each of the possible error positions, the element S 'on the second diagonal element of the inner product matrix of the target class of data is calculated' i(i+1) 、S' p(p+1) Element S on the second diagonal element of the inner product matrix of the original data respectively i(i+1) 、S p(p+1) Is S' j(j+1) And S is equal to j(j+1) The calculation formula of the difference value is as follows:
x ij '=x ij +ΔK ij ,ΔK ij data x at a potentially erroneous location (i, j) for target data ij Data x at' possible error location (i, j) relative to the original data ij A second error deviation of (2) to obtainSimilarly, the second error deviation amounts corresponding to the possible error positions (i, q), (p, j), (p, q) of the target data are respectively:
an error correction unit 25 for correcting the error data at the final error position in the target data according to the error deviation amount corresponding to the final error position.
In the embodiment of the invention, the error data at the final error position in the target data can be corrected by subtracting the corresponding error deviation amount from the error data at the final error position in the target data.
Preferably, as shown in fig. 3, the possible position determining unit 23 includes:
a column coordinate setting unit 331 for setting a position in which the element value of the first diagonal element of the target data inner product matrix is different from that of the first diagonal element of the original data inner product matrix as a column coordinate of a position where an error is likely;
a row coordinate setting unit 332, configured to set a position where the element value of the first diagonal element of the target data class inner product matrix is different from the element value of the first diagonal element of the original data class inner product matrix as a row coordinate of a possible error position; and
the coordinate combination unit 333 is configured to combine each column coordinate of the possible error location with each row coordinate of the possible error location one by one to generate all the possible error locations.
Preferably, the final error localization unit 24 includes:
a first deviation amount calculating unit 341, configured to calculate a first error deviation amount corresponding to each possible error position according to the second diagonal element of the target data inner product matrix and the second diagonal element of the original data inner product matrix;
a second deviation amount calculating unit 342, configured to calculate a second error deviation amount corresponding to each possible error position according to the second diagonal element of the target data class inner product matrix and the second diagonal element of the original data class inner product matrix;
a final position setting unit 343 for setting a possible error position, in which the first error deviation amount and the second error deviation amount are identical in value, as a final error position; and
an error deviation setting unit 344 for setting the first error deviation amount and the second error deviation amount corresponding to the final error position as the error deviation amounts corresponding to the final error position.
In the embodiment of the invention, the target data and the diagonal elements associated with the target data are read from the memory, whether the target data is in error or not is determined according to the diagonal elements associated with the target data, the inner product matrix of the target data, the first diagonal elements and the second diagonal elements of the inner product matrix of the target data, and when the target data is in error, each possible error position in the target data is determined, the final error position is determined at the possible error positions, and error data at the final error position is corrected, so that multi-bit error data in the data read from the memory are positioned and corrected, the hardware cost for positioning and correcting the multi-bit error data is reduced, and the accuracy and the efficiency for positioning and correcting the multi-bit error data are improved.
In the embodiment of the present invention, each unit of the multi-bit error data correction device may be implemented by a corresponding hardware or software unit, and each unit may be an independent software or hardware unit, or may be integrated into one software or hardware unit, which is not used to limit the present invention.
ExamplesThirdly,:
fig. 4 shows the structure of a computing device provided by the third embodiment of the present invention, and only the portions relevant to the embodiment of the present invention are shown for convenience of explanation.
The device 4 of the embodiment of the invention comprises a processor 40, a memory 41 and a computer program 42 stored in the memory 41 and executable on the processor 40. The processor 40, when executing the computer program 42, implements the steps of the method embodiments described above, such as steps S101 to S105 shown in fig. 1. Alternatively, the processor 40, when executing the computer program 42, performs the functions of the units in the above-described device embodiments, for example the functions of the units 21 to 25 shown in fig. 2.
In the embodiment of the invention, the target data and the diagonal elements associated with the target data are read from the memory, whether the target data is in error or not is determined according to the diagonal elements associated with the target data, the inner product matrix of the target data, the first diagonal elements and the second diagonal elements of the inner product matrix of the target data, and when the target data is in error, each possible error position in the target data is determined, the final error position is determined at the possible error positions, and error data at the final error position is corrected, so that multi-bit error data in the data read from the memory are positioned and corrected, the hardware cost for positioning and correcting the multi-bit error data is reduced, and the accuracy and the efficiency for positioning and correcting the multi-bit error data are improved.
Embodiment four:
in an embodiment of the present invention, there is provided a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps in the above-described method embodiment, for example, steps S101 to S105 shown in fig. 1. Alternatively, the computer program, when executed by a processor, performs the functions of the units in the above-described apparatus embodiments, for example, the functions of the units 21 to 25 shown in fig. 2.
In the embodiment of the invention, the target data and the diagonal elements associated with the target data are read from the memory, whether the target data is in error or not is determined according to the diagonal elements associated with the target data, the inner product matrix of the target data, the first diagonal elements and the second diagonal elements of the inner product matrix of the target data, and when the target data is in error, each possible error position in the target data is determined, the final error position is determined at the possible error positions, and error data at the final error position is corrected, so that multi-bit error data in the data read from the memory are positioned and corrected, the hardware cost for positioning and correcting the multi-bit error data is reduced, and the accuracy and the efficiency for positioning and correcting the multi-bit error data are improved.
The computer readable storage medium of embodiments of the present invention may include any entity or device capable of carrying computer program code, recording medium, such as ROM/RAM, magnetic disk, optical disk, flash memory, and so on.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (10)
1. A method for correcting multi-bit erroneous data, said method comprising the steps of:
when a data reading instruction is received, reading target data and diagonal elements associated with the target data from a memory, wherein the diagonal elements associated with the target data comprise first diagonal elements and second diagonal elements of an original data inner product matrix and a quasi inner product matrix corresponding to the target data; wherein the first diagonal element is a main diagonal element, and the second diagonal element is a diagonal element on the upper side of the main diagonal;
calculating an inner product matrix and a class inner product matrix of the target data, and determining whether the read target data is in error or not according to diagonal elements associated with the target data, and first diagonal elements and second diagonal elements of the inner product matrix and the class inner product matrix of the target data;
when the read target data is determined to be in error, determining each possible error position in the target data according to diagonal elements associated with the target data and first diagonal elements of the inner product matrix and the inner product matrix of the target data;
determining a final error position and an error deviation amount corresponding to the final error position in all possible error positions according to the diagonal elements associated with the target data and the second diagonal elements of the inner product matrix and the class inner product matrix of the target data;
and correcting the error data at the final error position in the target data according to the error deviation amount corresponding to the final error position.
2. The method of claim 1, wherein the step of determining whether the read target data is erroneous comprises:
judging whether the first diagonal element and the second diagonal element of the target data inner product matrix are consistent with the first diagonal element and the second diagonal element of the original data inner product matrix respectively; or alternatively
And judging whether the first diagonal element and the second diagonal element of the target data inner product matrix are respectively consistent with the first diagonal element and the second diagonal element of the original data inner product matrix.
3. The method of claim 1, wherein determining each potentially erroneous location in the target data comprises:
setting a position of the first diagonal element of the target data inner product matrix, which is different from the element value in the first diagonal element of the original data inner product matrix, as column coordinates of the possible error position;
setting a position of the first diagonal element of the target data class inner product matrix, which is different from the element value in the first diagonal element of the original data class inner product matrix, as row coordinates of the possible error position;
and combining each column coordinate of the possible error positions with each row coordinate of the possible error positions one by one to generate all the possible error positions.
4. The method of claim 1, wherein the step of determining a final error location and an error offset corresponding to the final error location among all possible error locations comprises:
calculating a first error deviation value corresponding to each possible error position according to the second diagonal element of the target data inner product matrix and the second diagonal element of the original data inner product matrix;
calculating a second error deviation value corresponding to each possible error position according to the second diagonal element of the target data class inner product matrix and the second diagonal element of the original data class inner product matrix;
setting the error-prone position at which the first error deviation amount and the second error deviation amount are numerically consistent as the final error position;
and setting the first error deviation amount and the second error deviation amount corresponding to the final error position as the error deviation amounts corresponding to the final error position.
5. The method of claim 1, wherein prior to the step of reading target data and diagonal elements associated with the target data from memory, the method further comprises:
when a data storage instruction is received, acquiring data to be stored in the data storage instruction, and calculating an inner product matrix and a class inner product matrix of the data to be stored;
writing the data to be stored into the memory, and simultaneously writing a first diagonal element and a second diagonal element of the inner product matrix of the data to be stored, which are similar to the inner product matrix, into the memory.
6. A correction device for multi-bit erroneous data, said device comprising:
the data reading unit is used for reading target data and diagonal elements associated with the target data from a memory when a data reading instruction is received, wherein the diagonal elements associated with the target data comprise first diagonal elements and second diagonal elements of an inner product matrix and a similar inner product matrix of original data corresponding to the target data; wherein the first diagonal element is a main diagonal element, and the second diagonal element is a diagonal element on the upper side of the main diagonal;
the error judging unit is used for calculating an inner product matrix and a class inner product matrix of the target data and determining whether the read target data is in error or not according to diagonal elements associated with the target data, and first diagonal elements and second diagonal elements of the inner product matrix and the class inner product matrix of the target data;
a possible position determining unit, configured to determine, when it is determined that the read target data is in error, each possible error position in the target data according to a diagonal element associated with the target data and a first diagonal element of the inner product matrix and the inner product matrix of the target data;
a final error positioning unit, configured to determine a final error position and an error deviation amount corresponding to the final error position in all possible error positions according to the diagonal element associated with the target data and the second diagonal element of the inner product matrix and the inner product matrix of the target data; and
and the error correction unit is used for correcting the error data at the final error position in the target data according to the error deviation amount corresponding to the final error position.
7. The apparatus of claim 6, wherein the possible location determination unit comprises:
a column coordinate setting unit configured to set, as column coordinates of the possible error location, a location in which an element value in a first diagonal element of the target data inner product matrix is different from an element value in a first diagonal element of the original data inner product matrix;
a row coordinate setting unit, configured to set, as row coordinates of the possible error location, a location where an element value in a first diagonal element of the target data class inner product matrix is different from an element value in a first diagonal element of the original data class inner product matrix; and
and the coordinate combination unit is used for combining each column coordinate of the possible error positions with each row coordinate of the possible error positions one by one to generate all the possible error positions.
8. The apparatus of claim 6, wherein the final error localization unit comprises
A first deviation amount calculating unit, configured to calculate a first error deviation amount corresponding to each possible error position according to the second diagonal element of the target data inner product matrix and the second diagonal element of the original data inner product matrix;
a second deviation amount calculating unit, configured to calculate a second error deviation amount corresponding to each possible error position according to the second diagonal element of the target data class inner product matrix and the second diagonal element of the original data class inner product matrix;
a final position setting unit configured to set the error-prone position at which the first error deviation amount and the second error deviation amount are numerically identical as the final error position; and
and the error deviation setting unit is used for setting the first error deviation amount and the second error deviation amount corresponding to the final error position as the error deviation amount corresponding to the final error position.
9. A computing device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method of any of claims 1 to 5 when the computer program is executed.
10. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the method according to any one of claims 1 to 5.
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1959648A (en) * | 2005-10-31 | 2007-05-09 | 国际商业机器公司 | Data protection method |
US20070198890A1 (en) * | 2005-11-13 | 2007-08-23 | International Business Machines Corporation | Method for creating an error correction coding scheme |
CN101345605A (en) * | 2007-07-11 | 2009-01-14 | 索尼株式会社 | Transmitting apparatus, receiving apparatus, error correcting system, transmitting method, and error correcting method |
CN101621299A (en) * | 2008-07-04 | 2010-01-06 | 华为技术有限公司 | Burst correcting method, equipment and device |
CN102141976A (en) * | 2011-01-10 | 2011-08-03 | 中国科学院软件研究所 | Method for storing diagonal data of sparse matrix and SpMV (Sparse Matrix Vector) realization method based on method |
US20160125439A1 (en) * | 2014-10-31 | 2016-05-05 | The Nielsen Company (Us), Llc | Methods and apparatus to correct segmentation errors |
US9577675B1 (en) * | 2013-12-03 | 2017-02-21 | Marvell International Ltd. | System and method for encoding user data with low-density parity-check codes with flexible redundant parity check matrix structures |
-
2018
- 2018-06-06 CN CN201810575940.1A patent/CN109032833B/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1959648A (en) * | 2005-10-31 | 2007-05-09 | 国际商业机器公司 | Data protection method |
US20070198890A1 (en) * | 2005-11-13 | 2007-08-23 | International Business Machines Corporation | Method for creating an error correction coding scheme |
CN101345605A (en) * | 2007-07-11 | 2009-01-14 | 索尼株式会社 | Transmitting apparatus, receiving apparatus, error correcting system, transmitting method, and error correcting method |
CN101621299A (en) * | 2008-07-04 | 2010-01-06 | 华为技术有限公司 | Burst correcting method, equipment and device |
CN102141976A (en) * | 2011-01-10 | 2011-08-03 | 中国科学院软件研究所 | Method for storing diagonal data of sparse matrix and SpMV (Sparse Matrix Vector) realization method based on method |
US9577675B1 (en) * | 2013-12-03 | 2017-02-21 | Marvell International Ltd. | System and method for encoding user data with low-density parity-check codes with flexible redundant parity check matrix structures |
US20160125439A1 (en) * | 2014-10-31 | 2016-05-05 | The Nielsen Company (Us), Llc | Methods and apparatus to correct segmentation errors |
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