CN108989849B - DVB-T2+ S2 television signal processing method and system - Google Patents
DVB-T2+ S2 television signal processing method and system Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/238—Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams
- H04N21/2383—Channel coding or modulation of digital bit-stream, e.g. QPSK modulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/426—Internal components of the client ; Characteristics thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/433—Content storage operation, e.g. storage operation in response to a pause request, caching operations
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/438—Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving MPEG packets from an IP network
- H04N21/4382—Demodulation or channel decoding, e.g. QPSK demodulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client
- H04N21/61—Network physical structure; Signal processing
- H04N21/6106—Network physical structure; Signal processing specially adapted to the downstream path of the transmission network
- H04N21/6112—Network physical structure; Signal processing specially adapted to the downstream path of the transmission network involving terrestrial transmission, e.g. DVB-T
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client
- H04N21/61—Network physical structure; Signal processing
- H04N21/6106—Network physical structure; Signal processing specially adapted to the downstream path of the transmission network
- H04N21/6143—Network physical structure; Signal processing specially adapted to the downstream path of the transmission network involving transmission via a satellite
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Abstract
The invention provides a DVB-T2+ S2 television signal processing method and a system, wherein the system comprises an audio buffer: for buffering the digital audio data; video buffer: for caching the digital video data; high-speed flash memory: the GOP storage device is used for storing all pixel point data of all frames of a GOP; a video output module: the video playing device is used for playing the processed video data; a permanent storage: for storing the processed DVB-T2+ S2 television signals. The DVB-T2+ S2 television signal processing method and the system provided by the invention have the advantages that the content of the video signal of the television signal is subjected to lossy compression under the condition of keeping the picture quality as much as possible, the space occupied by the storage of the television signal is reduced, the utilization rate of a memory is improved, and the practicability is good.
Description
Technical Field
The invention relates to the field of television broadcasting, in particular to a DVB-T2+ S2 television signal processing method and system.
Background
DVB (Digital Video Broadcasting) is a series of internationally recognized Digital television public standards maintained by the DVB project.
The transmission modes of the DVB system include the following modes: satellite (DVB-S and DVB-S2), cable (DVB-C), terrestrial radio (DVB-T), and terrestrial radio-handheld (DVB-H). The main difference between these transmission modes is the modulation mode used, since the requirements of the frequency bandwidth to which they are applied differ from modulation mode to modulation mode. The DVB-S using the high frequency carrier uses QPSK modulation, the DVB-C using the low frequency carrier uses QAM-64 modulation, and the DVB-T using the VHF and UHF carriers uses COFDM modulation.
Many set-top boxes on the market are integrated with DVB-T and DVB-S decoding modules, and can realize the decoding and restoring of DVB-T signals and DVB-S signals.
DVB-T and DVB-S signals are used for a large part to store backups in addition to television playback. DVB-T and DVB-S adopt an MPEG transport stream format, the compression ratio is large, and the storage space of DVB-T and DVB-S data is difficult to reduce through the change of the compression format. With the explosive growth of the number of tv programs, it is difficult for the existing storage devices to store the DVB signals completely.
Disclosure of Invention
Aiming at the defects of the DVB-T2+ S2 television signal processing method and system in television signal storage, the invention provides the DVB-T2+ S2 television signal processing method and system, which are used for lossy compression of video signal contents of television signals, reduce the space occupied by television signal storage, improve the utilization rate of a memory and have good practicability.
Correspondingly, the invention provides a DVB-T2+ S2 television signal processing method, which comprises the following steps:
receiving a satellite television modulation signal or a ground television modulation signal based on an antenna module;
decoding and demultiplexing the satellite television modulation signal or the ground television modulation signal based on a DVB-T2+ S2 decoding module to generate digital audio data and digital video data containing a plurality of GOPs, and respectively storing the digital audio data and the digital video data into an audio buffer and a video buffer;
based on the processor module, sequentially converting the digital video data into pixel point data of a video output module by taking GOP as a unit and loading the pixel point data into a high-speed flash memory;
after outputting the first frame of pixel point data in the high-speed flash memory to a video output module based on the processor module, randomly extracting and outputting the pixel point data of the rest frames in the high-speed flash memory to the video output module according to a preset clock signal;
adjusting the clock control signal until the output image of the video output module is stable;
and storing the output image of the video output module and the digital audio data of the audio buffer into a permanent memory based on a processor module.
The processor-based module sequentially converts the digital video data into pixel point data of a video output module by taking GOP as a unit and loads the pixel point data into a high-speed flash memory, and comprises the following steps:
and analyzing the I frame, the P frame and the B frame in the GOP based on a processor module, generating all pixel point data of all frames in the GOP and loading the pixel point data into a high-speed flash memory.
The pixel point data is YCbCr data of a pixel point.
At most, only pixel point data of a group of GOP is stored in the high-speed flash memory.
After outputting the first frame of pixel point data in the high-speed flash memory to the video output module based on the processor module, randomly extracting and outputting the pixel point data of the rest frames in the high-speed flash memory to the video output module according to a preset clock signal comprises the following steps:
each frame of pixel point data occupies x-bit address of the high-speed flash memory;
outputting the pixel point of the front x-bit address in the high-speed flash memory to a video output module based on the processor module;
sequentially outputting n-bit pixel point data in (ix +1) th to (i +1) th x bits to a processor module based on the processor module according to a preset clock signal, wherein i is a positive integer, i is more than or equal to 1, and n is less than or equal to x;
and the other pixel point data except the n-bit pixel point data is the same as the pixel point data obtained by subtracting the x-bit address from the self address.
The processor-based module storing the output image of the video output module and the digital audio data of the audio buffer in a persistent memory comprises the steps of:
based on the MPEG standard, the processor module compresses the output image of the video output module and the digital audio data of the audio buffer.
The processor module compressing the output image of the video output module and the digital audio data of the audio buffer based on the MPEG standard comprises the following steps:
compressing, based on the processor module, output pictures of the video output module into I-frames, P-frames, B-frames in a plurality of consecutive GOPs.
The permanent memory stores the output image of the video output module and the digital audio data of the audio buffer based on the ROID 0.
Correspondingly, the invention also provides a DVB-T2+ S2 television signal processing system, which comprises
An antenna module: the antenna module is used for receiving satellite television modulation signals or terrestrial television modulation signals;
DVB-T2+ S2 Decode Module: the system is used for decoding and demultiplexing the satellite television modulation signal or the ground television modulation signal to generate digital audio data and digital video data containing a plurality of GOPs;
a clock signal module: for generating a clock signal;
the processor module: the video output module is used for converting the digital video data into pixel point data of the video output module in sequence by taking GOP as a unit, loading the pixel point data into the high-speed flash memory, outputting the first frame of pixel point data in the high-speed flash memory to the video output module, then randomly extracting and outputting the pixel point data of the rest frames in the high-speed flash memory to the video output module according to a preset clock signal, and storing an output image of the video output module and the digital audio data of the audio buffer into a permanent memory;
audio buffer: for buffering the digital audio data;
video buffer: for caching the digital video data;
high-speed flash memory: the GOP storage device is used for storing all pixel point data of all frames of a GOP;
a video output module: the video playing device is used for playing the processed video data;
a permanent storage: for storing the processed DVB-T2+ S2 television signals.
The embodiment of the invention provides a DVB-T2+ S2 television signal processing method and system, which are used for lossy compression of video signal contents of television signals, reduce the space occupied by television signal storage, improve the utilization rate of a storage and have good practicability.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 shows a flow diagram of a DVB-T2+ S2 television signal processing method of an embodiment of the present invention;
fig. 2 shows a flow chart of operations at the transmitting end of a DVB television signal;
fig. 3 shows a flow chart of the operation of a DVB television signal receiving end;
figure 4 shows a block diagram of a DVB-T2+ S2 television signal processing system in accordance with an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The compression mode of MPEG-2 is already mature, it is difficult to improve it on the compression technology at present, make the data space take up and reduce while keeping good commonality, therefore, the embodiment of the invention provides a DVB-T2+ S2 television signal processing method and system, carry on the lossy compression to the video signal content of the television signal, reduce the storage space of television signal, raise the utilization factor of the memorizer.
Fig. 1 shows a flow chart of a DVB-T2+ S2 television signal processing method according to an embodiment of the present invention, and the DVB-T2+ S2 television signal processing method according to the embodiment of the present invention includes the following steps:
s101: receiving a satellite television modulation signal or a ground television modulation signal based on an antenna module;
fig. 2 shows a flow diagram of a transmitting end of a television signal. Basically, the input of the transmitting end (i.e., satellite or terrestrial broadcasting station) is image/sound digital data, and the output is a modulated radio frequency signal. The input video and audio data is subjected to audio and video coding, multiplexing and modulation, and is sent out for 4 steps to form a final signal and is transmitted in different modes.
Fig. 3 shows a flow chart of a receiving end of a television signal, which does the exact opposite of the transmitting end. The input video and audio data are received, demodulated, demultiplexed and decoded in 4 steps to complete the signal reception and finally output to the display screen/sound equipment of the terminal.
Aiming at DVB-S2 digital satellite direct broadcast system standard, the standard takes a satellite as a transmission medium, puts video, audio and data into MPEG-2 transmission stream packed by fixed length, has strong anti-interference capability during the transmission process of signals, and then carries out channel processing. The compressed digital signal transmitted by the satellite is processed by the satellite set-top box after passing through the satellite receiver, and a video signal is output.
Aiming at DVB-T2 digital terrestrial broadcasting system standard, a Coded Orthogonal Frequency Division Multiplexing (COFDM) modulation mode is used, 4 sets of television programs can be transmitted in an 8MHz bandwidth, and the transmission quality is high. MPEG-2 digital video and audio compression coding technology is adopted. The transmission capacity of terrestrial digital transmission is theoretically almost equivalent to that of a cable television system, and the coverage of a local area is good.
In a specific implementation, the signal receiving operation of the receiving terminal is completed by the antenna module. Specifically, the antenna module may be divided into a satellite signal antenna and a broadcast signal antenna for satellite television modulated signals (i.e., DVB-S2 satellite signals) and terrestrial television modulated signals (i.e., DVB-T2 terrestrial broadcast signals).
S102: decoding and demultiplexing the satellite television modulation signal or the terrestrial television modulation signal based on a DVB-T2+ S2 decoding module to generate digital audio data and digital video data containing a plurality of GOPs;
s103: the digital audio data is stored in an audio buffer, and the digital video data is stored in a video buffer;
based on the DVB-T2+ S2 decoding module, the demodulation and demultiplexing work is carried out, the satellite television modulation signal and/or the terrestrial television modulation signal are/is decoded and demultiplexed, and digital audio data and digital video data are generated.
The conventional decoding module needs to decode and output digital audio data and digital video data directly, and the DVB-T2+ S2 television signal processing method according to the embodiment of the invention outputs the digital audio data to the audio buffer and outputs the digital video data to the video buffer instead of outputting the digital video data directly.
Generally, according to the MPEG-2 frame structure, digital video data is composed of a plurality of GOPs (group of picture image groups), each GOP being composed of a series of I frames, P frames, and B frames in a fixed pattern. A commonly used structure consists of 15 frames in the form of IBBPBBPBBPBBPBB.
The I frame represents a key frame, which can be understood as the complete preservation of the picture of this frame; decoding can be completed only by the frame data (because the complete picture is contained).
The P frame represents the difference between the frame and a previous key frame (or P frame), and the difference defined by the frame needs to be superimposed on the previously buffered picture to generate a final picture when decoding (i.e. the P frame has no complete picture data and only has data different from the picture of the previous frame).
The B frame is a bidirectional difference frame, that is, the B frame records the difference between the current frame and the previous and subsequent frames, and when the B frame is decoded, not only the previous buffer picture but also the decoded picture are obtained, and the final picture is obtained by the superposition of the previous and subsequent pictures and the current frame data.
The existing Set Top Box (STB), receiving card, digital tv set, mobile device, etc. can all complete the operation of this step, and the embodiment of the present invention is not described in detail.
S104: based on the processor module, sequentially converting the digital video data into pixel point data of a video output module by taking GOP as a unit and loading the pixel point data into a high-speed flash memory;
and decoding the digital video data in the video memory, sequentially converting the digital video data into pixel point data of a video output module by taking GOP as a unit, and loading the pixel point data to the high-speed flash memory.
The pixel data refers to color information of a pixel, such as rgb information or YCbCr information of the pixel.
YCbCr or Y' CbCr are sometimes written as: YCBCR or Y' CBCR, which is a type of color space, is commonly used in video processing for continuous processing in movies, or in digital photography systems. Y' is the luminance (luma) component of the color, while CB and CR are the density offset components of the blue and red colors. Y' and Y are different, and Y is the so-called lumen (luminance), which represents the concentration of light and is non-linear, using a gamma correction (gamma correction) encoding process. The human eye is more sensitive to the Y component of the video and therefore the eye will not perceive a change in image quality after the chrominance component has been reduced by sub-sampling the chrominance component, the main sub-sampling formats being YCbCr 4:2:0, YCbCr 4:2:2 and YCbCr 4:4: 4.
And reading the decoded digital video data in the video buffer through the processor module, and loading all pixel data of all frames in one GOP into the high-speed flash memory by taking the GOP as a unit.
Specifically, the pixel data may be YCbCr data of the pixel, or the YCbCr data may be loaded after being converted into RGB data.
The specific conversion formula is as follows,
R＝1.164*(Y-16)+1.596*(Cr-128)
G＝1.164*(Y-16)-0.392*(Cb-128)-0.813*(Cr-128)
B＝1.164*(Y-16)+2.017*(Cb-128)。
specifically, the storage physical structure of the pixel point in the high-speed flash memory is as follows:
each frame of pixel point data occupies x-bit address of the high-speed flash memory, i.e. the first frame occupies 0 to x-bit address of the high-speed flash memory, the second frame occupies (x +1) to (2x) bit address … … of the high-speed flash memory, and so on.
In a specific implementation, digital video data is decoded and stored, usually in units of GOPs; each decoding and storing is orderly, namely, synchronously generated, and because the secondary operation is not needed, the decoded and stored data is not reserved after being used or taken out, and the memory address is emptied.
S105: after outputting the first frame of pixel point data in the high-speed flash memory to a video output module based on the processor module, randomly extracting and outputting the pixel point data of the rest frames in the high-speed flash memory to the video output module according to a preset clock signal;
pixel information of frames of at most 1 GOP is cached in the high-speed flash memory at each moment, generally, the 1 st frame information is output to a video output module, namely pixel point data of 0-x bit addresses are output to the video output module, then, according to a set clock signal and a preset clock signal, n-bit pixel point data in (ix +1) -x-bits (i +1) are sequentially output to a processor module based on the processor module, wherein i is a positive integer, i is more than or equal to 1, and n is less than or equal to x;
in a GOP, the other pixel point data outside the n-bit pixel point data is the same as the pixel point data obtained by subtracting the x-bit address from the self address, namely the other pixel point data outside the n-bit pixel point data is the same as the pixel point data at the same position of the previous frame.
The clock signal can be regarded as a fixed square wave signal, when the clock signal is in a high level, the processor module sequentially outputs n-bit pixel point data in (ix +1) th to (i +1) th x bits to the video output module, wherein i is a positive integer, i is more than or equal to 1, and n is less than or equal to x;
when the clock signal is in low level, the processor module outputs the rest pixel point data except the n-bit pixel point data and the pixel point data obtained by subtracting the x-bit address from the self address to the video output module.
To ensure that the percentage of data retained in each GOP is the same, the percentage of the high level of the clock signal in each GOP should be the same.
Distortion of the image is inevitable to some extent due to the setting of the P frame of MPEG; the method comprises the following steps that (1) change image vector information of first 1-2 frames I mainly recorded by a P frame is known from recording information of the P frame; if the decoded video signal is compressed again in the IBBPBBPBBPBBPBB format, the storage space occupation does not change much even in the case of distortion.
Therefore, the present embodiment of the invention adjusts the content of the video data. According to the embodiment of the invention, the decoded video data is partially extracted and output except the first frame according to the clock signal, and compared with the original video data, the difference between the previous frame and the next frame (the difference pixel points are reduced) of the extracted video data is reduced, which is beneficial to reducing the storage space occupation of the B frame and the P frame.
Specifically, some of the remaining pixel point data other than the n-bit pixel point data is exactly the same as the pixel point data obtained by subtracting the x-bit address from the own address; however, a part of the pixel data is changed, namely the pixel data is different from the pixel data obtained by subtracting the x-bit address from the self address, and the embodiment of the invention enables the part of the pixel data to be equal to the pixel data obtained by subtracting the x-bit address from the self address, so that the number of the pixels of the video data which are changed as a whole is reduced, namely the capacities of the B frame and the P frame are reduced, and the storage space occupied by the compressed video data is reduced.
S106: adjusting the clock control signal until the output image of the video output module is stable;
according to the method, part of detail information can be lost, but video data with moderate size and quality can be obtained by adjusting the overall ratio of the high-level signal of the clock signal; the final standard is to observe the stability of the video signal by naked eyes, the image can be basically continuous, and the total distortion degree is preferably not more than 30%.
S107: and storing the output image of the video output module and the digital audio data of the audio buffer into a permanent memory based on a processor module.
Specifically, the processor module repacks the output image of the video output module into digital video data, and the digital video data and the digital audio data are integrally stored in the permanent memory.
The specific packaging mode can adopt an MPEG mode to ensure the compression rate, and the storage mode can adopt an RAID0 mode for storage so as to improve the data security.
RAID0, also known as Stripe or Striping, represents the highest storage performance of all RAID levels. The principle behind RAID0 for improving storage performance is to distribute consecutive data across multiple disks for access so that a system with data requests can be executed by multiple disks in parallel, each disk executing its own portion of the data request. The parallel operation on the data can fully utilize the bandwidth of the bus and obviously improve the overall access performance of the disk.
Figure 4 shows a block diagram of a DVB-T2+ S2 television signal processing system in accordance with an embodiment of the invention, the dashed lines identifying the control signal connections. Correspondingly, the embodiment of the invention also provides a DVB-T2+ S2 television signal processing system, which comprises
An antenna module: the antenna module is used for receiving satellite television modulation signals or terrestrial television modulation signals;
DVB-T2+ S2 Decode Module: the system is used for decoding and demultiplexing the satellite television modulation signal or the ground television modulation signal to generate digital audio data and digital video data containing a plurality of GOPs;
a clock signal module: for generating a clock signal;
the processor module: the video output module is used for converting the digital video data into pixel point data of the video output module in sequence by taking GOP as a unit, loading the pixel point data into the high-speed flash memory, outputting the first frame of pixel point data in the high-speed flash memory to the video output module, then randomly extracting and outputting the pixel point data of the rest frames in the high-speed flash memory to the video output module according to a preset clock signal, and storing an output image of the video output module and the digital audio data of the audio buffer into a permanent memory;
audio buffer: for buffering the digital audio data;
video buffer: for caching the digital video data;
high-speed flash memory: the GOP storage device is used for storing all pixel point data of all frames of a GOP;
a video output module: the video playing device is used for playing the processed video data;
a permanent storage: for storing the processed DVB-T2+ S2 television signals.
The embodiment of the invention provides a DVB-T2+ S2 television signal processing method and system, which are used for lossy compression of video signal contents of television signals, reduce the space occupied by television signal storage, improve the utilization rate of a storage and have good practicability.
The DVB-T2+ S2 television signal processing method and system provided by the embodiments of the present invention are described in detail above, and a specific example is applied in the present disclosure to explain the principle and the implementation of the present invention, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable storage medium, and the storage medium may include: read Only Memory (ROM), Random Access Memory (RAM), magnetic or optical disks, and the like.
Claims (2)
1. A DVB-T2+ S2 television signal processing method, comprising the steps of:
receiving a satellite television modulation signal or a ground television modulation signal based on an antenna module;
decoding and demultiplexing the satellite television modulation signal or the ground television modulation signal based on a DVB-T2+ S2 decoding module to generate digital audio data and digital video data containing a plurality of GOPs, and respectively storing the digital audio data and the digital video data into an audio buffer and a video buffer;
based on the processor module, sequentially converting the digital video data into pixel point data of a video output module by taking GOP as a unit and loading the pixel point data into a high-speed flash memory;
after outputting the first frame of pixel point data in the high-speed flash memory to a video output module based on the processor module, randomly extracting and outputting the pixel point data of the rest frames in the high-speed flash memory to the video output module according to a preset clock signal;
adjusting the clock control signal until the output image of the video output module is stable;
storing the output image of the video output module and the digital audio data of the audio buffer into a permanent memory based on a processor module;
the processor-based module sequentially converts the digital video data into pixel point data of a video output module by taking GOP as a unit and loads the pixel point data into a high-speed flash memory, and comprises the following steps:
analyzing an I frame, a P frame and a B frame in the GOP based on a processor module, generating all pixel point data of all frames in the GOP and loading the pixel point data into a high-speed flash memory;
the pixel point data is YCbCr data of a pixel point;
at most, only storing pixel point data of a group of GOPs in the high-speed flash memory;
after outputting the first frame of pixel point data in the high-speed flash memory to the video output module based on the processor module, randomly extracting and outputting the pixel point data of the rest frames in the high-speed flash memory to the video output module according to a preset clock signal comprises the following steps:
each frame of pixel point data occupies x-bit address of the high-speed flash memory;
outputting the pixel point of the front x-bit address in the high-speed flash memory to a video output module based on the processor module;
according to a preset clock signal, the preset clock signal is a square wave signal, when the clock signal is at a high level, n-bit pixel point data in (ix +1) th to (i +1) th x bits are sequentially output to a processor module based on the processor module, wherein i is a positive integer, i is not less than 1, and n is not more than x, when the clock signal is at a low level, the processor module outputs the rest pixel point data outside the n-bit pixel point data and pixel point data obtained by subtracting an x-bit address from the address of the processor module to a video output module;
the processor-based module storing the output image of the video output module and the digital audio data of the audio buffer in a persistent memory comprises the steps of:
based on MPEG standard, the processor module compresses the output image of the video output module and the digital audio data of the audio buffer;
the processor module compressing the output image of the video output module and the digital audio data of the audio buffer based on the MPEG standard comprises the following steps:
compressing, based on the processor module, output images of the video output module into I-frames, P-frames, B-frames in a plurality of consecutive GOPs;
the permanent memory stores the output image of the video output module and the digital audio data of the audio buffer based on the ROID 0.
2. A DVB-T2+ S2 television signal processing system, comprising
An antenna module: the antenna module is used for receiving satellite television modulation signals or terrestrial television modulation signals;
DVB-T2+ S2 Decode Module: the system is used for decoding and demultiplexing the satellite television modulation signal or the ground television modulation signal to generate digital audio data and digital video data containing a plurality of GOPs;
a clock signal module: for generating a clock signal;
the processor module: the digital video data are sequentially converted into pixel point data of a video output module by taking GOP as a unit and loaded into a high-speed flash memory; the high-speed flash memory is also used for randomly extracting and outputting pixel point data of other frames in the high-speed flash memory to the video output module according to a preset clock signal after outputting the pixel point data of the first frame in the high-speed flash memory to the video output module; the device is also used for storing the output image of the video output module and the digital audio data of the audio buffer into a permanent memory;
after outputting the first frame of pixel point data in the high-speed flash memory to the video output module, randomly extracting and outputting the pixel point data of the rest frames in the high-speed flash memory to the video output module according to a preset clock signal comprises the following steps:
each frame of pixel point data occupies x-bit address of the high-speed flash memory;
outputting the pixel point of the front x-bit address in the high-speed flash memory to a video output module based on the processor module;
according to a preset clock signal, the preset clock signal is a square wave signal, when the clock signal is at a high level, n-bit pixel point data in (ix +1) th to (i +1) th x bits are sequentially output to a processor module based on the processor module, wherein i is a positive integer, i is not less than 1, and n is not more than x, when the clock signal is at a low level, the processor module outputs the rest pixel point data outside the n-bit pixel point data and pixel point data obtained by subtracting an x-bit address from the address of the processor module to a video output module;
audio buffer: for buffering the digital audio data;
video buffer: for caching the digital video data;
high-speed flash memory: the GOP storage device is used for storing all pixel point data of all frames of a GOP;
a video output module: the video playing device is used for playing the processed video data;
a permanent storage: for storing the processed DVB-T2+ S2 television signals.
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