CN108988820B - Network information analysis system - Google Patents
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- CN108988820B CN108988820B CN201811161102.6A CN201811161102A CN108988820B CN 108988820 B CN108988820 B CN 108988820B CN 201811161102 A CN201811161102 A CN 201811161102A CN 108988820 B CN108988820 B CN 108988820B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
Abstract
The invention discloses a network information analysis system, which is characterized in that weak signals in a network information transmission channel received by a regeneration receiving circuit are positively fed back through an oscillator taking a triode Q1 as a core to carry out distortion compensation and primary amplification, wherein an operational amplifier AR3 is used for feeding back primary amplification signals, so that the accuracy of distortion compensation is improved, signals meeting the amplitude and frequency requirements of a later-stage circuit are output, the signals enter a filter circuit, noise interference is filtered through an LC filter circuit, the interference of other frequency signals is avoided by a band-pass filter, the signals enter a signal amplitude modulation circuit, boosting secondary amplitude modulation is carried out through a Boost circuit, and when the output signals are abnormal, a thyristor is conducted, the signals enter a subtracter to output difference signals and are converted into PWM signals to be coupled to a grid electrode of a MOS tube Q1 to control the conduction or cut-off of the MOS tube Q1, so that the accuracy of the secondary amplitude modulation is controlled. The problem that signal distortion and attenuation in a network information transmission channel can not be effectively received by a terminal server is effectively solved.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a network information analysis system.
Background
The development of a network system, the transmission of a lot of information through the network brings great convenience to people, along with the increasing dependence of people on the network (such as the Internet), the comprehensive monitoring analysis of all the transmitted information in the network is particularly important in terms of eliminating network accidents, improving network safety and improving network performance, at present, a network analysis system (such as a Kelai network analysis system) is mainly adopted for analysis, and a signal in a real-time packet-grabbing network information transmission channel is particularly transmitted to a terminal server, and the received signal is analyzed through the terminal server, however, the signal is transmitted through a long-distance channel, and the signal is distorted and attenuated due to the attenuation of the channel and the interference of noise and other signals, so that the terminal server cannot effectively receive the signal in a data transmission channel.
The present invention provides a new solution to this problem.
Disclosure of Invention
Aiming at the situation, in order to overcome the defects of the prior art, the invention aims to provide a network information analysis system which has the characteristics of ingenious conception and humanized design, and effectively solves the problem that signal distortion and attenuation in a network information transmission channel cannot be effectively received by a terminal server.
The technical scheme is that the device comprises a regeneration receiving circuit, a filter circuit and a signal amplitude modulation circuit, and is characterized in that weak signals in a network information transmission channel received by the regeneration receiving circuit are positively fed back through an oscillator taking a triode Q1 as a core, the weak signals in the received network information transmission channel are subjected to distortion compensation and primary amplification, an operational amplifier AR3 is used for feeding back primary amplification signals to an input end of the oscillator taking the triode Q1 as the core, the primary amplification signals meet the amplitude and frequency requirements of a later stage circuit, the primary amplification signals enter the filter circuit, the external interference is filtered through LC (inductance-capacitance) filter, the band-pass filter taking the operational amplifier AR1 as the core selects frequencies, only the frequencies of the primary amplification signals are allowed to pass, signals outside the frequency range are blocked, finally the primary amplification signals enter the signal amplitude modulation circuit, secondary amplitude modulation is carried out through a Boost circuit consisting of an inductor L4, a MOS (metal oxide semiconductor) tube Q1, a diode D2, a resistor R14 and a resistor R15, when the output signals do not meet the standard signals 0V to +5V received by a server for an analysis system, the thyristor L1 triggers to be conducted, the operational amplifier enters the MOS 2 to be converted into the standard signals of a subtracter, the signal is controlled to be the differential value of the Q-stage, and the differential value is controlled to be conducted to be the PWM (pulse width of the Q1), and the differential value is controlled to be the differential, and the differential value of the PWM signal is controlled to be the Q1.
Preferably, the signal amplitude modulation circuit comprises a MOS transistor Q1 and a diode D1, wherein the drain electrode of the MOS transistor Q1, the cathode of the diode D1 and one end of a resistor R14 are connected with the output end of an operational amplifier AR1, the source electrode of the MOS transistor Q1 and the anode of the diode D1 are respectively connected with one end of a grounding inductor L4 and the cathode of a diode D2, the anode of the diode D2 is connected with a signal output port, the anode of a thyristor VTL1, the cathode of the voltage regulator Z1 and the anode of the voltage regulator Z2, the control electrode of the thyristor VTL1 is respectively connected with the anode of the voltage regulator Z1, one end of a grounding resistor R11, one end of a grounding capacitor C9 and one end of a resistor R9, the other end of the resistor R9 is connected with the cathode of the voltage regulator Z2, the cathode of the thyristor VTL1 is connected with one end of a resistor R10, the other end of the resistor R10 is connected with the same phase input end of the operational amplifier AR2, the inverting input end of the operational amplifier AR2 is respectively connected with one end of a resistor R11 and one end of a resistor R12, the other end of the resistor R11 is connected with a standard amplitude signal, the output end of the operational amplifier AR2 is respectively connected with the other end of the resistor R12 and one end of a resistor R13, the other end of the resistor R13 is respectively connected with a pin 6 and a pin 7 of an NE555 chip U1 and the positive electrode of an electrolytic capacitor E4, the pin 2, the pin 4 and the pin 8 of the NE555 chip U1 are connected with a power supply +5V, the pin 5 of the NE555 chip U1 is connected with the positive electrode of the electrolytic capacitor E2, the positive electrode of a MOS tube Q1, the other end of the resistor R14, one end of a grounding resistor R15 and one end of a grounding capacitor C10, and the negative electrode of the electrolytic capacitor E4, the negative electrode of the electrolytic capacitor E2, the electrolytic capacitor E3 and the pin 1 of the NE555 chip U1 are all connected with the ground.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages;
the method comprises the steps that 1, a weak signal in a received network information transmission channel is filtered by a pi-type filter and then is added to a base electrode of a triode Q1, a resistor R1 and a resistor R2 are base bias resistors of the triode Q1, a capacitor C2 is added between the base electrode and a collector electrode of the triode Q1, the weak signal is a neutralization capacitor, an emitter electrode of the triode Q1 is respectively connected with one end of a bypass capacitor C4 and one end of an emitter electrode resistor R4, amplification is carried out, the collector electrode of the triode Q1 outputs, the triode Q1, an inductor L2, an inductor L6 and a capacitor C5 form an oscillator to generate an oscillation signal to carry out distortion compensation and primary amplification, meanwhile, a primary amplification signal acquired by a resistor R14 enters a filter circuit formed by an operational amplifier AR3, a resistor R15 and a capacitor C10, the external interference signal is filtered and then is fed back to the base electrode of the triode Q1 through a voltage stabilizing tube Z3 string inductor L5, and signals meeting the amplitude and frequency requirements of a later-stage circuit are output;
2, filtering out the interference of external noise by an LC filter circuit, avoiding the interference of signals with other frequencies by a band-pass filter, carrying out Boost secondary amplitude modulation by a Boost circuit consisting of an inductor L4, an MOS tube Q1, a diode D2, a resistor R14 and a resistor R15, triggering and conducting a thyristor VTL1 when the output signal does not meet the standard signal 0V to +5V received by a server for an analysis system, enabling the signal to enter a subtracter with an operational amplifier AR2 as a core to carry out difference value operation with the standard amplitude signal to obtain a difference value signal, generating a PWM pulse signal which is in direct proportion to the amplitude of the difference value signal by a pulse width modulation circuit consisting of the resistor R13, an NE555 chip U1, an electrolytic capacitor E2, an electrolytic capacitor E3 and an E4, and coupling the PWM pulse signal to the grid electrode of the MOS tube Q1 to control the conducting or cutting off of the MOS tube Q1 so as to control the precision of the secondary amplitude modulation, and compensating the problem of signal attenuation in channel transmission, so that a terminal server can effectively receive the signal in a data transmission channel.
Drawings
Fig. 1 is a circuit block diagram of the present invention.
Fig. 2 is a schematic circuit diagram of the present invention.
FIG. 3 is a signal flow diagram of a Boost circuit of the present invention.
Detailed Description
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the embodiments, which proceeds with reference to the accompanying figures 1-3. The following embodiments are described in detail with reference to the drawings.
Exemplary embodiments of the present invention will be described below with reference to the accompanying drawings.
The first embodiment of the network information analysis system comprises a regeneration receiving circuit, a filter circuit and a signal amplitude modulation circuit, wherein weak signals in a network information transmission channel received by the regeneration receiving circuit are filtered by a pi-shaped filter formed by a capacitor C1, a capacitor C3 and an inductor L1 and then added to a base electrode of a triode Q1, wherein a resistor R1 and a resistor R2 are base bias resistors of the triode Q1, a capacitor C2 is added between the base electrode and a collector electrode of the triode Q1 and is a neutralization capacitor, an emitter electrode of the triode Q1 is respectively connected with one end of a bypass capacitor C4 and one end of an emitter resistor R4 for amplification, the collector electrode of the triode Q1 outputs, the triode Q1, an inductor L2, an inductor L6 and a capacitor C5 form an oscillator to generate oscillation signals (transmitting frequency signals during network information transmission), distortion compensation and primary amplification are carried out on the weak signals in the received network information transmission channel, meanwhile, the primary amplified signal collected by the resistor R14 enters a filter circuit formed by an operational amplifier AR3, a resistor R15 and a capacitor C10, the external interference signal is filtered and then fed back to the base electrode of the triode Q1 through a voltage stabilizing tube Z3 series inductor L5, the primary amplified signal is ensured to meet the requirements of the amplitude and the frequency of a later-stage circuit, then enters the filter circuit, the external noise interference is filtered through an LC filter circuit formed by the inductor L3 and the capacitor C6, enters a band-pass filter formed by the operational amplifier AR1, the resistors R6-R8, the capacitor C7 and the capacitor C8 for frequency selection, only the frequency of the primary amplified signal is allowed to pass, the signal outside the frequency range is blocked, namely the signal is output after the interference of other frequency signals is avoided, finally enters a signal amplitude modulation circuit, the Boost secondary amplitude modulation is carried out through a Boost circuit formed by the inductor L4, the MOS tube Q1, the diode D2, the resistor R14 and the resistor R15, when the output signal does not meet the standard signal 0V to +5V received by the server for the analysis system, the thyristor VTL1 is triggered to be conducted, the signal enters a subtracter taking the operational amplifier AR2 as a core to carry out difference value operation with the standard amplitude signal to obtain a difference value signal, then a pulse width modulation circuit consisting of a resistor R13, an NE555 chip U1, electrolytic capacitors E2, E3 and E4 generates a PWM pulse signal in direct proportion to the amplitude of the difference value signal, the PWM pulse signal is coupled to the grid electrode of the MOS tube Q1 to control the conduction or the cut-off of the MOS tube Q1, so that the accuracy of secondary amplitude modulation is controlled, and the terminal server can effectively receive the signal in the data transmission channel.
In the second embodiment, on the basis of the first embodiment, the signal amplitude modulation circuit receives the signal output by the filter circuit, and performs Boost two-stage amplitude modulation output through a Boost circuit formed by an inductor L4, a MOS transistor Q1, a diode D2, a resistor R14 and a resistor R15, wherein a voltage division circuit formed by the resistor R14 and the resistor R15 provides a gate voltage for the MOS transistor Q1, and discharges through a capacitor C10 to start the MOS transistor Q1 to be in a conducting state, the signal amplitude modulation circuit outputs a signal which is the product of the signal output by the filter circuit and the conducting time of the MOS transistor Q1, and when the output signal does not meet the standard signal 0V to +5v received by the server for an analysis system, the voltage regulator tube Z2 or the voltage regulator tube Z1 breaks down, so that a trigger circuit formed by the thyristor VTL1, the voltage regulator tube Z2, the resistor R9 and the capacitor C10 is conducted or a trigger circuit formed by the thyristor VTL1, the voltage regulator tube Z1, the resistor R11 and the capacitor C10 is conducted, (the conduction angle of the thyristor VTL1 can be regulated by a resistor R9 and a resistor R11, namely, the voltage of the conduction of the thyristor VTL1 is regulated), after the thyristor VTL1 is triggered and turned on, a signal is connected to the non-inverting input end of an operational amplifier AR2 through an anode, a cathode and a resistor R10 of the thyristor VTL1, difference operation is carried out on the non-inverting input end standard amplitude signal (standard signal 0V to +5V received by a server for an analysis system) to obtain a difference signal, then a PWM pulse signal which is proportional to the amplitude of the difference signal is generated by a pulse width modulation circuit consisting of a resistor R13, an NE555 chip U1, an electrolytic capacitor E2, an E3 and an E4 and is coupled to the grid electrode of a MOS tube Q1, the conduction or cut-off of the MOS tube Q1 is controlled, the accuracy of the two-stage amplitude modulation is controlled by controlling the precision of the resistor R13 and the electrolytic capacitor E4, the value of the electrolytic capacitor E2 is regulated to be a time constant, the width of a control pulse of the 555 chip U1 is regulated within a time constant, the voltage signal amplitude input by the NE555 chip U1 is changed to make the output pulse width of the NE555 chip U1 be in direct proportion to the input voltage, the MOS transistor comprises a MOS transistor Q1 and a diode D1, the drain electrode of the MOS transistor Q1, the cathode of the diode D1 and one end of a resistor R14 are connected with the output end of an operational amplifier AR1, the source electrode of the MOS transistor Q1 and the anode of the diode D1 are respectively connected with one end of a grounding inductor L4 and the cathode of a diode D2, the anode of the diode D2 is connected with a signal output port, the anode of a thyristor VTL1, the cathode of the voltage stabilizing tube Z1 and the anode of the voltage stabilizing tube Z2, the control electrode of the thyristor VTL1 is respectively connected with the anode of the voltage stabilizing tube Z1, one end of a grounding resistor R11, one end of a grounding capacitor C9, one end of a resistor R9, the other end of the resistor R9 is connected with the cathode of the voltage stabilizing tube Z2, one end of a cathode of the thyristor VTL1 is connected with one end of a resistor R10, and the other end of the resistor R10 is connected with the same phase input end of the operational amplifier AR2, the inverting input end of the operational amplifier AR2 is respectively connected with one end of a resistor R11 and one end of a resistor R12, the other end of the resistor R11 is connected with a standard amplitude signal, the output end of the operational amplifier AR2 is respectively connected with the other end of the resistor R12 and one end of a resistor R13, the other end of the resistor R13 is respectively connected with a pin 6 and a pin 7 of an NE555 chip U1 and the positive electrode of an electrolytic capacitor E4, the pin 2, the pin 4 and the pin 8 of the NE555 chip U1 are connected with a power supply +5V, the pin 5 of the NE555 chip U1 is connected with the positive electrode of the electrolytic capacitor E2, the positive electrode of a MOS tube Q1, the other end of the resistor R14, one end of a grounding resistor R15 and one end of a grounding capacitor C10, and the negative electrode of the electrolytic capacitor E4, the negative electrode of the electrolytic capacitor E2, the electrolytic capacitor E3 and the pin 1 of the NE555 chip U1 are all connected with the ground.
In the third embodiment, on the basis of the second embodiment, the regenerative receiving circuit receives the weak signal in the network information transmission channel, filters the external interference signal by a pi-type filter formed by a capacitor C1, a capacitor C3 and an inductor L1, and then adds the filtered external interference signal to the base of a triode Q1, wherein a resistor R1 and a resistor R2 are base bias resistors of the triode Q1, a capacitor C2 is added between the base and a collector of the triode Q1, which is a neutralization capacitor, an emitter of the triode Q1 is respectively connected with one end of a bypass capacitor C4 and one end of an emitter resistor R4, amplifies the weak signal, an oscillator is formed by the collector output of the triode Q1, an inductor L6 and the capacitor C5 to generate an oscillation signal (an emission frequency signal when network information is emitted), and performs distortion compensation and primary amplification on the weak signal in the received network information transmission channel, meanwhile, the primary amplified signal collected by the resistor R14 enters a filter circuit formed by the operational amplifier AR3, the resistor R15 and the capacitor C10, external interference signals are filtered and fed back to the base electrode of the triode Q1 through the voltage stabilizing tube Z3 and the inductor L5, the primary amplified signal is ensured to meet the requirements of the amplitude and the frequency of a later-stage circuit, the primary amplified signal comprises an inductor L1, a capacitor C1 and a capacitor C2, the left end of the inductor L1, one end of the capacitor C1 and one end of the capacitor C2 are all used for receiving weak signals in a network information transmission channel, the right end of the inductor L1 is respectively connected with one end of the capacitor C3, one end of the resistor R2, one end of the resistor R1, one end of the inductor L5 and the base electrode of the triode Q1, the emitter of the triode Q1 is respectively connected with one end of the capacitor C4 and one end of the resistor R4, the other end of the capacitor C1, the other end of the resistor C3, the other end of the resistor R2 and the other end of the resistor C4 are all connected with the ground, the collector of the triode Q1 is respectively connected with the other end of the capacitor C2, one end of the inductor L2 and one end of the grounding capacitor C5, the other end of the inductor L2 is respectively connected with one end of the grounding inductor L6 and one end of the resistor R14, the other end of the resistor R1 and the other end of the resistor R3 are connected with a power supply +5V, the other end of the resistor R14 is connected with the in-phase input end of the operational amplifier AR3, the inverting input end of the operational amplifier AR3 is respectively connected with one end of the resistor R15 and one end of the capacitor C10, the output end of the operational amplifier AR3 is respectively connected with the other end of the resistor R15, the other end of the capacitor C10 and the negative electrode of the voltage stabilizing tube Z3, and the positive electrode of the voltage stabilizing tube Z3 is connected with the other end of the inductor L5;
the filtering circuit receives signals output by the regeneration receiving circuit, after interference of external noise is filtered by an LC filtering circuit formed by an inductor L3 and a capacitor C6, the signals enter a band-pass filter formed by an operational amplifier AR1, resistors R6-R8, a capacitor C7 and a capacitor C8 for frequency selection, only the frequencies of the signals after primary amplification pass through, signals outside the frequency range are blocked, namely, signals with other frequencies are prevented from being interfered and then output.
When the invention is particularly used, weak signals in a network information transmission channel received by a regeneration receiving circuit are filtered by a pi-type filter formed by a capacitor C1, a capacitor C3 and an inductor L1 and then added to the base electrode of a triode Q1, wherein a resistor R1 and a resistor R2 are base bias resistors of the triode Q1, a capacitor C2 is added between the base electrode and a collector electrode of the triode Q1 and is a neutralization capacitor, the emitter electrode of the triode Q1 is respectively connected with one end of a bypass capacitor C4 and one end of an emitter resistor R4 for amplification, the collector electrode of the triode Q1 outputs an oscillation signal (an emission frequency signal when network information is emitted) formed by the triode Q1, the inductor L2, the inductor L6 and the capacitor C5, distortion compensation is carried out on the weak signals in the received network information transmission channel, the primary amplification signal is carried out, meanwhile, the primary amplification signal acquired by a resistor R14 enters a filter circuit formed by an operational amplifier AR3, a resistor R15 and a capacitor C10, the primary amplification signal is fed back to the base electrode of the triode Q1 through a voltage stabilizing tube Z3 after the external interference signal is filtered, the primary amplification signal is output, and the distortion frequency compensation circuit is satisfied; then enters a filter circuit, after the interference of external noise is filtered by an LC filter circuit formed by an inductor L3 and a capacitor C6, the filtered interference enters a band-pass filter formed by an operational amplifier AR1, resistors R6-R8, a capacitor C7 and a capacitor C8 for frequency selection, only the frequency of signals after primary amplification is allowed to pass through, signals outside the frequency range are blocked, namely, the interference of other frequency signals is avoided, the signals are output, finally, the signals enter a signal amplitude modulation circuit, the signals enter a Boost circuit formed by an inductor L4, a MOS tube Q1, a diode D2, a resistor R14 and a resistor R15 for boosting and secondary amplitude modulation, the output signals do not meet the standard signal 0.5 V+5V received by a server for an analysis system, a thyristor VTL1 triggers and is conducted, the signals enter a subtracter with the operational amplifier AR2 as a core for carrying out difference operation with the standard amplitude signal, a pulse width modulation circuit formed by a resistor R13, a NE555 chip U1, an electrolytic capacitor E2 and E3 and E4 generates pulse signals which are in proportion to the amplitude of the difference signal amplitude, the pulse width modulation circuit is coupled to the grid electrode of a MOS tube Q1, the control the MOS tube Q1 is conducted or the signal is controlled, the signal in the terminal of the PWM signal is attenuated by the PWM signal is controlled, and the signal in the terminal is attenuated by the terminal of the signal is effectively transmitted.
While the invention has been described in connection with certain embodiments, it is not intended that the invention be limited thereto; for those skilled in the art to which the present invention pertains and the related art, on the premise of based on the technical scheme of the present invention, the expansion, the operation method and the data replacement should all fall within the protection scope of the present invention.
Claims (1)
1. A network information analysis system comprises a regeneration receiving circuit, a filter circuit and a signal amplitude modulation circuit, and is characterized in that weak signals in a network information transmission channel received by the regeneration receiving circuit are positively fed back through an oscillator taking a triode Q1 as a core, the weak signals in the received network information transmission channel are subjected to distortion compensation and primary amplification, an operational amplifier AR3 is applied to feed back primary amplification signals to an input end of the oscillator taking the triode Q1 as the core, the primary amplification signals meet the amplitude and frequency requirements of a later stage circuit, the primary amplification signals enter the filter circuit, the external interference is filtered through LC (inductance-capacitance) filter, the band-pass filter taking the operational amplifier AR1 as the core selects frequencies, only the frequencies of the primary amplification signals are allowed to pass, signals outside the frequency range are blocked, finally the primary amplification signals enter the signal amplitude modulation circuit, the secondary amplitude modulation is carried out through a Boost circuit consisting of an inductor L4, a MOS (metal oxide semiconductor) tube Q1, a diode D2, a resistor R14 and a resistor R15, when the output signals do not meet the standard signals 0 V+5V received by a server for an analysis system, the thyristor L1 triggers on, the signals enter the operational amplifier to enter the MOS 2 to be converted into the standard signals of a subtracter to be controlled to be the amplitude, the difference value of the PWM (pulse width modulation) or the difference value of the Q1, and the difference value is controlled to be converted to be the PWM (pulse width modulation) to be the Q1, and the difference value is controlled to be the amplitude-modulated to be the difference;
the regeneration receiving circuit comprises an inductor L1, a capacitor C1 and a capacitor C2, wherein the left end of the inductor L1, one end of the capacitor C1 and one end of the capacitor C2 are respectively connected with one end of a capacitor C3, one end of a resistor R2, one end of a resistor R1, one end of a resistor L5 and a base electrode of a triode Q1, an emitter electrode of the triode Q1 is respectively connected with one end of a capacitor C4 and one end of a resistor R4, the other end of the capacitor C1, the other end of the capacitor C3, the other end of the resistor R2, the other end of the capacitor C4 and the other end of the resistor R4 are respectively connected with ground, a collector electrode of the triode Q1 is respectively connected with the other end of the capacitor C2, one end of the inductor L2 and one end of a grounding capacitor C5, the other end of the inductor L2 is respectively connected with one end of a grounding inductor L6, the other end of a resistor R14, the other end of the resistor R1 and the other end of the resistor R3 are connected with a power supply +5V, the other end of the resistor R14 is connected with a non-inverting input end of an operational amplifier AR3, the inverting input end of the operational amplifier AR3 is respectively connected with an inverting end of the resistor R15, the output end of the resistor R3 is connected with the resistor C10, and the other end of the output end of the resistor R3 is connected with the positive end of the resistor Z3 is respectively connected with the resistor Z3;
the filter circuit comprises an inductor L3, the left end of the inductor L3 is connected with an adjustable end of a potentiometer RP1, the right end of the inductor L3 is respectively connected with one end of a grounding capacitor C6 and one end of a resistor R6, the other end of the resistor R6 is respectively connected with one end of a grounding resistor R7, one end of a capacitor C7 and one end of a capacitor C8, the other end of the capacitor C8 is respectively connected with an inverting input end of an operational amplifier AR1 and one end of a resistor R8, the other end of the capacitor C7 is respectively connected with the other end of the resistor R8 and the output end of the operational amplifier AR1, and the non-inverting input end and the gnd end of the operational amplifier AR1 are connected with the ground;
the signal amplitude modulation circuit comprises a MOS tube Q1 and a diode D1, wherein the drain electrode of the MOS tube Q1, the cathode of the diode D1 and one end of a resistor R14 are connected with the output end of an operational amplifier AR1, the source electrode of the MOS tube Q1 and the anode of the diode D1 are respectively connected with one end of a grounding inductor L4 and the cathode of the diode D2, the anode of the diode D2 is connected with a signal output port, the anode of a thyristor VTL1, the cathode of a voltage stabilizing tube Z1 and the anode of a voltage stabilizing tube Z2, the control electrode of the thyristor VTL1 is respectively connected with the anode of the voltage stabilizing tube Z1, one end of a grounding resistor R11, one end of a grounding capacitor C9 and one end of a resistor R9, the other end of the resistor R9 is connected with the cathode of the voltage stabilizing tube Z2, the cathode of the thyristor VTL1 is connected with one end of a resistor R10, the other end of the resistor R10 is connected with the same phase input end of the operational amplifier AR2, the inverting input end of the operational amplifier AR2 is respectively connected with one end of a resistor R11 and one end of a resistor R12, the other end of the resistor R11 is connected with a standard amplitude signal, the output end of the operational amplifier AR2 is respectively connected with the other end of the resistor R12 and one end of a resistor R13, the other end of the resistor R13 is respectively connected with a pin 6 and a pin 7 of an NE555 chip U1 and the positive electrode of an electrolytic capacitor E4, the pin 2, the pin 4 and the pin 8 of the NE555 chip U1 are connected with a power supply +5V, the pin 5 of the NE555 chip U1 is connected with the positive electrode of the electrolytic capacitor E2, the positive electrode of a MOS tube Q1, the other end of the resistor R14, one end of a grounding resistor R15 and one end of a grounding capacitor C10, and the negative electrode of the electrolytic capacitor E4, the negative electrode of the electrolytic capacitor E2, the electrolytic capacitor E3 and the pin 1 of the NE555 chip U1 are all connected with the ground.
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