CN108987404B

CN108987404B - Three-dimensional memory and manufacturing method thereof

Info

Publication number: CN108987404B
Application number: CN201810810624.8A
Authority: CN
Inventors: 孟洁云; 盖晨光; 张焕焕; 曹礼敏
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2018-07-23
Filing date: 2018-07-23
Publication date: 2020-08-04
Anticipated expiration: 2038-07-23
Also published as: CN108987404A

Abstract

The invention relates to a three-dimensional memory and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a semiconductor structure having a core region with an array common source; forming a first contact that vertically penetrates from an upper surface of the semiconductor structure, the first contact contacting the array common source; forming an insulating layer on the upper surface of the semiconductor structure; and forming a second contact portion vertically penetrating from a surface of the insulating layer, the second contact portion contacting the first contact portion.

Description

Three-dimensional memory and manufacturing method thereof

Technical Field

The present invention generally relates to semiconductor manufacturing methods, and more particularly to a method for fabricating a three-dimensional memory device and a three-dimensional memory device.

Background

To overcome the limitations of the two-dimensional memory device, the industry has developed a memory device having a three-dimensional (3D) structure to increase integration density by arranging memory cells three-dimensionally over a substrate.

In a three-dimensional memory device such as a 3D NAND flash memory, an Array (Array) area includes a core (core) area and a word line connection area. The core area has an array of memory cells therein. The word line connecting region is used for leading out a contact part of a gate layer of each layer of memory cells in the memory cell array. These gate layers are used as word lines of the memory cell array to perform programming, erasing, reading, etc. Different structures in the Array region, such as a channel layer in a channel hole in a memory cell Array, a gate layer of a word line connection region, and an Array Common Source (ACS), need to be reached through contact holes that extend vertically downward from the surface in the Array region. And then filling the contact holes with a conductive material to form connecting lines.

However, because the patterns and depths of the structures such as the channel hole, the gate layer, the array common source and the like are different, the forming process of the contact hole is difficult, and the process is not easy to control. Particularly, in the ACS area, the cross section of a contact hole connected with the ACS is elliptical, the medium needing etching for forming the contact hole is thick, and the elliptical pattern is easy to distort and deform in the deep hole etching process. The deformed contact hole is not conducive to a subsequent process of filling the contact hole with a conductive material, which may not be uniformly filled, thereby causing degradation of the electrical performance of the memory.

Disclosure of Invention

The invention provides a three-dimensional memory and a manufacturing method thereof, which can reduce the difficulty of etching a contact hole.

The technical scheme adopted by the invention for solving the technical problems is to provide a method for manufacturing a three-dimensional memory, which comprises the following steps: providing a semiconductor structure having a core region with an array common source; forming a first contact that vertically penetrates from an upper surface of the semiconductor structure, the first contact contacting the array common source; forming an insulating layer on the upper surface of the semiconductor structure; and forming a second contact portion vertically penetrating from a surface of the insulating layer, the second contact portion contacting the first contact portion.

In an embodiment of the invention, the core region further has a channel structure, the semiconductor structure has a third contact portion vertically penetrating from an upper surface of the semiconductor structure, and the third contact portion contacts the channel structure; the method forms a second contact part vertically penetrating from the surface of the insulating layer, and simultaneously comprises the following steps: and forming a fourth contact part vertically penetrating from the surface of the insulating layer, wherein the fourth contact part is contacted with the third contact part.

In an embodiment of the present invention, the step of forming the first contact portion vertically penetrating from the upper surface of the semiconductor structure includes: a plurality of columnar first contacts are formed on each array common source, and the first contacts are arranged at intervals along the extending direction of the array common source.

In an embodiment of the present invention, the step of forming the first contact portion vertically penetrating from the upper surface of the semiconductor structure includes: one first contact portion is formed on each array common source and extends along the extending direction of the array common source.

In an embodiment of the present invention, the step of forming the first contact portion vertically penetrating from the upper surface of the semiconductor structure includes: forming a first contact hole vertically penetrating from an upper surface of the semiconductor structure to the array common source; and filling a conductive material in the first contact hole to form the first contact portion.

In an embodiment of the invention, a thickness of the array common source in an extending direction of the semiconductor structure is larger than a size of the contact hole in the thickness direction.

In an embodiment of the present invention, the step of forming the second contact portion vertically penetrating from the surface of the insulating layer includes: forming a second contact hole vertically penetrating from the surface of the insulating layer to reach the first contact portion; and filling a conductive material in the second contact hole to form the second contact portion.

In an embodiment of the present invention, the step of forming the second contact portion vertically penetrating from the surface of the insulating layer includes: forming a second contact hole vertically penetrating from an upper surface of the semiconductor structure to reach the first contact portion; and filling a conductive material in the second contact hole to form the second contact portion; wherein the step of forming the first contact hole and the step of forming the second contact hole are performed in different etching steps.

In an embodiment of the present invention, in the step of providing the semiconductor structure, the semiconductor structure further has a word line connection region having a plurality of spaced gate layers, and a plurality of fifth contacts perpendicular to an upper surface of the semiconductor structure, each fifth contact contacting a corresponding gate layer; the method forms a second contact part vertically penetrating from the surface of the insulating layer, and simultaneously comprises the following steps: and forming a sixth contact part vertically penetrating from the surface of the insulating layer, wherein the sixth contact part is in contact with the fifth contact part.

The invention also provides a three-dimensional memory device, which comprises a core region, wherein the core region is provided with an array common source, a vertical first contact part contacting the top of the array common source and a second contact part contacting the first contact part, and the thickness of the array common source in the extending direction of the three-dimensional memory device is larger than the size of the second contact part in the thickness direction.

In an embodiment of the invention, each array common source has a plurality of columnar first contacts, and the first contacts are arranged at intervals along an extending direction of the array common source.

In an embodiment of the invention, each array common source has one first contact, and the first contact extends along an extending direction of the array common source.

In an embodiment of the invention, the core region further has a channel structure, a vertical third contact contacting a top of the channel structure, and a fourth contact contacting the third contact.

In an embodiment of the present invention, the three-dimensional memory device further has a word line connection region having a plurality of spaced gate layers, a vertical fifth contact contacting a top of each gate layer, and a sixth contact contacting the fifth contact.

In an embodiment of the invention, a thickness of the array common source in an extending direction of the three-dimensional memory device is 100-500nm, and a size of the first contact in the thickness direction is 80-280 nm.

In an embodiment of the invention, the height of the first contact portion is 180-280nm, and the height of the second contact portion is 100-250 nm.

By adopting the technical scheme, the contact part for leading out the array common source and the contact hole thereof are formed through a plurality of steps, so that the thickness of the medium etched in each step is reduced when the contact hole is formed, and the difficulty of an etching process and an in-hole deposition process is reduced. Furthermore, the conductive material of the contact part of the array common source is regular, and the yield of the memory is improved.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

fig. 1 is a flowchart of a method for fabricating a three-dimensional memory according to an embodiment of the invention.

Fig. 2A-2D are schematic cross-sectional views in an exemplary process of a method of fabricating a three-dimensional memory according to an embodiment of the invention.

Fig. 3A and 3B are schematic cross-sectional views from another perspective of the semiconductor structure shown in fig. 2B and 2D, respectively, according to an embodiment of the invention.

Fig. 4A-4B are cross-sectional views illustrating an exemplary process of forming a second contact in accordance with an embodiment of the present invention.

Fig. 5A-5B are cross-sectional views illustrating exemplary processes of forming third through fifth contacts according to an embodiment of the invention.

Fig. 6A and 6B are schematic cross-sectional views from another perspective of the semiconductor structure shown in fig. 2B and 2D, respectively, according to another embodiment of the present invention.

Fig. 7A-7B are schematic cross-sectional views in an exemplary process of a method of fabricating a three-dimensional memory as a comparison.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

Some embodiments of the present invention describe methods of fabricating three-dimensional memory devices, and in particular methods of forming contacts (contacts) in a core region (core area) and word line connection regions of a three-dimensional memory device. The method described in some embodiments of the invention can reduce the difficulty of etching the contact hole and improve the regularity thereof, thereby ensuring the quality of the subsequently formed contact part. Some embodiments of the present invention describe three-dimensional memory devices with better yield.

Fig. 1 is a flowchart of a method of fabricating a three-dimensional memory device according to a first embodiment of the present invention. Fig. 2A to 2D are schematic process diagrams illustrating a method of fabricating a three-dimensional memory device according to a first embodiment of the present invention. A method of fabricating a three-dimensional memory device of the present embodiment is described below with reference to fig. 1 to 2D.

At step 102, a semiconductor structure is provided.

The semiconductor structure is at least a portion of a structure that will be used in subsequent processing to ultimately form a three-dimensional memory device. The semiconductor structure may include an array region, which may include a core region and a word line (word line) connection region. The core region is a region including memory cells, and the word line connection region is a region including word line connection circuits. The array region may have a substrate and stacked layers, as viewed in a vertical direction. The stacked layers may include gate layers and spacer layers stacked alternately. An array of vertical channel structures and an array common source are formed on the stacked layers of the core region. A stepped structure may be formed on the stacked layers of the word line connection region for leading out a contact.

In the partial cross-sectional view of the semiconductor structure illustrated in fig. 2A, the semiconductor structure 200a may include a core region 210 and a wordline connection region 220. These regions 210-220 may be disposed on a substrate (not shown). The substrate is typically a silicon-containing substrate such as Si, SOI (silicon on insulator), SiGe, Si: C, etc., although this is not a limitation. Some doped wells, such as N-wells or P-wells, may be provided on the substrate as desired.

With continued reference to fig. 2A, both the core region 210 and the word line connection region 220 are provided with a stack layer 201, and the stack layer 201 may include gate layers 201a and spacer layers 201b that are alternately stacked. A first insulating layer 202 may be formed on the stack layer 201. A spacer layer 201b is provided between each two gate layers 201 a. In an embodiment of the present invention, the material of the gate layer 201a may be polysilicon or a metal (e.g., tungsten). The material of the spacer layer 201b is, for example, silicon oxide. The material of the first insulating layer 202 may be selected from various materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, and the like. An array of vertical channel structures 211 and an array common source 212 are formed on the stacked layers of the core region 210, only a part of which is illustrated. The channel structure 211 may include a vertical channel layer within a channel hole and a conductive plug (plug) as a drain over the channel layer. The array common source 212 and the stacked layer 201 can be electrically isolated by an insulating layer 213. The channel structure 211 may use a known structure and is not expanded here. A staircase structure 221 may be formed on the stacked layers of the word line connection region 220.

Although not a necessary structure of the present invention, in the core region 210, the semiconductor structure 200a may have a plurality of third contacts 214 vertically penetrating from the upper surface S1 thereof, each third contact 214 contacting each channel structure 211. Here, the upper surface S2 of the array common source 212 is lower than the upper surface S1 of the semiconductor structure 200 a. That is, the upper surface S2 of the array common source 212 and the upper surface S1 of the semiconductor structure 200a have a height difference of H1; accordingly, the upper surface S2 of the array common source 212 has a height difference with the upper surface of the third contact 214. This height difference H1 may be 180-280 nm. In addition, at the word line connection region 220, the semiconductor structure 200a may have a plurality of fifth contacts 222 perpendicular to its upper surface S1, each fifth contact 222 contacting a corresponding gate layer, such as 201 a. The upper surface S3 of the fifth contact 222 may be lower than the upper surface S1 of the semiconductor structure 200 a. That is, the upper surface S3 of the fifth contact 222 and the upper surface S1 of the semiconductor structure 200a have a height difference of H2.

The material of the array common source 212, the

respective contacts

214, 215, and 222 is a conductive material, such as a metal. An exemplary metal is tungsten.

Although exemplary configurations of the initial semiconductor structure are described herein, it will be appreciated that one or more features may be omitted, substituted, or added to the semiconductor structure. For example, the stepped structure of the word line connection region for leading out the contact may be omitted or replaced by another structure. In addition, the materials of the illustrated layers are only exemplary, and for example, the spacer layer 201b may also be selected from other non-conductive materials available in a three-dimensional NAND memory, such as amorphous silicon, amorphous carbon, and the like.

At step 104, a first contact is formed that penetrates vertically from an upper surface of the semiconductor structure. The first contact contacts the array common source.

In this step, the first contact is formed on the array common source separately to reduce the depth of the hole etched for forming the contact.

In the partial cross-sectional view of the semiconductor structure illustrated in fig. 2B, a first contact 215 vertically penetrating from the upper surface S1 of the semiconductor structure 200B is formed in the core region 210, and the first contact 215 contacts the array common source 212. FIG. 3A is a cross-sectional view of another perspective of the semiconductor structure 200B shown in FIG. 2B, in accordance with one embodiment of the present invention. Referring to fig. 2B and 3A, a plurality of pillar-shaped first contacts 215 are formed on each array common source 212. These first contacts 215 are arranged at intervals along the extending direction of the array common source 212. The material of the first contact 215 is a conductive material, such as metal tungsten. In one embodiment, the height of the first contact portion 215 may be 180 nm and 280 nm. The upper surface of the first contact 215 will reach the upper surface S1 of the semiconductor structure 200b, thereby filling in the height difference H1.

At step 106, an insulating layer is formed on the upper surface of the semiconductor structure.

In this step, an insulating layer is overlaid on the semiconductor structure to form a subsequent conductive interconnect structure.

In the partial cross-sectional view of the semiconductor structure illustrated in FIG. 2C, a second insulating layer 203 is formed over the semiconductor structure 200C, the second insulating layer 203 overlying the previous first insulating layer 202, the manner of overlying the second insulating layer 203 may include deposition, suitable processes may be selected from a variety of known deposition processes, such as L PCVD, PECVD, HDPCVD, MOCVD, MBE, A L D, the material of the second insulating layer 203 may be selected from a variety of materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, and the like, and the material of the second insulating layer 203 may be the same as or different from the first insulating layer 202.

At step 108, a second contact is formed that penetrates vertically from the upper surface of the semiconductor structure. The second contact portion contacts the first contact portion.

In this step, another layer contact may be formed for the array common source. In addition, another layer contact can also be formed for the channel structure. In the partial cross-sectional view of the semiconductor structure illustrated in fig. 2D, a fourth contact 216 and a second contact 217 are formed on the semiconductor structure 200D to vertically penetrate from the upper surface thereof, thereby contacting the third contact 214 and the first contact 215, respectively. The fourth contact 216 may be aligned with the third contact 214 and the second contact 217 may be aligned with the first contact 215. The material of the fourth and

second contacts

216, 217 may be a conductive material, such as metallic tungsten. In one embodiment, the height of the fourth and

second contacts

216, 217 may be 100 nm and 250 nm.

Fig. 3B is a cross-sectional view of another perspective of the semiconductor structure 200D shown in fig. 2D according to an embodiment of the invention. As shown with reference to fig. 2D and 3B, a cylindrical second contact portion 217 is formed on each cylindrical first contact portion 215. These fourth contacts 217 are also arranged at intervals along the extending direction of the array common source 212.

In addition, when the fifth contact 222 of the word line connection region 220 is present, a sixth contact 223 vertically penetrating from the upper surface of the semiconductor structure is also formed in step 108. The sixth contact portion 223 contacts the fifth contact portion 223.

In an embodiment of the present invention, the fourth contact portion 216 and the sixth contact portion 223 may be cylindrical, and the second contact portion 217 may be an elliptic cylinder.

In the embodiment, the contact part for leading out the array common source and the contact hole thereof are formed through multiple steps, so that the thickness of the medium etched in each step is reduced when the contact hole is formed, and the difficulty of an etching process and an in-hole deposition process is reduced.

Flow charts are used herein to illustrate operations performed by methods according to embodiments of the present application. It should be understood that the preceding operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes. For example, additional holes or slots may be formed in the above process.

The semiconductor structure formed in the above embodiments may be processed by the following conventional steps to obtain a three-dimensional memory. A three-dimensional memory according to an embodiment of the invention is described herein with reference to the semiconductor structure 200d formed in this embodiment. Referring to fig. 2D and 3B, the three-dimensional memory device may include a core region 210, the core region 210 having a channel structure 211, a vertical third contact 214 contacting a top of the channel structure, and a fourth contact 216 contacting the third contact 214. The core region 210 also has an array common-source 212, a vertical first contact 215 contacting the top of the array common-source 212, and a second contact 217 contacting the first contact 215. The thickness Th of the array common source 212 in the extending direction of the three-dimensional memory device is larger than the dimension D of the first contact 215 in the direction of the aforementioned thickness Th. In the present embodiment, each array common-source electrode 212 has a plurality of first contacts 215 having a cylindrical shape, and the first contacts 215 are arranged at intervals along the extending direction of the array common-source electrode 212.

In one embodiment, the first contact portion 215 is an elliptic cylinder, and thus in the present embodiment, the dimension D1 is a length of a short axis of the first contact portion 215 in the direction of the thickness Th.

In one embodiment, the three-dimensional memory may have a word line connection region 220, the word line connection region 220 having a plurality of spaced gate layers 201a, a vertical fifth contact 222 contacting a top of each gate layer 201a, and a sixth contact 222 contacting the fifth contact 221.

Some dimensions in the above structure are exemplified below. It will be appreciated that the dimensions may vary depending on the storage density of the three-dimensional memory device and the process requirements. For example, the thickness Th of the array common source 212 in the extending direction of the three-dimensional memory device is 100-500nm, the dimension D1 of the first contact 215 in the direction of the thickness Th is 80-280nm, and the dimension D2 of the second contact 217 in the direction of the thickness Th is 50-150 nm. And as can be seen in fig. 2D, Th > D1> D2. For example, the height of the first contact 215 is 180 nm and 280nm, and the height of the second contact 217 is 100 nm and 250 nm. The height of the fourth contact portion 216 may be the same as the height of the second contact portion 217.

In the three-dimensional memory device of the embodiment, the conductive materials of the first contact portion 215 and the second contact portion 217 are regular, which is beneficial to improving the yield of the memory.

In comparison, according to the method shown in fig. 7A to 7B, the semiconductor structure 700a includes a core region 710 and a word line connection region 720, and includes a stack layer 701, a first insulating layer 702, and a second insulating layer 703 in a vertical direction. When forming the contact, the hard mask layer 704 and the photoresist pattern 705 are covered, and then contact holes reaching the contact 711, the array common source 712, and the contact 722 are formed by etching through the respective openings 705a of the photoresist pattern 705. Next, as shown in fig. 7B,

contacts

713, 714, and 723 are formed on the semiconductor structure 700B. In this way, the difficulty of forming a deep contact hole above the array common source 712 and forming the corresponding contact 713 is high, which may easily result in poor quality of the contact 713.

Fig. 4A-4B are cross-sectional schematic views of an exemplary process of forming a first contact in accordance with an embodiment of the present invention. An exemplary process of forming the first contact portion is described below with reference to fig. 4A-4B. First, as shown in fig. 4A, a hard mask layer 204 and a photoresist pattern 205 may be formed on the semiconductor structure 200a of fig. 2A, thereby obtaining a semiconductor structure 200a 1. Herein, the hard mask layer 204 may include a Bottom Anti-Reflective Coating (BARC) layer, a Dielectric Anti-Reflective Coating (DARC) layer, and an Amorphous Carbon (AC) layer, but the structure thereof is not limited thereto. The photoresist pattern 205 may have an opening 205a to expose the first insulating layer 201 above the array common source 212. Next, as shown in fig. 4B, a first contact hole 215a is formed to vertically penetrate from the upper surface of the semiconductor structure 200a2 to reach the array common source 212. The first contact hole 215a may be formed using an etching method. The thickness Th of the array common source 212 in the extending direction of the semiconductor structure 200a2 is larger than the dimension D1 of the first contact hole 215a in the direction of the thickness Th. For example, the thickness Th of the array common source 212 in the extending direction of the three-dimensional memory device is 100-500nm, the dimension D1 of the first contact hole 215a in the direction of the thickness Th is 80-280nm, and as can be seen in FIG. 4B, Th > D1. Then, the first contact hole 215a is filled with a conductive material to form a first contact portion 215 as shown in fig. 2B.

Fig. 5A-5B are cross-sectional schematic views of an exemplary process of forming second, fourth, and sixth contacts in accordance with an embodiment of the invention. An exemplary process of forming the second, fourth, and sixth contacts is described below with reference to fig. 5A-5B. First, as shown in fig. 5A, a hard mask layer 206 and a photoresist pattern 207 may be formed on the semiconductor structure 200C of fig. 2C, thereby obtaining a semiconductor structure 200C 1. Here, the hard mask layer 207 may include a bottom anti-reflective coating layer, a dielectric anti-reflective coating layer, and an amorphous carbon layer, but the structure thereof is not limited. The photoresist pattern 207 may have an opening 207a to expose the second insulating layer 202 above the array common source 212. Next, as shown in fig. 5B,

second contact holes

216a and 217a vertically penetrating from the upper surface of the semiconductor structure 200c2 to reach the third contact portion 214 and the first contact portion 215 are formed. Here, the

second contact holes

216a and 217a may be formed using an etching method. The dimension D1 of the first contact hole 215a in the direction of the thickness Th is 80-280nm, and the dimension D2 of the second contact hole 216a in the direction of the thickness Th is 50-150 nm. And as can be seen in fig. 5B, Th > D1> D2. Then, the

second contact holes

216a and 217a are filled with a conductive material to form a fourth contact portion 216 and a second contact portion 217, respectively, as shown in fig. 2D. When necessary, the third contact hole 223a is also formed at the same time as the

second contact holes

216a, 217a are formed; then, the conductive material is filled in the third contact hole 223a while the conductive material is filled in the

second contact holes

216a and 217 a. In fact, the steps of forming the

contact holes

216a, 217a and 223a may be performed together, and the steps of forming the second, fourth and sixth contacts may be performed together.

In an embodiment of the present invention, the step of etching the semiconductor structure shown in fig. 4A to form the first contact hole 215A and the step of etching the second contact hole 216a on the semiconductor structure shown in fig. 5A are performed in different etching steps. The first contact hole 215a and the second contact hole 216a are formed by different etching steps, so that the thickness of the medium etched at each step can be reduced, and the difficulty of the etching process and the in-hole deposition process can be reduced.

In the embodiment of the present invention, the form of the first contact portion formed on the array common source may be changed as long as it can function to raise the height of the upper surface of the array common source. The first contact on each array common source may be one and extend along the extension direction of the array common source. Fig. 6A and 6B are schematic cross-sectional views from another perspective of the semiconductor structure shown in fig. 2B and 2D, respectively, according to another embodiment of the present invention. Referring to fig. 6A, in the semiconductor structure 200b ', the first contact 215' is substantially a conductive wall having the same shape as the array common source 212. It is understood that before forming this first contact 215', a first contact hole extending along the extending direction of the array common source needs to be formed. The first contact hole is in a strip shape from a top view. The first contact hole may also be referred to as a Trench (Trench) at this time. Two edges of the groove are respectively parallel to two edges of the array common source, and the central line of the groove is superposed with the central line of the array common source. Referring next to fig. 6B, a plurality of second contact portions 217 having a cylindrical shape are formed on each of the first contact portions 215'. The second contact portions 217 are arranged at intervals along the extending direction of the first contact portion 215'.

As a variation of the present embodiment, the first contact portion 215' may not be continuous but may be disconnected at some positions.

Other details of the three-dimensional memory device, such as the arrangement of memory cells, the specific structure of the word line connection regions, etc., are not important to the present invention and will not be described herein.

In the context of the present invention, the three-dimensional memory may be a 3D flash memory, e.g. a 3D NAND flash memory.

This application uses specific words to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.

Although the present invention has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A method of fabricating a three-dimensional memory, comprising the steps of:

providing a semiconductor structure having a core region with an array common source, a channel structure, and a word line connection region, the semiconductor structure having a third contact that vertically penetrates from an upper surface of the semiconductor structure, the third contact contacting the channel structure, the word line connection region having a plurality of spaced gate layers and a plurality of fifth contacts that are perpendicular to the upper surface of the semiconductor structure, each fifth contact contacting a corresponding gate layer, the array common source and the fifth contacts being located below the upper surface of the semiconductor structure;

forming a first contact that vertically penetrates from an upper surface of the semiconductor structure, the first contact contacting the array common source;

forming an insulating layer on the upper surface of the semiconductor structure; and

and forming a second contact part, a fourth contact part and a sixth contact part which vertically penetrate through the surface of the insulating layer, wherein the second contact part is contacted with the first contact part, the fourth contact part is contacted with the third contact part, and the sixth contact part is contacted with the fifth contact part.

2. The method of claim 1, wherein forming a first contact that vertically penetrates from an upper surface of the semiconductor structure comprises: a plurality of columnar first contacts are formed on each array common source, and the first contacts are arranged at intervals along the extending direction of the array common source.

3. The method of claim 1, wherein forming a first contact that vertically penetrates from an upper surface of the semiconductor structure comprises: one first contact portion is formed on each array common source and extends along the extending direction of the array common source.

4. The method of claim 1, wherein forming a first contact that vertically penetrates from an upper surface of the semiconductor structure comprises:

forming a first contact hole vertically penetrating from an upper surface of the semiconductor structure to the array common source; and

and filling a conductive material in the first contact hole to form the first contact part.

5. The method of claim 4, wherein a thickness of the array common source in a direction of extension of the semiconductor structure is greater than a dimension of the contact hole in the direction of the thickness.

6. The method of claim 1, wherein forming a second contact that vertically penetrates from a surface of the insulating layer comprises:

forming a second contact hole vertically penetrating from the surface of the insulating layer to reach the first contact portion; and

and filling a conductive material in the second contact hole to form the second contact portion.

7. The method of claim 4, wherein forming a second contact that vertically penetrates from a surface of the insulating layer comprises:

forming a second contact hole vertically penetrating from an upper surface of the semiconductor structure to reach the first contact portion; and

filling a conductive material in the second contact hole to form the second contact portion;

wherein the step of forming the first contact hole and the step of forming the second contact hole are performed in different etching steps.

8. A three-dimensional memory device comprising a core region having an array common source, a vertical first contact contacting a top of the array common source, a second contact contacting the first contact, a channel structure, a vertical third contact contacting the top of the channel structure, a fourth contact contacting the third contact, a word line connection region having a plurality of spaced gate layers, a vertical fifth contact contacting a top of each gate layer, and a sixth contact contacting the fifth contact, wherein a thickness of the array common source in a direction of extension of the three-dimensional memory device is larger than a dimension of the second contact in a direction of the thickness; the upper surface of first contact site and third contact site is parallel and level, the upper surface of second contact site, fourth contact site and sixth contact site is parallel and level.

9. The three-dimensional memory device according to claim 8, wherein each array common source has a plurality of columnar first contacts thereon, the first contacts being arranged at intervals along an extending direction of the array common source.

10. The three-dimensional memory device of claim 8, wherein each array common source has one of the first contacts thereon, the first contact extending along an extending direction of the array common source.

11. The three-dimensional memory device as claimed in claim 8, wherein the thickness of the array common source in the extending direction of the three-dimensional memory device is 100-500nm, and the dimension of the first contact in the thickness direction is 80-280 nm.

12. The three-dimensional memory device as claimed in claim 8, wherein the height of the first contact is 180-280nm, and the height of the second contact is 100-250 nm.