CN108987395A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN108987395A CN108987395A CN201810552747.6A CN201810552747A CN108987395A CN 108987395 A CN108987395 A CN 108987395A CN 201810552747 A CN201810552747 A CN 201810552747A CN 108987395 A CN108987395 A CN 108987395A
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- 230000005669 field effect Effects 0.000 claims abstract description 66
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- 239000000463 material Substances 0.000 claims abstract description 27
- 239000010410 layer Substances 0.000 description 94
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 73
- 229910052710 silicon Inorganic materials 0.000 description 73
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- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 239000007943 implant Substances 0.000 description 7
- 230000036961 partial effect Effects 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 229910044991 metal oxide Inorganic materials 0.000 description 6
- 150000004706 metal oxides Chemical class 0.000 description 6
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- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of semiconductor device, including one first fin field-effect transistor (FinFET) device, first fin field effect transistor device includes an epitaxial layer of the semiconductor material for being formed in multiple fins of a substrate and being formed on fin and the first grid structure across fin, wherein, epitaxial layer forms nonplanar regions and source/drain.Semiconductor device includes one second fin field effect transistor device, and the second fin field effect transistor device includes from being formed in the one of the substrate on the whole fin of plane (substantially planar), the second grid structure for being formed on the on the whole fin of plane and forming an on the whole epitaxial layer of the semiconductor material of the regions and source/drain of plane and the fin across on the whole plane.
Description
Technical field
This disclosure relates to which a kind of semiconductor device, the in particular to semiconductor with fin field-effect transistor (FinFET) fill
It sets.
Background technique
Semiconductor device is used in various electronic applications, such as PC, mobile phone, digital camera and other electronics
Equipment.Semiconductor device usually passes through successive sedimentation insulating layer on a semiconductor substrate or dielectric layer, conductive layer and semiconductor
Material layer, and manufactured using lithographic process patterning a variety of materials layer with being formed on circuit block and element.Perhaps
Multiple ic is fabricated on single a semiconductor crystal wafer, and by the cutting line between cutting integrated circuit with simple grain
(singulate) single a chip (die) on wafer.Single a chip is usually in multi-chip module or other encapsulated types
Individually encapsulated.
With semi-conductor industry enter nanotechnology process nodes with pursue higher device density, higher efficiency and
Lower cost, the challenge from processing procedure and design problem already lead to the development of three dimensional design, such as crystal is imitated in fin field
It manages (FinFET).Fin field-effect transistor is manufactured using thin vertical " fin " (or fin structure) for extending from substrate.Fin
The channel of formula field-effect transistor is formed in this vertical fin.Grid is provided on fin.The advantages of fin field-effect transistor
Including reducing short-channel effect and higher electric current.
Although existing fin field effect transistor device and manufacture fin field effect transistor device method generally for
Its expected purpose is enough, but can not be entirely satisfactory in all respects.
Summary of the invention
The disclosure provides a kind of semiconductor device, including one first fin field-effect transistor (FinFET) device, the first fin
Formula field effect transistor device includes the extension from a substrate multiple fins extended, the semiconductor material being formed on fin
Layer and a first grid structure across fin, epitaxial layers form nonplanar regions and source/drain；And one
Two fin field effect transistor devices, the second fin field effect transistor device include from substrate extend one on the whole the fin of plane,
Be formed on the on the whole fin of plane and formed on the whole an epitaxial layer of the semiconductor material of the regions and source/drain of plane,
An and second grid structure of the fin across on the whole plane.
The disclosure provides a kind of manufacturing method for semiconductor device, including provides a substrate；Base is etched in a first area
Plate, to form multiple fins of one first fin field-effect transistor (FinFET)；The etching substrate in a second area, to be formed
The fin of the on the whole plane of the one of one second fin field-effect transistor (FinFET)；It is formed on fin and the on the whole fin of plane
One epitaxial layer of semiconductor material；It is formed across a first grid structure of nonplanar fin: and be formed across and on the whole put down
One second grid structure of the fin in face, wherein epitaxial layer on fin formed it is adjacent with first grid structure multiple non-flat
The regions and source/drain in face, and the epitaxial layer formation on the fin of on the whole plane is adjacent with second grid structure on the whole
The regions and source/drain of plane.
The disclosure provides a kind of semiconductor device, including one first active area, has one first fin field-effect transistor
(FinFET) device is formed in the first active area, the first fin field effect transistor device include be formed in it is more in a substrate
A fin, an epitaxial layer of the semiconductor material being formed on fin and the first grid structure across fin, wherein
Epitaxial layer forms nonplanar regions and source/drain；One second active area has one second fin field effect transistor device shape
At in the second active area, the second fin field effect transistor device include to be formed in a substrate one on the whole the fin of plane,
Be formed on the on the whole fin of plane and formed on the whole an epitaxial layer of the semiconductor material of the regions and source/drain of plane,
An and second grid structure of the fin across on the whole plane；And a contact point, contact point, which is located at, is formed on the whole plane
Fin above epitaxial layer on, wherein the epitaxial layer of semiconductor material is phosphatization silicon (SiP).
Detailed description of the invention
The viewpoint of the disclosure can preferably understand from subsequent embodiment and attached drawing.Notice different characteristic, which has no, to be illustrated in
This.The size of different characteristic may be increased or decreased arbitrarily with clear discussion.
Fig. 1 is that have showing for the semiconductor device for mixing fin field effect transistor device structure according to the embodiment of the present disclosure
It is intended to.
Fig. 2 is the side schematic view according to the semiconductor device of Fig. 1 of the embodiment of the present disclosure.
Fig. 3 is the schematic diagram according to the layout of the semiconductor device of Fig. 1 of the embodiment of the present disclosure.
Fig. 4 is the sectional view of transistor, the resistance that the various parts being shown in transistor connection are contributed.
Fig. 5 A to Fig. 5 N is the side that the region (OD) is defined according to the mixed oxide of formation in a substrate of the embodiment of the present disclosure
The schematic diagram of method.
Fig. 6 and Fig. 6 A is the schematic diagram for connecting the contact point of epitaxial layer of semiconductor device structure.
Wherein, the reference numerals are as follows:
10~semiconductor device
12~silicon substrate
14~oxide isolation areas
16~fin
18~silicon area
20~surface
22~regions and source/drain
24~regions and source/drain
26a-26c~gate structure
C~width
A~distance
B~distance
50~P well
RV0~resistance
RMD2~resistance
RMD1~resistance
Rcsd~resistance
Rsd~resistance
Rldd~resistance
ROV~resistance
Rch~resistance
200~silicon substrate
202~oxide skin(coating)
204~silicon nitride layer
206~oxide skin(coating)
The region 208~plane OD
210~non-planar the region OD
212~mask layer
212a~modification mask layer
214~protective layer
215a~opening
215b~opening
200a~silicon substrate
202a~portions of oxide layer
204a~partial nitridation silicon layer
206a~portions of oxide layer
216~silicon column
E~height
200b~modification silicon substrate
218a-218d~silicon plane
220a~opening
220b~opening
200c~modification silicon substrate
202b~portions of oxide layer
204b~partial nitridation silicon layer
216b~silicon column
224~protective layer
226~oxide skin(coating)
226a-226d~oxide skin(coating)
228~epitaxial structure
230~epitaxial structure
30~contact point
Specific embodiment
Disclosure below provides many different embodiments to implement the different characteristic of the disclosure.In disclosure below
Hold the particular example for describing each component and its arrangement mode, to simplify explanation.Certainly, these specific examples are not to limit
It is fixed.For example, it should be understood that when element is referred to as " being connected to " or " being couple to " another element, can be directly connected to or
Other elements are couple to, or may exist one or more intermediary elements.
The disclosure in particular to has fin field-effect transistor about semiconductor device and its manufacturing method
(FinFET) semiconductor device and its manufacturing method.In various embodiments, fin field effect transistor structure can be to difference
Electrical requirements are optimised in a particular area, such as provide for static discharge (ESD) protection, high-voltage metal oxide semiconductor
(HVMOS) device, lock diode (gated diode) or other structures and the transistor unit structure that optimizes.Existing fin
Field effect transistor structure maintain original fin field effect transistor structure patterning can across all active device regions (including
Between adjacent polysilicon grid in the region of larger space).It is generated higher due to lower epitaxial film growth efficiency
Junction resistance (such as: higher Rsd), the method will lead to failure and lower linear region in metal contact land
Drain current (Idlin).In some embodiments of the disclosure, an apparatus structure includes being used for non-planar (non-planar) fin
(commonly referred to as oxide defines first active area of formula field effect transistor device (or multiple non-planar fin field-effect transistors)
(OD) region) and for plane fin field effect transistor device the second active area.For plane fin field-effect transistor
The membrane quality that the silicon epitaxy in the second active area of device is grown up, which obtains improving, can improve device efficiency, especially because
Reducing junction resistance (Rsd) improves the performance of linear region drain current (Idlin).Land for metal contact land
Window increase improves yield and reliability performance.
Fig. 1 is tool there are two the schematic diagram of the semiconductor device 10 of different type active area, and active area is also known as herein
The region (OD) is defined for oxide or oxide defines pattern.Each active area is doped region, and including source area
Passage area between domain and drain region and source region and drain region.The examples of materials of active area includes doping
There is the semiconductor material of various types of p-type dopants and/or N-type dopant, but not limited to this.More specifically, semiconductor
Device 10 includes silicon substrate 12, has on silicon substrate 12 and is oxidized the separated multiple regions of object area of isolation 14.Actively first
In region (region OD), the regions and source/drain 22 of tight spacing is formed on silicon area 16 (also known as fin 16).Multiple
In embodiment, regions and source/drain 22 is formed in the region that epitaxial growth material is constituted on corresponding fin 16.Multiple
In embodiment, epitaxial growth material includes SiP (phosphatization silicon) layer.In some embodiments, epitaxial growth material includes SiGe (silicon
Germanium) layer.Gate structure 26a, 26b and the 26c (it can be formed by polysilicon or at least one metal material) at three intervals
It is to extend perpendicular to the direction of regions and source/drain 22.In the second active area (region OD), silicon area 18 is compared to fin
Piece 16 has relatively wide region, has the planar boundary (surface for the regions and source/drain 24 for being formed on extension
20).When compared with fin 16, silicon area 18 is considered silicon (Si) plane domain.In various embodiments, source electrode/
Drain region 24 is also from the formation of the silicon of epitaxial growth, phosphatization silicon (SiP) and/or SiGe (SiGe).
Fig. 2 is the schematic diagram for showing the side of semiconductor device 10 of Fig. 1.In this schematic diagram, three gate structures
The clearer display in the interval of 26a, 26b and 26c.As can be seen that when with gate structure 26b and 26c point open at a distance from ratio
Compared with when, gate structure 26a and 26b point open relatively short distance.For example, gate structure 26a and 26b is separated one
A distance A.In various embodiments, distance A is about 0.1 to 0.3 micron (μm).Gate structure 26b and 26c is by separately another
The distance B at a farther (on center).In various embodiments, distance B is about 0.4 to 0.5 micron.It is understood that such as the dress of Fig. 3
It sets shown in layout, two gate structure 26b and 26c (its line for being shown as two intervals) separated form pair transistor arrangement
Two grids.Specifically, Fig. 3 shows two N-type metal oxide semiconductcor field effect transistors being formed in P well 50
(NMOS) arrangement, but it is understood that the disclosure applies equally to P type metal oxide semiconductor field-effect transistor (PMOS) or mutual
The arrangement of benefit formula metal-oxide semiconductor (MOS) (CMOS).As shown in FIG. 2 and 3, the first transistor arrangement passes through gate structure
Regions and source/drain on the right side of regions and source/drain 22 and 24, gate structure 26b on the left of 26b and on the left of gate structure 26c
22 and 24 and gate structure 26b is formed.Second transistor arrangement passes through the regions and source/drain 22 on the left of gate structure 26c
With on the right side of 24, gate structure 26c regions and source/drain 22 and 24 and gate structure 26c formed.Although it is understood that grid
Structure 26b and 26c are shown as the continuous grid shared between first and second transistor arrangement in different active areas
Polar curve, but only for ease of illustration this.Polysilicon lines can be cut to allow unit control the first transistor and the second crystal
Pipe arrangement, that is, form the gate structure of separation.
It is for the needle in transistor arranges it is understood that providing the relatively wide distance B between gate structure 26b and 26c
Stronger protection is provided to static discharge.For example, this relatively wide distance allows wider regions and source/drain to be formed in
Wherein, this regions and source/drain can reduce junction resistance (Rsd).Therefore, under identical application voltage, linear region
Drain current (Idlin) significant can increase, so that corresponding transistor be made to have stronger protection for static discharge.In addition,
This region (also known as recess region (dishing)) is for connecting in transistor (especially regions and source/drain) and metal
The region of the contact point land of portion's interconnection layer (such as: M1 layers (the first metal layer)).It should be understood that the polysilicon lines being more narrowly spaced
Between region (distance A) be used to connect transistor (especially source region) and M1 layer of contact point land
It is known that by the second active area not repeated arrangement from the first active area first configuration source
Pole/drain region 22, and form regions and source/drain 24 on wider and more plane surface 20 (as shown in Figure 1), can be with
Reach enough and more preferably epitaxial film is grown up, in the broader region being especially isolated between gate structure 26b and 26c
(i.e. in sunk area).Regions and source/drain 22 of the upper surface of regions and source/drain 24 than nonplanar mushroom cap shape
Wider and more plane, and more preferably contact window is provided for metal contact land.It should be understood that regions and source/drain can not
It can be perfect ground level, therefore use term " on the whole plane (substantially planar) " sometimes in the disclosure.?
That is compared to patterning (the nonplanar source/drain for keeping standard fin field-effect transistor in the second active area
The patterning in region 22), regions and source/drain is enough planes (i.e. on the whole plane), so that due to larger source/drain
The lower resistance in region, and have biggish linear region drain current (Idlin).
(plane fin field-effect transistor is formed in the fin field-effect transistor of more standard to this method described in the disclosure
The region OD beside the region OD) it can preferably optimize transistor arrangement in selected areas.For example, second of configuration
(i.e. planar configuration) can be used for being formed the transistor with different electrical requirements, such as electrostatic discharge protective device, height
Press MOS device or lock diode.
In various embodiments, the width (C) of the region plane OD (silicon area 18) at least across 100 nanometers (i.e. and polycrystalline
On the parallel direction of the gate structure 26 of silicon), and it is at least 200 nanometers in various embodiments.This size is to source/drain
It is crucial that polar region domain 24, which provides enough epitaxial growths,.This causes regions and source/drain 22 respectively to have common mushroom cap shape
Shape.In various embodiments, the width C in the region plane OD is about 150 nanometers to about 250 nanometers, and in this region can be with
See the regions and source/drain 24 with relatively evenly thickness (at least 61 nano thickness).In contrast, it is imitated in fin field brilliant
In identical corresponding region in the first active area (region OD) of body pipe (non-planar), it can be seen that with about 24 nanometers or more
The relatively poor epitaxial film growth of small thickness.This is indicated compared with nonplanar fin field-effect transistor, in the area plane OD
The epitaxial film in domain is grown with about 250% incrementss.
Fig. 4 is the sectional view of transistor, to show with contributive to overall electrical resistance each in transistor connection
Kind resistance.Resistance RV0Represent the electricity connecting between metal and MD contact layer (such as: metal contact layer, metal define contact layer)
Resistance.Resistance RMD2The resistance of the MD contact layer due to the 2nd MD processing procedure (such as: metal procedure, metal define processing procedure) is represented, and
Resistance RMD1Represent the resistance due to the MD contact layer of the first MD processing procedure.Resistance RcsdWhat representative was contacted with source/drain implant layer
Resistance.Resistance RsdRepresent the resistance of source/drain implant.Resistance RlddRepresent the resistance of lightly doped drain (LDD) implant dosage.
Resistance ROVThe resistance for carrying out the overlapping of self-capacitance processing procedure is represented, is the accumulation layer under gate overlap, i.e., due to shadow effect
(shadow effect) is without channel and the resistance region of lightly doped drain implant.Finally, resistance RchRepresent the electricity of electric channel
Resistance.NLDD in Fig. 4 shows that the implant dosage processing procedure of the lightly doped drain of N-type metal oxide semiconductcor field effect transistor will
Reduce the R according to implant dosagelddAnd ROVResistance.N+SD shows that source/drain implant processing procedure will affect RsdAnd Rcsd's
Resistance.
Include that resistance in region 100 depends on epitaxial layer, for example, phosphatization silicon (SiP) i.e./or SiGe (SiGe).Resistance
ROVFirst stage by epitaxial growth is influenced.In the amount of the qualitative effects bottom leakage current of the epitaxial layer in this stage.Resistance Rldd
Also it is influenced by the SiP first stage grown up and the concentration of dopant in lightly doped drain.Resistance RsdGrown up by SiP
Second stage and in SiP layers concentration of dopant influence.Finally, resistance RcsdThe phase III shadow grown up by SiP
It rings, the amount including contacting consumed SiP with SiP layers by silicide (such as: titanium silicide (TiSi)).In short, flat
The SiP floor of achievable bigger and preferred quality in the area OD of face, can by improve the contact point MD (such as: metal contact, gold
Belong to and define contact point) it lands and the next significant reduction resistance R of electrical conduction between the region SiPsd, it is the main contributions of overall electrical resistance
Person.
In various embodiments, the apparatus structure of Fig. 1 is manufactured (to imitate crystal in standard fin field in the non-planar region OD
Pipe) and both the region plane OD (plane fin field-effect transistor) there is about 1.8V to operate voltage.For the region plane OD
Transistor has enough epitaxy Si P to grow up, and the good contact point MD is caused to land.Apparatus structure is tested and has linear region
76% gain of drain current (Idlin) efficiency.
There is non-planar (fin field-effect transistor) region OD and plane OD (to imitate crystal in fin field for Fig. 5 A to Fig. 5 N display
Pipe) both regions apparatus structure manufacturing method.It should be understood that non-planar (fin field-effect transistor) region OD and plane OD
(fin field-effect transistor) region can be adjacent to each other or be spaced each other, and provided attached drawing is only to show step, can
These regions are manufactured for some embodiments, and their non-display the relative position of each other.
According to some embodiments, since Fig. 5 A, provides and be formed on 202 (referred to as liner oxidation of oxide skin(coating)
Object) silicon substrate 200.Silicon nitride (SiN) layer 204 (referred to as OD silicon nitride) is formed on oxide skin(coating) 202.Oxide skin(coating) 206
(referred to as OD oxide) is formed on silicon nitride layer 204.Up to the present, the region plane OD 208 is (by corresponding flat (fin field
Imitate transistor) region OD) and the non-planar region OD 210 (by non-planar (fin field-effect transistor) region OD of correspondence) be consistent
's.Mask layer 212 (being made of the vertical pillars (piller) or finger-shaped material (finger) that are spaced each other) is formed in non-planar
On oxide skin(coating) 206 in the region OD 210, rather than on the oxide skin(coating) 206 in the region plane OD 208.
In figure 5B, formed protective layer 214 (can be photoresist layer) in the structure of Fig. 5 A, and with etching or other
Mode forms the opening 215a and 215b across protective layer 214 to oxide skin(coating) 206, the i.e. top of exposed oxide layer 206
Boundary part.In some embodiments, this etching operation leads to some columns for removing mask layer 212.In some embodiments,
The etching operation for forming opening 215a and 215b may include executing dry type at least once to the photoresist layer of blank (blank) to lose
Scribe journey (such as: reactive ion etch (RIE) processing procedure).
In figure 5 c, protective layer 214 is removed, modification mask layer 212a is left.In some embodiments, protective layer is removed
214 operation includes executing selective wet etch process, only removes protective layer 214, and leave substantially intact modification
Mask layer 212a.
In figure 5d, use modification mask layer 212a as mask etching across oxide skin(coating) 202, silicon nitride layer 204 with
And oxide skin(coating) 206 (Fig. 5 C) and it is partially etched to silicon substrate 200.In various embodiments, etching operation is to silicon substrate 200
The distance E that etched about 50 nanometers leaves with the silicon column of fin 16 or repairing for silicone grease object 216 corresponded in Fig. 1
Change silicon substrate 200a, and silicon substrate 200a has remaining portions of oxide layer 202a, partial nitridation silicon layer 204a and portion thereon
Sub-oxide layer 206a.In some embodiments, the etching operation for forming silicon column 216 includes respectively or jointly in oxygen
Dry etch process (example one or more times is executed on compound layer 206, silicon nitride layer 204, oxide skin(coating) 202 and silicon substrate 200
Such as: reactive ion etch (RIE) processing procedure).
In Fig. 5 E, after removing portions of oxide layer 206a, another protective layer 222 is formed, and etch modification silicon
Substrate 200a (Fig. 5 D) has opening 220a in plane OD (fin field-effect transistor) region 208 with generation, opening 220b exists
In non-planar (fin field-effect transistor) region OD 210, it is open between the region plane OD 208 and the non-planar region OD 210
Modify silicon substrate 200b.These openings will be used to form the oxide isolation areas in Fig. 1 14.This operation is in modification silicon substrate
Four silicon planes 218a, 218b, 218c and 218d are left in 200b.
In Fig. 5 F, another protective layer 224 (can be photoresist layer) is formed in structure, and forms opening to lose
Modification silicon substrate 200b is carved to remove silicon plane 218a and 218c, to leave silicon plane in modification silicon substrate 200c
218b and 218d.In some embodiments, this operation for removing silicon plane 218a and 218c is optional.Silicon plane 218d
With the silicon column 216b being formed on, wherein there are remaining portions of oxide layer 202b and portion on silicon column 216b
Divide silicon nitride layer 204b.
In Fig. 5 G, protective layer 224 is removed, the modification silicon substrate 200c with silicon plane 218b and 218d is left,
In have silicon column 216b and remaining portions of oxide layer 202b and partial nitridation silicon layer 204b on silicon plane 218d.
In some embodiments, the operation for removing protective layer 224 may include executing selective wet etch process, only remove protective layer
224, and leave substantially intact silicon plane 218b and 218d (and the counter structure being formed on).
In fig. 5h, the deposited oxide layer 226 in the structure of Fig. 5 G, to be used to form shallow plough groove isolation area.
In Fig. 5 I, chemical mechanical grinding (CMP) operation, the oxide after leaving grinding are executed on oxide skin(coating) 226
Layer 226a.As shown in fig. 5i, the oxide skin(coating) 226a after grinding has a step, wherein the oxide on silicon plane 218d
The upper surface in region is about 50 nanometers higher than the upper surface of the oxide areas on silicon plane 218b, corresponds to silicon column 216b
Height E.The operation of this chemical mechanical grinding exposes partial nitridation silicon layer 204b and the portion configured on silicon column 216b
Sub-oxide layer 202b.
In fig. 5j, etching operation is executed to remove partial nitridation silicon layer 204b, and is further reduced oxide skin(coating)
The height of 226a leaves oxide skin(coating) 226b.
In Fig. 5 K, the partial oxide on silicon column 216b is removed using the etch process with etching selectivity
Layer 202b, to avoid damage silicon substrate.
In Fig. 5 L, it is further reduced the height of oxide skin(coating) 226b using directional etch processing procedure, leaves reduction height
Oxide skin(coating) 226c.This directional etch processing procedure increases the height of the silicon column 216b extended on oxide skin(coating) 226c.
A small amount of oxide remains on silicon plane 218b.
In Fig. 5 M, in the final directional etch processing procedure of the preceding execution of source/drain growth process (by using in figure
Arrow is shown).This directional etch processing procedure is used to be further reduced the height of oxide 226c, leaves and is further reduced height
The oxide skin(coating) 226d of degree.This directional etch processing procedure further increases the silicon column 216b extended on oxide skin(coating) 226d
Height.This directional etch processing procedure also exposes silicon plane 218b, removes oxide on it.There are some loads to imitate here
It answers, the height of silicon plane 218b is caused to be slightly less than the height (such as: about 5.65 nanometers small) of silicon plane 218d.
In Fig. 5 N, epitaxial structure 228 (the corresponding regions and source/drain 24 in Fig. 1) is formed on silicon plane 218b.
In addition, forming epitaxial structure 230 (the corresponding regions and source/drain 22 in Fig. 1) on silicon plane 218d.
Before Fig. 5 N or later, multiple operations are executed to complete the structure of Fig. 1, including form gate structure 26.One
In a little embodiments, gate structure 26 can be in the preceding formation for forming epitaxial structure 228 and 230.These technologies are to formation fin
The usual skill of field-effect transistor is familiar with, this is no longer repeated, to avoid the disclosure is unnecessarily obscured.
It is understood that Fig. 5 A to Fig. 5 N only shows the possible embodiment that fin is patterned.It should be understood that fin can lead to
Any appropriate method is crossed to be patterned.For example, one or more lithographic process can be used to pattern in fin, including dual
Patterning process or multiple patterning process.Usually, double patterning processing procedure or multiple patterning process combination optical graving
Journey and self-aligned processing procedure use the available spacing of single, direct lithographic process than other to allow to generate to have
The pattern of smaller spacing.For example, in one embodiment, sacrificial layer is formed on substrate, and is used photoetching
Processing procedure patterning.Spacer is used self-aligned processing procedure to be formed in beside patterned sacrificial layer.Sacrificial layer is then removed,
And the spacer (or mandrel (mandrel)) left can then be used to patterning fin.
Fig. 6 and Fig. 6 A show be connected to the epitaxial layer of semiconductor device structure of Fig. 1 contact point 30 (such as: tungsten (W)
Contact point).By in figure it is found that silicon area 18 (the on the whole fin of plane) provide to improve epitaxial film growth wide base
Bottom, so that the metal that the regions and source/drain 24 of base plan provides an improvement of contact point 30 lands window.In some realities
It applies in example, this contact point can be formed to extend through covering regions and source/drain 22 and 24 and gate structure 26a extremely
The dielectric layer (commonly referred to as interlayer dielectric layer or inter-metal dielectric layer) of 26c.In some embodiments, this dielectric layer can
Including low k (low-k) dielectric material.
In some embodiments, a kind of semiconductor device is provided, does not keep existing fin field effect transistor structure
Or it patterns across all active areas.This mode makes (multiple) the fin field effect with fin field effect transistor structure brilliant
The region of body pipe device can optimize during fabrication for specific region to be directed to for different electrical requirements, such as offer
Static discharge (ESD) protection, high-voltage metal oxide semiconductor (HVMOS) device, lock diode (gated diode) or other
Structure and the transistor unit structure optimized.In that region, in the region OD, silicon epitaxy growth membrane quality is enhanced,
It can improve device efficiency, especially because reducing junction resistance (Rsd) improves the table of linear region drain current (Idlin)
It is existing.Land window for the contact point MD land increases, and improves yield and reliability performance.
In one embodiment, a kind of semiconductor device includes one first fin field-effect transistor (FinFET) device, the
One fin field effect transistor device includes the multiple fins being formed in a substrate, the semiconductor material being formed on multiple fins
The epitaxial layer expected and the first grid structure across multiple fins, epitaxial layers form nonplanar source/drain
Region.Semiconductor device includes one second fin field effect transistor device, and the second fin field effect transistor device includes being formed in
On the whole a fin for plane, the source/drain regions for being formed on the on the whole fin of plane and forming on the whole plane in substrate
One second grid structure of one epitaxial layer of the semiconductor material in domain and the fin across on the whole plane.In some embodiments
In, semiconductor device further includes the fin across on the whole plane and the third gate structure separated with second grid structure,
And a contact point, contact point, which is located at, to be formed on the fin of the on the whole plane between second grid structure and third gate structure
On the epitaxial layer of side.In certain embodiments, on the whole the fin of plane has extremely on the direction for being parallel to second grid structure
Few 100 nanometers of width.In certain embodiments, the epitaxial layer of semiconductor material is phosphatization silicon (SiP).In some embodiments
In, second grid structure and first grid structure are in a straight line.In certain embodiments, semiconductor device further includes across on the whole
The fin of plane, and the third gate structure separated with second grid structure, and across nonplanar multiple fins
One the 4th gate structure.In certain embodiments, the first fin field effect transistor device and the second fin field-effect transistor dress
It sets and is separately formed in one first active area and one second active area, the first active area and the second active area quilt
Monoxide region separates.In certain embodiments, institute's shape on the fin of the on the whole plane of the second fin field effect transistor device
At a part of epitaxial layer of semiconductor material extend on a part of oxide areas.In certain embodiments, greatly
The upper surface of fin to plane is lower than the upper surface of multiple fins.In certain embodiments, the first fin field-effect transistor fills
Width of the distance that the multiple fins set are spaced each other less than the fin of the on the whole plane of the second fin field effect transistor device.
In another embodiment, a kind of manufacturing method for semiconductor device includes providing a substrate, in a first area
Etching substrate, to form multiple fins of one first fin field-effect transistor (FinFET)；The etching substrate in a second area,
To form the fin of an on the whole plane of one second fin field-effect transistor (FinFET)；In multiple fins and on the whole plane
An epitaxial layer of semiconductor material is formed on fin；It is formed across a first grid structure of nonplanar multiple fins: and
It is formed across a second grid structure of the on the whole fin of plane.Epitaxial layer on multiple fins provides and first grid structure phase
Adjacent multiple nonplanar regions and source/drains, and the epitaxial layer on the fin of on the whole plane provides and second grid knot
The regions and source/drain of the adjacent on the whole plane of structure.In certain embodiments, manufacturing method for semiconductor device further includes second
A third gate structure of the on the whole fin of plane is formed across in region, wherein third gate structure and second grid structure every
It opens, and forms a contact point, contact point is in the on the whole plane being formed between second grid structure and third gate structure
On epitaxial layer on fin.In certain embodiments, on the whole the fin of plane has on the direction for being parallel to second grid structure
There is at least 100 nanometers of width.In certain embodiments, the epitaxial layer of semiconductor material is phosphatization silicon (SiP).In certain implementations
In example, second grid structure and first grid structure are in a straight line.In certain embodiments, manufacturing method for semiconductor device also wraps
The monoxide area of isolation in the substrate being etched between first area and second area is included, and fill oxide extremely aoxidizes
In object area of isolation.In certain embodiments, on the whole the upper surface of the fin of plane be lower than multiple fins upper surface.
In another embodiment, a kind of semiconductor device includes having one first fin field-effect transistor (FinFET) dress
One first active area being formed within is set, the first fin field effect transistor device includes the multiple fins being formed in a substrate
Piece, an epitaxial layer of the semiconductor material being formed on multiple fins and the first grid structure across multiple fins,
Epitaxial layers form nonplanar regions and source/drain.Semiconductor device also includes having one second fin field-effect transistor dress
Set one second active area being formed within, the second fin field effect transistor device includes forming one on the whole putting down in a substrate
The fin in face is formed on the on the whole fin of plane and forms the on the whole semiconductor material of the regions and source/drain of plane
One second grid structure of one epitaxial layer and the fin across on the whole plane.This semiconductor device includes a contact point, contact
Point is on the epitaxial layer being formed on the on the whole fin of plane.The epitaxial layer of semiconductor material is phosphatization silicon (SiP), and on the whole
The fin of plane has at least 100 nanometers of width on the direction for being parallel to second grid structure.In certain embodiments, half
Conductor device further includes the fin across on the whole plane and the third gate structure separated with second grid structure, wherein connecing
Contact is configured between second grid structure and third gate structure.In certain embodiments, second grid structure and first
Gate structure is in a straight line.
Aforementioned interior text outlines the feature of many embodiments, allows technician in the art in all its bearings more
The disclosure is understood goodly.Technician in the art, it is to be appreciated that and can be designed based on the disclosure easily or
It modifies other processing procedures and structure, and identical purpose is reached with this and/or reaches identical excellent with the embodiment introduced herein etc.
Point.Technician in the art it will also be appreciated that these equal structures without departing from the disclosure inventive concept and range.
Under the premise of without departing substantially from the inventive concept and range of the disclosure, various changes, displacement or modification can be carried out to the disclosure.
Claims (1)
1. a kind of semiconductor device, comprising:
One first fin field-effect transistor (FinFET) device, above-mentioned first fin field effect transistor device includes prolonging from a substrate
One epitaxial layer of the multiple fins, the semiconductor material being formed on above-mentioned fin stretched and across the one of above-mentioned fin
One gate structure, wherein above-mentioned epitaxial layer forms nonplanar regions and source/drain；And
One second fin field effect transistor device, above-mentioned second fin field effect transistor device include one extended from aforesaid substrate
On the whole the fin of plane (substantially planar), be formed on the fin of above-mentioned on the whole plane and formed and on the whole put down
The one of one epitaxial layer of the above-mentioned semiconductor material of the regions and source/drain in face and the fin across above-mentioned on the whole plane
Two gate structures.
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| US201762513012P | 2017-05-31 | 2017-05-31 | |
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| US15/990,278 | 2018-05-25 | ||
| US15/990,278 US10763280B2 (en) | 2017-05-31 | 2018-05-25 | Hybrid FinFET structure |
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