CN108987354B

CN108987354B - Wide bandgap power semiconductor module packaging structure

Info

Publication number: CN108987354B
Application number: CN201710397945.5A
Authority: CN
Inventors: 沈杰; 王传宇; 曹伟杰; 吴跃飞; 徐腾
Original assignee: LG Electronics Shanghai Research and Development Center Co Ltd
Current assignee: LG Electronics Shanghai Research and Development Center Co Ltd
Priority date: 2017-05-31
Filing date: 2017-05-31
Publication date: 2020-07-24
Anticipated expiration: 2037-05-31
Also published as: CN108987354A

Abstract

The invention provides a wide bandgap power semiconductor module packaging structure, and relates to the technical field of circuit device packaging. In the structure, a drive isolation protection circuit and a wide bandgap power semiconductor device are packaged in different layers in a multi-layer packaging layer structure and are packaged into a whole; a driving isolation control interface of the driving isolation protection circuit penetrates through a packaging layer in the multi-layer packaging layer structure through a through hole of the multi-layer packaging layer structure and is connected with a gate pole of the wide bandgap power semiconductor device; the pulse width modulation signal input interface and the driving power supply input interface respectively penetrate through a packaging layer in the multilayer packaging layer structure through via holes of the multilayer packaging layer structure, and a pulse width modulation signal input interface connection point and a driving power supply input interface connection point are formed on the upper surface of the multilayer packaging layer structure; the drain electrode and the source electrode of the wide bandgap power semiconductor device are exposed out of the multilayer packaging layer structure, and a power loop interface connection point is formed on the upper surface of the multilayer packaging layer structure.

Description

Wide bandgap power semiconductor module packaging structure

Technical Field

The invention relates to the technical field of circuit device packaging, in particular to a wide bandgap power semiconductor module packaging structure.

Background

Currently, power semiconductor modules are generally used in circuit structures requiring application of power modules, such as various power supply circuits, motor controllers, and chargers. Among them, the wide bandgap power semiconductor is referred to as a third generation semiconductor, and its material includes diamond, SiC (silicon carbide), GaN (gallium nitride), and the like. The wide-bandgap power semiconductor has the characteristics of large forbidden bandwidth, high electron drift saturation velocity, small dielectric constant and good conductivity, has excellent properties and potential huge prospects in the application of the wide-bandgap power semiconductor in the field of microwave power devices, and is very suitable for manufacturing electronic devices with radiation resistance, high frequency, high power and high density integration.

The current packaging mode of the wide bandgap power semiconductor module is to place the wide bandgap power semiconductor devices and the drive isolation protection circuit on a traditional ceramic substrate, connect the wide bandgap power semiconductor devices and the drive isolation protection circuit by adopting a lead wire pressure welding technology, and then perform the procedures of glue pouring, mould pressing, curing and the like on the circuit on the whole ceramic substrate, thereby completing the packaging of the wide bandgap power semiconductor module. However, the parasitic parameters of the whole circuit are large due to the long connection lengths of the leads used between the wide bandgap power semiconductor devices and the driving isolation protection circuit, so that the working characteristics of the wide bandgap power semiconductor devices with high switching frequency cannot be exerted, and the switching frequency of the power semiconductor module is limited.

Disclosure of Invention

Embodiments of the present invention provide a wide bandgap power semiconductor module package structure, so as to solve the problem that in the prior art, due to long connection lengths of leads used between wide bandgap power semiconductor devices and between the wide bandgap power semiconductor devices and a drive isolation protection circuit, parasitic parameters of the whole circuit are large, the operating characteristics of the wide bandgap power semiconductor devices with high switching frequency cannot be exerted, and the switching frequency of a power semiconductor module is limited.

In order to achieve the purpose, the invention adopts the following technical scheme:

a wide bandgap power semiconductor module packaging structure comprises a single-device wide bandgap power semiconductor module, a half-bridge wide bandgap power semiconductor module or a full-bridge wide bandgap power semiconductor module, wherein the single-device wide bandgap power semiconductor module is composed of a drive isolation protection circuit and a wide bandgap power semiconductor device;

the drive isolation protection circuit and the wide bandgap power semiconductor device are packaged in different layers in a multilayer packaging layer structure; the multilayer packaging layer structure packages the drive isolation protection circuit and the wide bandgap power semiconductor device into a whole;

the drive isolation protection circuit is provided with a pulse width modulation signal input interface, a drive power supply input interface and a drive isolation control interface; the driving isolation control interface penetrates through a packaging layer in the multi-layer packaging layer structure through a through hole of the multi-layer packaging layer structure and is connected with a gate electrode of the wide bandgap power semiconductor device; the pulse width modulation signal input interface and the driving power supply input interface respectively penetrate through a packaging layer in the multilayer packaging layer structure through via holes of the multilayer packaging layer structure, and a pulse width modulation signal input interface connection point and a driving power supply input interface connection point are formed on the upper surface of the multilayer packaging layer structure; the drain electrode and the source electrode of the wide bandgap power semiconductor device are exposed out of the multilayer packaging layer structure, and a power loop interface connection point is formed on the upper surface of the multilayer packaging layer structure.

Furthermore, the multilayer packaging layer structure is made of low-temperature co-fired ceramic materials.

Furthermore, the lower surface of the multilayer packaging layer structure is connected with the radiator through a heat conduction filling material.

Furthermore, the pulse width modulation signal input interface connection point, the driving power supply input interface connection point and the power loop interface connection point on the upper surface of the multilayer packaging layer structure are connected with circuit wiring of an external printed circuit board.

Specifically, the single-device wide bandgap power semiconductor module includes a first driving isolation protection circuit and a first group of wide bandgap power semiconductor devices; the first group of wide bandgap power semiconductor devices comprises a wide bandgap power semiconductor device;

the first drive isolation protection circuit is provided with the pulse width modulation signal input interface, a drive power supply input interface, a drive isolation control interface and a power grounding interface; the pulse width modulation signal input interface, the driving power supply input interface, the driving isolation control interface and the power grounding interface penetrate through a packaging layer in the multilayer packaging layer structure through via holes of the multilayer packaging layer structure and are exposed out of the upper surface of the multilayer packaging layer structure to form a pulse width modulation signal input interface connection point, a driving power supply input interface connection point, a driving isolation control interface connection point and a power grounding interface connection point; the drain electrode, the source electrode and the gate electrode of the wide-bandgap power semiconductor device are exposed out of the multilayer packaging layer structure, and a drain electrode connecting point, a source electrode connecting point and a gate electrode connecting point are formed on the upper surface of the multilayer packaging layer structure;

the pulse width modulation signal input interface connection point, the driving power supply input interface connection point, the driving isolation control interface connection point, the power grounding interface connection point, the drain electrode connection point, the source electrode connection point and the gate electrode connection point are welded with circuit wiring of an external printed circuit board, so that the pulse width modulation signal input interface connection point is connected with an external pulse width modulation signal, the driving power supply input interface connection point is connected with an external driving power supply, the driving isolation control interface connection point is connected with the gate electrode connection point, the power grounding interface connection point is connected with the source electrode connection point, and the source electrode connection point and the drain electrode connection point form a power loop interface connection point which is connected with an external application circuit.

Or, the single-device wide bandgap power semiconductor module includes a first driving isolation protection circuit and a first group of wide bandgap power semiconductor devices; the first group of wide bandgap power semiconductor devices comprises a plurality of wide bandgap power semiconductor devices;

the first drive isolation protection circuit is provided with the pulse width modulation signal input interface, a drive power supply input interface, a drive isolation control interface and a power grounding interface; the pulse width modulation signal input interface, the driving power supply input interface, the driving isolation control interface and the power grounding interface penetrate through a packaging layer in the multilayer packaging layer structure through via holes of the multilayer packaging layer structure and are exposed out of the upper surface of the multilayer packaging layer structure to form a pulse width modulation signal input interface connection point, a driving power supply input interface connection point, a driving isolation control interface connection point and a power grounding interface connection point; the drain electrodes, the source electrodes and the gate electrodes of the plurality of wide bandgap power semiconductor devices are exposed out of the multilayer packaging layer structure, and drain electrode connection points, source electrode connection points and gate electrode connection points are formed on the upper surface of the multilayer packaging layer structure;

the pulse width modulation signal input interface connection point, the driving power supply input interface connection point, the driving isolation control interface connection point, the power grounding interface connection point, the drain electrode connection point, the source electrode connection point and the gate electrode connection point are welded with the circuit wiring of the external printed circuit board, so that the connection point of the pulse width modulation signal input interface is connected with an external pulse width modulation signal, the connection point of the driving power supply input interface is connected with an external driving power supply, such that the drive isolation control interface connection is connected to each gate connection point, such that the power ground interface connection is connected to each source connection point, such that each source connection point is connected together, and each drain connection point is connected together, and the source connection points connected together and the drain connection points connected together form a power loop interface connection point to be connected with an external application circuit.

Specifically, the half-bridge wide bandgap power semiconductor module comprises a first drive isolation protection circuit, a second drive isolation protection circuit, a first group of wide bandgap power semiconductor devices and a second group of wide bandgap power semiconductor devices; the first group of wide bandgap power semiconductor devices and the second group of wide bandgap power semiconductor devices respectively comprise a wide bandgap power semiconductor device;

the first drive isolation protection circuit is provided with a first pulse width modulation signal input interface and a first drive isolation control interface; the second drive isolation protection circuit is provided with a second pulse width modulation signal input interface and a second drive isolation control interface; the first drive isolation protection circuit and the second drive isolation protection circuit are provided with the same drive power supply input interface and the same drive grounding interface together; the first drive isolation control interface is connected with the gate electrodes of the first group of wide bandgap power semiconductor devices through copper columns in via holes of the multilayer packaging layer structure; the second drive isolation control interface is connected with the gate electrode of the second group of wide bandgap power semiconductor devices through a copper column in a via hole of the multilayer packaging layer structure; the source electrode of the first group of wide bandgap power semiconductor devices and the drain electrode of the second group of wide bandgap power semiconductor devices are connected together in the multilayer packaging layer structure and are used as an output pin interface; the first pulse width modulation signal input interface, the second pulse width modulation signal input interface, the driving power supply input interface, the driving grounding interface and the output pin interface, and the drain electrodes of the first group of wide bandgap power semiconductor devices and the source electrodes of the second group of wide bandgap power semiconductor devices respectively penetrate through a packaging layer in a multilayer packaging layer structure through copper columns in through holes of the multilayer packaging layer structure, are exposed out of the upper surface of the multilayer packaging layer structure, and respectively form a first pulse width modulation signal input interface direct-insert pin, a second pulse width modulation signal input interface direct-insert pin, a driving power supply input interface direct-insert pin, a driving grounding interface direct-insert pin, an output pin interface direct-insert pin, a power loop bus positive electrode direct-insert pin and a power loop bus negative electrode direct-insert pin;

the first pulse width modulation signal input interface direct-insert pin, the second pulse width modulation signal input interface direct-insert pin, the driving power supply input interface direct-insert pin, the driving grounding interface direct-insert pin, the output pin interface direct-insert pin, the power circuit bus positive electrode direct-insert pin and the power circuit bus negative electrode direct-insert pin are connected with the circuit wiring of the external printed circuit board, so that the first pulse width modulation signal input interface direct-insert pin and the second pulse width modulation signal input interface direct-insert pin are connected with the external pulse width modulation signal, the direct-insert pin of the driving power input interface is connected with an external driving power supply, the direct-insert pin of the driving grounding interface is grounded, and the output pin interface direct-insert pin, the power loop bus positive electrode direct-insert pin and the power loop bus negative electrode direct-insert pin are used as power loop interfaces to be connected with an external application circuit.

Or, the half-bridge wide bandgap power semiconductor module includes a first driving isolation protection circuit, a second driving isolation protection circuit, a first group of wide bandgap power semiconductor devices, and a second group of wide bandgap power semiconductor devices; the first group of wide bandgap power semiconductor devices and the second group of wide bandgap power semiconductor devices respectively comprise a plurality of wide bandgap power semiconductor devices with the same number;

the gate electrodes of the wide bandgap power semiconductor devices in the first group of wide bandgap power semiconductor devices are connected together in the multi-layer packaging layer structure and are used as the gate electrodes of the first group of wide bandgap power semiconductor devices; the drains of the wide bandgap power semiconductor devices in the first group of wide bandgap power semiconductor devices are connected together in the multilayer packaging layer structure and used as the drains of the first group of wide bandgap power semiconductor devices; the source electrodes of the wide bandgap power semiconductor devices in the first group of wide bandgap power semiconductor devices are connected together in the multilayer packaging layer structure and are used as the source electrodes of the first group of wide bandgap power semiconductor devices;

the gate electrodes of the wide bandgap power semiconductor devices in the second group of wide bandgap power semiconductor devices are connected together in the multi-layer packaging layer structure and are used as the gate electrodes of the second group of wide bandgap power semiconductor devices; the drains of the wide bandgap power semiconductor devices in the second group of wide bandgap power semiconductor devices are connected together in the multilayer packaging layer structure and used as the drains of the second group of wide bandgap power semiconductor devices; the source electrodes of the wide bandgap power semiconductor devices in the second group of wide bandgap power semiconductor devices are connected together in the multilayer packaging layer structure and are used as the source electrodes of the second group of wide bandgap power semiconductor devices;

Specifically, the full-bridge wide bandgap power semiconductor module comprises a first drive isolation protection circuit, a second drive isolation protection circuit, a third drive isolation protection circuit, a fourth drive isolation protection circuit, a first group of wide bandgap power semiconductor devices, a second group of wide bandgap power semiconductor devices, a third group of wide bandgap power semiconductor devices and a fourth group of wide bandgap power semiconductor devices; the first group of wide bandgap power semiconductor devices, the second group of wide bandgap power semiconductor devices, the third group of wide bandgap power semiconductor devices and the fourth group of wide bandgap power semiconductor devices respectively comprise a wide bandgap power semiconductor device;

the first drive isolation protection circuit is provided with a first pulse width modulation signal input interface and a first drive isolation control interface; the second drive isolation protection circuit is provided with a second pulse width modulation signal input interface and a second drive isolation control interface; the third drive isolation protection circuit is provided with a third pulse width modulation signal input interface and a third drive isolation control interface; the fourth driving isolation protection circuit is provided with a fourth pulse width modulation signal input interface and a fourth driving isolation control interface; the first drive isolation protection circuit, the second drive isolation protection circuit, the third drive isolation protection circuit and the fourth drive isolation protection circuit are provided with the same drive power supply input interface and the same drive grounding interface together; the first drive isolation control interface is connected with the gate electrodes of the first group of wide bandgap power semiconductor devices through copper columns in via holes of the multilayer packaging layer structure; the second drive isolation control interface is connected with the gate electrode of the second group of wide bandgap power semiconductor devices through a copper column in a via hole of the multilayer packaging layer structure; the third driving isolation control interface is connected with the gate electrode of the third group of wide bandgap power semiconductor devices through a copper column in a via hole of the multilayer packaging layer structure; the fourth driving isolation control interface is connected with the gate electrode of the fourth group of wide bandgap power semiconductor devices through a copper column in a via hole of the multilayer packaging layer structure; the source electrode of the first group of wide bandgap power semiconductor devices and the drain electrode of the second group of wide bandgap power semiconductor devices are connected together in the multilayer packaging layer structure and are used as a first output pin interface; the source electrode of the third group of wide bandgap power semiconductor devices and the drain electrode of the fourth group of wide bandgap power semiconductor devices are connected together in the multilayer packaging layer structure and are used as a second output pin interface; the drains of the first group of wide bandgap power semiconductor devices and the drains of the third group of wide bandgap power semiconductor devices are connected together in the multilayer packaging layer structure; the sources of the second group of wide bandgap power semiconductor devices and the sources of the fourth group of wide bandgap power semiconductor devices are connected together in the multilayer packaging layer structure; the first pulse width modulation signal input interface, the second pulse width modulation signal input interface, the third pulse width modulation signal input interface, the fourth pulse width modulation signal input interface, the driving power supply input interface, the driving grounding interface, the first output pin interface, the second output pin interface, the drains of the first group of wide bandgap power semiconductor devices and the third group of wide bandgap power semiconductor devices, and the sources of the second group of wide bandgap power semiconductor devices and the fourth group of wide bandgap power semiconductor devices respectively penetrate through the packaging layer in the multilayer packaging layer structure through the copper columns in the through holes of the multilayer packaging layer structure, and are exposed on the upper surface of the multilayer packaging layer structure to respectively form a first pulse width modulation signal input interface direct-insertion pin, a second pulse width modulation signal input interface direct-insertion pin and a third pulse width modulation signal input interface direct-insertion pin, A fourth pulse width modulation signal input interface direct-insert pin, a driving power supply input interface direct-insert pin, a driving grounding interface direct-insert pin, a first output pin interface direct-insert pin, a second output pin interface direct-insert pin, a power circuit bus positive electrode direct-insert pin and a power circuit bus negative electrode direct-insert pin;

the first pulse width modulation signal input interface direct-insert pin, the second pulse width modulation signal input interface direct-insert pin, the third pulse width modulation signal input interface direct-insert pin, the fourth pulse width modulation signal input interface direct-insert pin, the driving power supply input interface direct-insert pin, the driving grounding interface direct-insert pin, the first output pin interface direct-insert pin, the second output pin interface direct-insert pin, the power circuit bus positive electrode direct-insert pin and the power circuit bus negative electrode direct-insert pin are connected with the circuit wiring of an external printed circuit board, so that the first pulse width modulation signal input interface direct-insert pin, the second pulse width modulation signal input interface direct-insert pin, the third pulse width modulation signal input interface direct-insert pin and the fourth pulse width modulation signal input interface direct-insert pin are connected with an external pulse width modulation signal, and the direct-insert pin of the input interface of the driving power supply is connected with an external driving power supply, the direct-insert pin of the driving grounding interface is grounded, and the direct-insert pin of the interface of the first output pin, the direct-insert pin of the interface of the second output pin, the positive direct-insert pin of the power loop bus and the negative direct-insert pin of the power loop bus are used as power loop interfaces to be connected with an external application circuit.

Or, the full-bridge wide bandgap power semiconductor module includes a first driving isolation protection circuit, a second driving isolation protection circuit, a third driving isolation protection circuit, a fourth driving isolation protection circuit, a first group of wide bandgap power semiconductor devices, a second group of wide bandgap power semiconductor devices, a third group of wide bandgap power semiconductor devices, and a fourth group of wide bandgap power semiconductor devices; the first group of wide bandgap power semiconductor devices, the second group of wide bandgap power semiconductor devices, the third group of wide bandgap power semiconductor devices and the fourth group of wide bandgap power semiconductor devices respectively comprise a plurality of wide bandgap power semiconductor devices with the same number;

the gate electrodes of the wide bandgap power semiconductor devices in the third group of wide bandgap power semiconductor devices are connected together in the multilayer packaging layer structure and are used as the gate electrodes of the third group of wide bandgap power semiconductor devices; the drains of the wide bandgap power semiconductor devices in the third group of wide bandgap power semiconductor devices are connected together in the multilayer packaging layer structure and used as the drain of the third group of wide bandgap power semiconductor devices; the source electrodes of the wide bandgap power semiconductor devices in the third group of wide bandgap power semiconductor devices are connected together in the multilayer packaging layer structure and are used as the source electrodes of the third group of wide bandgap power semiconductor devices;

the gate electrodes of the wide bandgap power semiconductor devices in the fourth group of wide bandgap power semiconductor devices are connected together in the multi-layer packaging layer structure and are used as the gate electrodes of the fourth group of wide bandgap power semiconductor devices; the drains of the wide bandgap power semiconductor devices in the fourth group of wide bandgap power semiconductor devices are connected together in the multilayer packaging layer structure and are used as the drains of the fourth group of wide bandgap power semiconductor devices; the source electrodes of the wide bandgap power semiconductor devices in the fourth group of wide bandgap power semiconductor devices are connected together in the multilayer packaging layer structure and are used as the source electrodes of the fourth group of wide bandgap power semiconductor devices;

According to the wide bandgap power semiconductor module packaging structure provided by the embodiment of the invention, as the wide bandgap power semiconductor module packaging structure comprises a single-device structure wide bandgap power semiconductor module, a half-bridge structure wide bandgap power semiconductor module or a full-bridge structure wide bandgap power semiconductor module which consists of a drive isolation protection circuit and a wide bandgap power semiconductor device, the wide bandgap power semiconductor module packaging structure provided by the invention has various optional configurations, so that the wide bandgap power semiconductor module packaging structure is suitable for various application circuit topologies; in addition, the drive isolation protection circuit and the wide bandgap power semiconductor device are packaged in different layers in a multilayer packaging layer structure; the multilayer packaging layer structure packages the drive isolation protection circuit and the wide bandgap power semiconductor device into a whole; a driving isolation control interface of the driving isolation protection circuit penetrates through a packaging layer in the multi-layer packaging layer structure through a through hole of the multi-layer packaging layer structure and is connected with a gate pole of the wide bandgap power semiconductor device; the pulse width modulation signal input interface and the driving power supply input interface of the driving isolation protection circuit respectively penetrate through a packaging layer in the multi-layer packaging layer structure through via holes of the multi-layer packaging layer structure, and a pulse width modulation signal input interface connection point and a driving power supply input interface connection point are formed on the upper surface of the multi-layer packaging layer structure; the drain electrode and the source electrode of the wide bandgap power semiconductor device are exposed out of the multilayer packaging layer structure, and a power loop interface connection point is formed on the upper surface of the multilayer packaging layer structure. The multilayer packaging layer structure is adopted, and the device connection among the layers is completed through the through holes, so that the whole wide bandgap power semiconductor module packaging structure is high in integration level and small in size, the parasitic parameters of the whole circuit are reduced, and the problems that the working characteristics of the wide bandgap power semiconductor device with high switching frequency cannot be exerted and the switching frequency of a power semiconductor module is limited in the prior art can be solved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic top surface view of a wide bandgap power semiconductor module package structure according to an embodiment of the present invention;

fig. 2 is a schematic lower surface view of a wide bandgap semiconductor module package structure according to an embodiment of the present invention;

fig. 3 is a schematic side perspective view of a wide bandgap power semiconductor module package structure according to an embodiment of the present invention;

fig. 4 is a schematic connection diagram of an upper surface and a lower surface of a wide bandgap power semiconductor module package structure according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a single-device wide bandgap power semiconductor module according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a principle case where any group of wide bandgap power semiconductor devices includes a plurality of wide bandgap power semiconductor devices according to an embodiment of the present invention;

fig. 7 is a first schematic diagram illustrating a structure and circuit layout of a single-device wide bandgap power semiconductor module according to an embodiment of the present invention;

fig. 8 is a second schematic diagram of the structure and circuit layout of the single-device wide bandgap power semiconductor module according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a half-bridge wide bandgap power semiconductor module according to an embodiment of the present invention;

fig. 10 is a schematic diagram of a multi-layer package layer structure in a half-bridge wide bandgap power semiconductor module according to an embodiment of the present invention;

fig. 11 is a schematic diagram of layer 1 of a multilayer packaging layer structure in a half-bridge wide bandgap power semiconductor module according to an embodiment of the present invention;

fig. 12 is a schematic diagram of layer 2 of a multilayer packaging layer structure in a half-bridge wide bandgap power semiconductor module according to an embodiment of the present invention;

fig. 13 is a schematic diagram of layer 3 of a multilayer packaging layer structure in a half-bridge wide bandgap power semiconductor module according to an embodiment of the present invention;

fig. 14 is a schematic diagram of layer 4 of a multilayer packaging layer structure in a half-bridge wide bandgap power semiconductor module according to an embodiment of the present invention;

fig. 15 is a schematic structural diagram of a full-bridge wide bandgap power semiconductor module according to an embodiment of the present invention;

fig. 16 is a schematic structural diagram of a multilayer packaging layer in a full-bridge wide bandgap power semiconductor module according to an embodiment of the present invention;

fig. 17 is a schematic diagram of layer 1 of a multilayer packaging layer structure in a full-bridge wide bandgap power semiconductor module according to an embodiment of the present invention;

fig. 18 is a layer 2 schematic diagram of a multilayer packaging layer structure in a full-bridge wide bandgap power semiconductor module according to an embodiment of the invention;

fig. 19 is a schematic diagram of layer 3 of a multilayer packaging layer structure in a full-bridge wide bandgap power semiconductor module according to an embodiment of the invention;

fig. 20 is a schematic diagram of layer 4 of a multilayer packaging layer structure in a full-bridge wide bandgap power semiconductor module according to an embodiment of the present invention;

fig. 21 is a schematic diagram of layer 5 of a multilayer packaging layer structure in a full-bridge wide bandgap power semiconductor module according to an embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1, fig. 2, and fig. 3, an embodiment of the invention provides a wide bandgap power semiconductor module package structure 10, which includes a single device wide bandgap power semiconductor module 20, a half-bridge wide bandgap power semiconductor module 30, or a full-bridge wide bandgap power semiconductor module 40, which is composed of a driving isolation protection circuit 101 and a wide bandgap power semiconductor device 102 (in the embodiment of the invention, a 650V GaN chip is taken as an example), and only the single device wide bandgap power semiconductor module is taken as an example in fig. 1, fig. 2, and fig. 3 for explanation. The specific structural principles and wide bandgap power semiconductor module package structures of the single device wide bandgap power semiconductor module 20, the half bridge wide bandgap power semiconductor module 30, and the full bridge wide bandgap power semiconductor module 40 are shown in the following embodiments.

The drive isolation protection circuit 101 and the wide bandgap power semiconductor device 102 are encapsulated in different layers in a multilayer encapsulation layer structure 103; the multilayer packaging layer structure 103 integrally packages the drive isolation protection circuit 101 and the wide bandgap power semiconductor device 102.

The driving isolation protection circuit 101 is provided with a Pulse Width Modulation (PWM) input interface, a driving power input interface, and a driving isolation control interface 110; the driving isolation control interface 110 is connected to the gate 104 of the wide bandgap power semiconductor device 102 through via holes of the multi-layered packaging layer structure 103 (holes that can be formed through each layer in the multi-layered packaging layer structure and can be generally used in cooperation with copper pillars for circuit connection) through packaging layers in the multi-layered packaging layer structure 103 (i.e., each layer in the multi-layered packaging layer structure 103); the pulse width modulation signal input interface and the driving power supply input interface respectively penetrate through the packaging layers in the multilayer packaging layer structure 103 through via holes of the multilayer packaging layer structure 103, and a pulse width modulation signal input interface connection point 106 and a driving power supply input interface connection point 107 are formed on the upper surface 105 of the multilayer packaging layer structure 103; the drain 108 and the source 109 of the wide bandgap power semiconductor device 102 expose the multi-layer package layer structure 103, and a power loop interface connection point is formed on the upper surface 105 of the multi-layer package layer structure 103.

Further, the multi-layer package layer structure 103 may be made of low temperature co-fired Ceramic (L ow temperature co-fired Ceramic, L TCC for short).

Further, as shown in fig. 4, a lower surface 111 of the multi-layer encapsulation layer structure 103 is connected to a heat sink 113 (short for Cooling) through a thermal conductive filling material 112.

Further, as shown in fig. 4, the pwm signal input interface connection point 106, the driving power input interface connection point 107, and the power loop interface connection point (i.e., the drain 108 and the source 109 of the wide bandgap power semiconductor device 102) on the upper surface 105 of the multi-layered packaging layer structure 103 are connected to the circuit wiring of the external printed circuit board 50. As can be seen from fig. 1, the pwm signal input interface connection point 106, the driving power input interface connection point 107, and the power circuit interface connection point are exposed on the upper surface 105, and therefore, can be connected to the circuit wiring of the external printed circuit board 50, and only the position of the external printed circuit board 50 is shown in fig. 4.

Specifically, as shown in fig. 5, the single device wide bandgap power semiconductor module 20 includes a first driving isolation protection circuit 201 and a first group of wide bandgap power semiconductor devices 202; the first group of wide bandgap power semiconductor devices 202 includes one wide bandgap power semiconductor device 102. In addition, as shown in fig. 6, the first group of wide bandgap power semiconductor devices 202 may further include a plurality of wide bandgap power semiconductor devices 102, and the principle is that the gate, the drain and the source of each wide bandgap power semiconductor device 102 need to be connected together.

As shown in fig. 5 and 7, the first driving isolation protection circuit 201 is provided with a pulse width modulation signal input interface, a driving power input interface, a driving isolation control interface and a power ground interface; the pulse width modulation signal input interface, the driving power supply input interface, the driving isolation control interface and the power grounding interface penetrate through a packaging layer in the multilayer packaging layer structure through via holes of the multilayer packaging layer structure and are exposed out of the upper surface of the multilayer packaging layer structure to form a pulse width modulation signal input interface connection point 203, a driving power supply input interface connection point 204, a driving isolation control interface connection point 205 and a power grounding interface connection point 206; the drain, source and gate of the wide bandgap power semiconductor device 102 are exposed from the multi-layer packaging layer structure, and a drain connection point 207, a source connection point 208 and a gate connection point 209 are formed on the upper surface of the multi-layer packaging layer structure. The pulse width modulation signal input interface connection point 203, the driving power input interface connection point 204, the driving isolation control interface connection point 205, the power ground interface connection point 206, the drain connection point 207, the source connection point 208 and the gate connection point 209 are welded to a circuit wiring 210 of an external printed circuit board, so that the pulse width modulation signal input interface connection point 203 is connected with an external pulse width modulation signal (PWM signal), the driving power input interface connection point 204 is connected with an external driving power, the driving isolation control interface connection point 205 is connected with the gate connection point 209, the power ground interface connection point 206 is connected with the source connection point 208, and the source connection point 208 and the drain connection point 207 form a power loop interface connection point to be connected with an external application circuit (not shown in the figure).

In addition, as shown in fig. 8, if the first group of wide bandgap power semiconductor devices 202 includes a plurality of wide bandgap power semiconductor devices 102, the drains, sources and gates of the plurality of wide bandgap power semiconductor devices 102 are exposed out of the multi-layer package structure, and a drain connection point 207, a source connection point 208 and a gate connection point 209 are formed on the upper surface of the multi-layer package structure; thus, in fig. 8, the drive isolation control interface connection points 205 are connected to respective gate connection points 209, the respective drive isolation control interface connection points 205 are connected together within the multi-layer package structure through vias in the multi-layer package structure, the power ground interface connection points 206 are connected to respective source connection points 208, the respective source connection points 208 are connected together, the respective drain connection points 207 are connected together, and the connected source connection points 208 and the connected drain connection points 207 form a power loop interface connection point (not shown) for connection to an external application circuit.

Specifically, as shown in fig. 9, the half-bridge wide bandgap power semiconductor module 30 includes a first driving isolation protection circuit 301, a second driving isolation protection circuit 302, a first group of wide bandgap power semiconductor devices 303, and a second group of wide bandgap power semiconductor devices 304; the first group of wide bandgap power semiconductor devices 303 and the second group of wide bandgap power semiconductor devices 304 each comprise a wide bandgap power semiconductor device 102; in addition, as shown in fig. 6, the first group 303 and the second group 304 of wide bandgap power semiconductor devices each include the same number of multiple wide bandgap power semiconductor devices 102, and the principle is that the gate, the drain and the source of each wide bandgap power semiconductor device 102 in each group need to be connected together.

As shown in fig. 10, 11, 12, 13, and 14, the multi-layer encapsulation layer structure 103 may include a plurality of encapsulation layers, for example, layer 1, layer 2, layer 3, and layer 4, respectively. As shown in fig. 10 and 11, two pads for placing the first group 303 and the second group 304 of wide bandgap power semiconductor devices, respectively, are provided on layer 1. In addition, the first driving isolation protection circuit 301 is provided with a first pulse width modulation signal input interface and a first driving isolation control interface; the second driving isolation protection circuit 302 is provided with a second pulse width modulation signal input interface and a second driving isolation control interface; the first driving isolation protection circuit 301 and the second driving isolation protection circuit 302 are provided with the same driving power input interface and the same driving ground interface. As shown in fig. 10 and 12, the first drive isolation control interface (not shown) is connected to the gate 306 of the first group of wide bandgap power semiconductor devices 303 through the copper pillar in the via hole of the multi-layer encapsulation layer structure 103 (the connection structure through the layers in fig. 10, and the circles in fig. 12, 13 and 14 may all represent the copper pillar); the second drive isolation control interface (not shown) is connected to the gates 307 of the second group of wide bandgap power semiconductor devices 304 through copper pillars in the vias of the multi-layer package layer structure 103. As shown in fig. 10, fig. 12, fig. 13 and fig. 14, the sources 308 of the first group of wide bandgap power semiconductor devices 303 and the drains 309 of the second group of wide bandgap power semiconductor devices 304 are connected together inside the multi-layer package layer structure 103 and serve as an output pin interface; the first pulse width modulation signal input interface, the second pulse width modulation signal input interface, the driving power supply input interface, the driving grounding interface and the output pin interface, and the drain 310 of the first group of wide bandgap power semiconductor devices 303 and the source 311 of the second group of wide bandgap power semiconductor devices 304 respectively pass through the packaging layers in the multi-layer packaging layer structure 103 through the copper pillars in the vias of the multi-layer packaging layer structure 103, a first pwm signal input interface in-line pin 313, a second pwm signal input interface in-line pin 314, a driving power input interface in-line pin 315, a driving ground interface in-line pin 316, an Output pin interface in-line pin 317 (Output for short), a power loop Bus positive in-line pin 318 (Bus for short), and a power loop Bus negative in-line pin 319 (Bus for short) are respectively formed exposed on the upper surface 312 of the multi-layer package layer structure 103.

Thus, the first pwm signal input interface in-line pin 313, the second pwm signal input interface in-line pin 314, the driving power input interface in-line pin 315, the driving ground interface in-line pin 316, the output pin interface in-line pin 317, the power circuit bus bar positive electrode in-line pin 318, and the power circuit bus bar negative electrode in-line pin 319 are connected to the circuit wiring (not shown) of the external pcb, the first pwm signal input interface in-line pin 313 and the second pwm signal input interface in-line pin 314 are made to access the external pwm signal, the driving power input interface in-line pin 315 is connected to an external driving power, the driving ground interface in-line pin 316 is grounded, so that the output pin interface in-line pin 317, the power loop bus bar positive in-line pin 318, and the power loop bus bar negative in-line pin 319 are connected as a power loop interface to an external application circuit.

In addition, if the first group of wide bandgap power semiconductor devices 303 and the second group of wide bandgap power semiconductor devices 304 each include the same number of multiple wide bandgap power semiconductor devices 102, the gates of the wide bandgap power semiconductor devices 102 in the first group of wide bandgap power semiconductor devices 303 are connected together inside the multi-layer packaging layer structure 103 to serve as the gate 306 of the first group of wide bandgap power semiconductor devices 303; the drains of the wide bandgap power semiconductor devices 102 in the first group of wide bandgap power semiconductor devices 303 are connected together inside the multilayer packaging layer structure 103 to serve as the drain 310 of the first group of wide bandgap power semiconductor devices 303; the sources of the wide bandgap power semiconductor devices 102 in the first group of wide bandgap power semiconductor devices 303 are connected together inside the multilayer packaging layer structure 103 to serve as the source 308 of the first group of wide bandgap power semiconductor devices 303; the gates of the wide bandgap power semiconductor devices 102 in the second group of wide bandgap power semiconductor devices 304 are connected together inside the multi-layer packaging layer structure 103 to serve as the gate 307 of the second group of wide bandgap power semiconductor devices 304; the drains of the wide bandgap power semiconductor devices 102 in the second group of wide bandgap power semiconductor devices 304 are connected together inside the multi-layer packaging layer structure 103 to serve as the drain 309 of the second group of wide bandgap power semiconductor devices 304; the sources of the wide bandgap power semiconductor devices 102 in the second group of wide bandgap power semiconductor devices 304 are connected together inside the multi-layer package layer structure 103 to serve as the source 311 of the second group of wide bandgap power semiconductor devices 304.

Specifically, as shown in fig. 15, the full-bridge wide bandgap power semiconductor module 40 includes a first driving isolation protection circuit 401, a second driving isolation protection circuit 402, a third driving isolation protection circuit 403, a fourth driving isolation protection circuit 404, a first group of wide bandgap power semiconductor devices 405, a second group of wide bandgap power semiconductor devices 406, a third group of wide bandgap power semiconductor devices 407, and a fourth group of wide bandgap power semiconductor devices 408; the first group of wide bandgap power semiconductor devices 405, the second group of wide bandgap power semiconductor devices 406, the third group of wide bandgap power semiconductor devices 407 and the fourth group of wide bandgap power semiconductor devices 408 each comprise one wide bandgap power semiconductor device 102; in addition, as shown in fig. 6, each of the first group 405, the second group 406, the third group 407, and the fourth group 408 includes a plurality of wide bandgap power semiconductor devices 102, and the principle is that the gate, the drain, and the source of each wide bandgap power semiconductor device 102 in each group need to be connected together.

As shown in fig. 16, 17, 18, 19, 20, 21, the multi-layer encapsulation layer structure 103 may include a plurality of encapsulation layers, for example, layer 1, layer 2, layer 3, layer 4, layer 5, respectively. As shown in fig. 16 and 17, four pads for placing a first group of wide bandgap power semiconductor devices 405, a second group of wide bandgap power semiconductor devices 406, a third group of wide bandgap power semiconductor devices 407, and a fourth group of wide bandgap power semiconductor devices 408, respectively, are provided on layer 1. In addition, the first driving isolation protection circuit 401 is provided with a first pulse width modulation signal input interface and a first driving isolation control interface; the second driving isolation protection circuit 402 is provided with a second pulse width modulation signal input interface and a second driving isolation control interface; the third driving isolation protection circuit 403 is provided with a third pulse width modulation signal input interface and a third driving isolation control interface; the fourth driving isolation protection circuit 404 is provided with a fourth pulse width modulation signal input interface and a fourth driving isolation control interface; the first driving isolation protection circuit 401, the second driving isolation protection circuit 402, the third driving isolation protection circuit 403 and the fourth driving isolation protection circuit 404 are provided with a same driving power input interface and a same driving grounding interface. As shown in fig. 16 and 18, the first drive isolation control interface (not shown) is connected to the gate 409 of the first group of wide bandgap power semiconductor devices 405 through the copper pillar in the via hole of the multi-layer packaging layer structure 103 (the connection structure through the layers in fig. 16, and the circles in fig. 18 to 21 may all represent the copper pillar); the second drive isolation control interface (not shown) is connected with the gates 410 of the second group of wide bandgap power semiconductor devices 406 through the copper pillars in the vias of the multi-layer packaging layer structure 103; the third driving isolation control interface (not shown in the figure) is connected with the gate 411 of the third group of wide bandgap power semiconductor devices 407 through the copper pillar in the via hole of the multi-layer packaging layer structure 103; the fourth driving isolation control interface (not shown) is connected to the gates 412 of the fourth group 408 of wide bandgap power semiconductor devices through the copper pillars in the vias of the multi-layered packaging layer structure 103. As shown in fig. 16 and fig. 18 to fig. 21, the source 413 of the first wide bandgap power semiconductor device 405 and the drain 414 of the second wide bandgap power semiconductor device 406 are connected together inside the multi-layer package layer structure 103 and serve as a first output pin interface; the source 415 of the third group of wide bandgap power semiconductor devices 407 and the drain 416 of the fourth group of wide bandgap power semiconductor devices 408 are connected together inside the multi-layer package layer structure 103 and serve as a second output pin interface. The

drains

417 and 418 of the first and third groups of wide bandgap

power semiconductor devices

405 and 407 are connected together within the multilayer packaging layer structure 103; the sources 419 of the second group of wide bandgap power semiconductor devices 406 and the sources 420 of the fourth group of wide bandgap power semiconductor devices 408 are connected together inside the multi-layer package level structure 103. The first pwm signal input interface, the second pwm signal input interface, the third pwm signal input interface, the fourth pwm signal input interface, the driving power input interface, the driving ground interface, the first output pin interface, the second output pin interface, the drain 417 of the first group of wide bandgap power semiconductor devices 405 and the drain 418 of the third group of wide bandgap power semiconductor devices 407, and the source 419 of the second group of wide bandgap power semiconductor devices 406 and the source 420 of the fourth group of wide bandgap power semiconductor devices 408 respectively penetrate through the package layers in the multilayer package layer structure 103 through the copper posts in the vias of the multilayer package layer structure 103, are exposed on the upper surface of the multilayer package layer structure 103, and respectively form a first pwm signal input interface in-line pin 422, a second pwm signal input interface in-line pin 423, a first pulse width modulation signal input interface in-line pin 421, a second pulse width modulation signal input interface in-line pin 421, and a third pulse width modulation signal input interface, A third pwm signal input interface in-line pin 424, a fourth pwm signal input interface in-line pin 425, a driving power input interface in-line pin 426, a driving ground interface in-line pin 427, a first Output pin interface in-line pin 428 (Output 1 for short), a second Output pin interface in-line pin 429 (Output 2 for short), a power loop Bus bar positive in-line pin 430 (Bus +) for short, and a power loop Bus bar negative in-line pin 431 (Bus-) for short.

The first pwm signal input interface in-line pin 422, the second pwm signal input interface in-line pin 423, the third pwm signal input interface in-line pin 424, the fourth pwm signal input interface in-line pin 425, the driving power input interface in-line pin 426, the driving ground interface in-line pin 427, the first output pin interface in-line pin 428, the second output pin interface in-line pin 429, the power loop bus bar positive in-line pin 430, and the power loop bus bar negative in-line pin 431 are connected to the circuit wiring (not shown) of the external pcb, so that the first pwm signal input interface in-line pin 422, the second pwm signal input interface in-line pin 423, the third pwm signal input interface in-line pin 424, and the fourth pwm signal input interface in-line pin 425 are connected to the external pwm signal, the driving power input interface in-line pin 426 is connected to an external driving power, the driving ground interface in-line pin 427 is grounded, and the first output pin interface in-line pin 428, the second output pin interface in-line pin 429, the power loop bus positive in-line pin 430, and the power loop bus negative in-line pin 431 are used as power loop interfaces to be connected to an external application circuit.

In addition, if the first group of wide bandgap power semiconductor devices 405, the second group of wide bandgap power semiconductor devices 406, the third group of wide bandgap power semiconductor devices 407 and the fourth group of wide bandgap power semiconductor devices 408 each include a plurality of wide bandgap power semiconductor devices 102 of the same number, gates of the wide bandgap power semiconductor devices 102 in the first group of wide bandgap power semiconductor devices 405 are connected together inside the multi-layer packaging layer structure 103 to serve as the gate 409 of the first group of wide bandgap power semiconductor devices 405; the drains of the wide bandgap power semiconductor devices 102 in the first group of wide bandgap power semiconductor devices 405 are connected together inside the multilayer packaging layer structure 103 to serve as the drain 417 of the first group of wide bandgap power semiconductor devices 405; the sources of the wide bandgap power semiconductor devices 102 in the first group of wide bandgap power semiconductor devices 405 are connected together inside the multi-layer package layer structure 103 as the source 413 of the first group of wide bandgap power semiconductor devices 405.

The gates of the wide bandgap power semiconductor devices 102 in the second group of wide bandgap power semiconductor devices 406 are connected together inside the multi-layer packaging layer structure 103 as the gates 410 of the second group of wide bandgap power semiconductor devices 406; the drains of the wide bandgap power semiconductor devices 102 in the second group of wide bandgap power semiconductor devices 406 are connected together inside the multi-layer packaging layer structure 103 to serve as the drain 414 of the second group of wide bandgap power semiconductor devices 406; the sources of the wide bandgap power semiconductor devices 102 in the second group of wide bandgap power semiconductor devices 406 are connected together inside the multi-layer package layer structure 103 to serve as the source 419 of the second group of wide bandgap power semiconductor devices 406.

The gates of the wide bandgap power semiconductor devices 102 in the third group of wide bandgap power semiconductor devices 407 are connected together inside the multi-layer packaging layer structure 103 to serve as the gate 411 of the third group of wide bandgap power semiconductor devices 407; the drains of the wide bandgap power semiconductor devices 102 in the third group of wide bandgap power semiconductor devices 407 are connected together inside the multi-layer package layer structure 103 to serve as the drain 418 of the third group of wide bandgap power semiconductor devices 407; the sources of the wide bandgap power semiconductor devices 102 in the third group of wide bandgap power semiconductor devices 407 are connected together inside the multi-layer package layer structure 103 to serve as the source 415 of the third group of wide bandgap power semiconductor devices 407.

The gates of the wide bandgap power semiconductor devices 102 in the fourth group of wide bandgap power semiconductor devices 408 are connected together inside the multi-layer encapsulation layer structure 103 as the gate 412 of the fourth group of wide bandgap power semiconductor devices 408; the drains of the wide bandgap power semiconductor devices 102 in the fourth group of wide bandgap power semiconductor devices 408 are connected together inside the multi-layer package layer structure 103 as the drain 416 of the fourth group of wide bandgap power semiconductor devices 408; the sources of the wide bandgap power semiconductor devices 102 in the fourth group of wide bandgap power semiconductor devices 408 are connected together inside the multi-layer package layer structure 103 to serve as the source 420 of the fourth group of wide bandgap power semiconductor devices 408.

According to the wide bandgap power semiconductor module packaging structure provided by the embodiment of the invention, as the wide bandgap power semiconductor module packaging structure comprises a single-device structure wide bandgap power semiconductor module, a half-bridge structure wide bandgap power semiconductor module or a full-bridge structure wide bandgap power semiconductor module which consists of a drive isolation protection circuit and a wide bandgap power semiconductor device, the wide bandgap power semiconductor module packaging structure provided by the invention has various optional configurations, so that the wide bandgap power semiconductor module packaging structure is suitable for various application circuit topologies; in addition, the drive isolation protection circuit and the wide bandgap power semiconductor device are packaged in different layers in a multilayer packaging layer structure; the multilayer packaging layer structure packages the drive isolation protection circuit and the wide bandgap power semiconductor device into a whole; a driving isolation control interface of the driving isolation protection circuit penetrates through a packaging layer in the multi-layer packaging layer structure through a through hole of the multi-layer packaging layer structure and is connected with a gate pole of the wide bandgap power semiconductor device; the pulse width modulation signal input interface and the driving power supply input interface of the driving isolation protection circuit respectively penetrate through a packaging layer in the multi-layer packaging layer structure through via holes of the multi-layer packaging layer structure, and a pulse width modulation signal input interface connection point and a driving power supply input interface connection point are formed on the upper surface of the multi-layer packaging layer structure; the drain electrode and the source electrode of the wide bandgap power semiconductor device are exposed out of the multilayer packaging layer structure, and a power loop interface connection point is formed on the upper surface of the multilayer packaging layer structure. The multilayer packaging layer structure is adopted, and the device connection among the layers is completed through the through holes, so that the whole wide bandgap power semiconductor module packaging structure is high in integration level and small in size, the parasitic parameters of the whole circuit are reduced, and the problems that the working characteristics of the wide bandgap power semiconductor device with high switching frequency cannot be exerted and the switching frequency of a power semiconductor module is limited in the prior art can be solved. In addition, the wide bandgap power semiconductor module packaging structure provided by the embodiment of the invention has the characteristics of simple structure, convenience in installation, high heat dissipation efficiency and mechanical shock resistance.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The principle and the implementation mode of the invention are explained by applying specific embodiments in the invention, and the description of the embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A wide bandgap power semiconductor module packaging structure is characterized by comprising a single-device wide bandgap power semiconductor module, a half-bridge wide bandgap power semiconductor module or a full-bridge wide bandgap power semiconductor module, wherein the single-device wide bandgap power semiconductor module is composed of a drive isolation protection circuit and a wide bandgap power semiconductor device;

2. The wide bandgap power semiconductor module package structure of claim 1, wherein the multilayer package layer structure is made of low temperature co-fired ceramic material.

3. The wide bandgap power semiconductor module package structure of claim 2, wherein the lower surface of the multi-layer package layer structure is connected to the heat spreader through a thermally conductive filler material.

4. The wide bandgap power semiconductor module package structure of claim 3, wherein the PWM signal input interface connection point, the driving power input interface connection point and the power loop interface connection point on the upper surface of the multi-layered package layer structure are connected to circuit traces of an external printed circuit board.

5. The package structure of claim 4, wherein the single device wide bandgap power semiconductor module comprises a first drive isolation protection circuit and a first group of wide bandgap power semiconductor devices; the first group of wide bandgap power semiconductor devices comprises a wide bandgap power semiconductor device;

6. The package structure of claim 4, wherein the single device wide bandgap power semiconductor module comprises a first drive isolation protection circuit and a first group of wide bandgap power semiconductor devices; the first group of wide bandgap power semiconductor devices comprises a plurality of wide bandgap power semiconductor devices;

7. The package structure of claim 4, wherein the half-bridge wide bandgap power semiconductor module comprises a first drive isolation protection circuit, a second drive isolation protection circuit, a first group of wide bandgap power semiconductor devices, and a second group of wide bandgap power semiconductor devices; the first group of wide bandgap power semiconductor devices and the second group of wide bandgap power semiconductor devices respectively comprise a wide bandgap power semiconductor device;

8. The package structure of claim 4, wherein the half-bridge wide bandgap power semiconductor module comprises a first drive isolation protection circuit, a second drive isolation protection circuit, a first group of wide bandgap power semiconductor devices, and a second group of wide bandgap power semiconductor devices; the first group of wide bandgap power semiconductor devices and the second group of wide bandgap power semiconductor devices respectively comprise a plurality of wide bandgap power semiconductor devices with the same number;

9. The package structure of claim 4, wherein the full-bridge wide bandgap power semiconductor module comprises a first driving isolation protection circuit, a second driving isolation protection circuit, a third driving isolation protection circuit, a fourth driving isolation protection circuit, a first group of wide bandgap power semiconductor devices, a second group of wide bandgap power semiconductor devices, a third group of wide bandgap power semiconductor devices, and a fourth group of wide bandgap power semiconductor devices; the first group of wide bandgap power semiconductor devices, the second group of wide bandgap power semiconductor devices, the third group of wide bandgap power semiconductor devices and the fourth group of wide bandgap power semiconductor devices respectively comprise a wide bandgap power semiconductor device;

10. The package structure of claim 4, wherein the full-bridge wide bandgap power semiconductor module comprises a first driving isolation protection circuit, a second driving isolation protection circuit, a third driving isolation protection circuit, a fourth driving isolation protection circuit, a first group of wide bandgap power semiconductor devices, a second group of wide bandgap power semiconductor devices, a third group of wide bandgap power semiconductor devices, and a fourth group of wide bandgap power semiconductor devices; the first group of wide bandgap power semiconductor devices, the second group of wide bandgap power semiconductor devices, the third group of wide bandgap power semiconductor devices and the fourth group of wide bandgap power semiconductor devices respectively comprise a plurality of wide bandgap power semiconductor devices with the same number;