CN108986014A - It is applicable in the pel assembly unit of out-of-order vertex coloring - Google Patents
It is applicable in the pel assembly unit of out-of-order vertex coloring Download PDFInfo
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- CN108986014A CN108986014A CN201810798858.5A CN201810798858A CN108986014A CN 108986014 A CN108986014 A CN 108986014A CN 201810798858 A CN201810798858 A CN 201810798858A CN 108986014 A CN108986014 A CN 108986014A
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- vertex
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- assembly unit
- pel assembly
- coloring
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- 238000004040 coloring Methods 0.000 title claims abstract description 34
- 238000003860 storage Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 9
- 238000013500 data storage Methods 0.000 claims description 2
- 230000014759 maintenance of location Effects 0.000 claims 1
- 238000009877 rendering Methods 0.000 abstract description 7
- 238000004043 dyeing Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2200/00—Indexing scheme for image data processing or generation, in general
- G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware
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- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Image Generation (AREA)
- Image Processing (AREA)
Abstract
The invention discloses a kind of pel assembly units for being applicable in out-of-order vertex coloring, it is related to graphic chips technical field.The pel assembly unit carries out parallel with vertex coloring, and it vertex random ordering can work in the case where inputting after dyeing, it is specific as follows: first, a call number is added to each vertex, a new attribute as vertex, it is bound together with other attributes, call number is incremented by successively since 0；At the same time, which is passed into pel assembly unit and carries out pel pre-assembled.The rate of vertex coloring can be greatly improved in the present invention, save pel assembly time, improve the efficiency of graphics rendering pipeline, guarantee the orderly integrality of pel assembly result.
Description
Technical field
The present invention relates to graphic chips technical fields, and in particular to a kind of pel assembly for being applicable in out-of-order vertex coloring
Unit.
Background technique
In graphics rendering pipeline, pel assembly is that the sequence and connection relationship for specifying on vertex according to user restore networking
Lattice structure.Vertex is needed first to be dyed before pel assembly, there are two types of modes for vertex coloring: serially and parallel.
Serial vertex coloring may insure that vertex is issued to pel assembly unit by original order, but due to vertex coloring
It is one computationally intensive, then time-consuming more work carries out figure if carrying out vertex coloring according to original vertices sequence one by one
Member assembly, will lead to whole figure rendering pipeline inefficiency.
Parallel vertex coloring runs to complete vertex coloring task using multiple calculating cores parallel, can greatly add in this way
Fast figure rendering speed.But the problem of vertex order not can guarantee is brought, although multiple calculating core operations is same
Vertex coloring program, but be different vertex data and will lead to the different branched program of operation, along with the memory access time can not yet
Together, so vertex output not can guarantee first in first out.Traditional pel assembly unit just not can guarantee opposite vertexes yet and carry out orderly
Complete assembly.
In conclusion the present invention devises a kind of pel assembly unit for being applicable in out-of-order vertex coloring.
Summary of the invention
In view of the shortcomings of the prior art, object of the present invention is to be to provide a kind of figure for being applicable in out-of-order vertex coloring
The rate of vertex coloring can be greatly improved in first assembly unit, save pel assembly time, improve the effect of graphics rendering pipeline
Rate guarantees the orderly integrality of pel assembly result.
To achieve the goals above, the present invention is to realize by the following technical solutions: being applicable in random ordering vertex coloring
Pel assembly unit, the pel assembly unit carries out parallel with vertex coloring, specific as follows: firstly, adding to each vertex
Add a call number, is bound together as a new attribute on vertex and other attributes, call number is successively passed since 0
Increase；At the same time, which is passed into pel assembly unit and carries out pel pre-assembled.
The pel assembly unit is that opposite vertexes call number carries out, and can still complete to be equipped with when the input of vertex random ordering
Sequence output.
The pel pre-assembled carries out pel assembly according to vertex index number, and the vertex index assembled is saved
In index storage.In this way, vertex coloring process and pel assembling process are parallel.
The data stored in the index storage are all vertex index；When vertex coloring process starts output vertex to figure
The on piece that vertex data is stored in pel assembly unit is first stored, and safeguards a record current vertex number by first assembly unit
According to the table of state.The n-th position of table records the storage state for the vertex data that vertex index is N, the storage state
Include two aspects: whether data are stored on the on piece storage of pel assembly, and there are the initial addresses of on piece storage.
The invention has the following advantages:
1, the present invention supports the pel assembly under the output of vertex coloring random ordering, and the rate of vertex coloring can be greatly improved.
2, pel assembly carries out parallel with vertex coloring, saves pel assembly time, improves the effect of graphics rendering pipeline
Rate.
3, this invention ensures that the orderly integrality of pel assembly result.
Detailed description of the invention
The following describes the present invention in detail with reference to the accompanying drawings and specific embodiments；
Fig. 1 is the improved graphics rendering pipeline figure of the present invention；
Fig. 2 is that index of the invention stores schematic diagram；
Fig. 3 is vertex data state table schematic diagram of the invention.
Specific embodiment
To be easy to understand the technical means, the creative features, the aims and the efficiencies achieved by the present invention, below with reference to
Specific embodiment, the present invention is further explained.
Referring to Fig.1-3, present embodiment uses following technical scheme: the pel assembly for being applicable in out-of-order vertex coloring is single
Member, the pel assembly unit carries out parallel with vertex coloring, specific as follows: firstly, adding an index to each vertex
Number, it is bound together as a new attribute on vertex and other attributes, call number is incremented by successively since 0；It is same with this
When, which is passed into pel assembly unit and carries out pel pre-assembled.
So-called pel pre-assembled carries out pel assembly according to vertex index number, and the vertex index assembled is saved
In index storage.In this way, vertex coloring process and pel assembling process are parallel.
Fig. 2 is the schematic diagram of index storage, and the data of storage are all vertex index, and the primitive types of storage are GL_
TRIANGLE_STRIP。
When vertex coloring process starts output vertex to pel assembly unit, it is single that vertex data is first stored in pel assembly
The on piece storage of member, and safeguard the table of a record current vertex data mode.The n-th position of table records vertex rope
It is cited as the storage state of the vertex data of N, which includes two aspects: whether data are stored on pel assembly
On piece storage, there are the initial addresses of on piece storage.
Fig. 3 is the schematic diagram of vertex data state table, and what the position N stored is the data mode on the vertex N.Highest order
The vertex data is represented for 1 to have deposited, and is otherwise represented and is not deposited.Other represent the initial address that the vertex data is stored on piece.
No. 0 vertex has been deposited in figure, and data are 0x0000_0000 in the initial address that on piece stores, and No. 1 vertex is not deposited, and No. 2 vertex are
It deposits, data are 0X0000_0020 in the initial address that on piece stores.
Then pel assembly unit sequence reads vertex index from index storage, and searches vertex data according to the index
State table, until the vertex data storage state of the index is that 1(has been deposited), then the vertex data is exported to assembly line next stage.
The call number of present embodiment is not necessarily since 0, and also not necessarily sequence adds 1.Any front stage agreement
Good index mark is all feasible.
Present embodiment opposite vertexes addition index, the vertex data after vertex coloring is identified with the index, pel dress
It goes to obtain vertex data by index with unit, it can dependence to avoid pel assembly unit to output sequence in vertex after dyeing.
Pel assembly unit carries out pre-assembled to index while graphics pipeline vertex coloring, is equivalent to and has saved assembly time.
The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention.The technology of the industry
Personnel are it should be appreciated that the present invention is not limited to the above embodiments, and the above embodiments and description only describe this
The principle of invention, without departing from the spirit and scope of the present invention, various changes and improvements may be made to the invention, these changes
Change and improvement all fall within the protetion scope of the claimed invention.The claimed scope of the invention by appended claims and its
Equivalent thereof.
Claims (4)
1. being applicable in the pel assembly unit of out-of-order vertex coloring, which is characterized in that the pel assembly unit and vertex coloring
It is parallel to carry out, it is specific as follows: firstly, a call number is added to each vertex, as a new attribute on vertex and other
Attribute is bound together；At the same time, which is passed into pel assembly unit and carries out pel pre-assembled.
2. the pel assembly unit according to claim 1 for being applicable in out-of-order vertex coloring, which is characterized in that the pel
Assembly unit is that opposite vertexes call number carries out, and can still complete assembly order output when the input of vertex random ordering.
3. the pel assembly unit according to claim 1 for being applicable in out-of-order vertex coloring, which is characterized in that the pel
Pre-assembled carries out pel assembly according to vertex index number, and the vertex index assembled is stored in index storage, vertex dye
Color process and pel assembling process are parallel.
4. the pel assembly unit according to claim 2 for being applicable in out-of-order vertex coloring, which is characterized in that the index
The data stored in storage are all vertex index；When vertex coloring process starts output vertex to pel assembly unit, first by top
Point data is stored in the on piece storage of pel assembly unit, and safeguards the table of a record current vertex state data memory,
The table includes three information: call number, and whether data are stored on the on piece storage of pel assembly, and there are on piece storages
Initial address；Pel assembly unit is according to index storage and vertex data storage state Output of for ms vertex.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810798858.5A CN108986014A (en) | 2018-07-19 | 2018-07-19 | It is applicable in the pel assembly unit of out-of-order vertex coloring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810798858.5A CN108986014A (en) | 2018-07-19 | 2018-07-19 | It is applicable in the pel assembly unit of out-of-order vertex coloring |
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| Publication Number | Publication Date |
|---|---|
| CN108986014A true CN108986014A (en) | 2018-12-11 |
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|---|---|---|---|
| CN201810798858.5A Pending CN108986014A (en) | 2018-07-19 | 2018-07-19 | It is applicable in the pel assembly unit of out-of-order vertex coloring |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111080505A (en) * | 2019-12-27 | 2020-04-28 | 西安芯瞳半导体技术有限公司 | Method and device for improving primitive assembly efficiency and computer storage medium |
| CN112991143A (en) * | 2021-05-06 | 2021-06-18 | 南京芯瞳半导体技术有限公司 | Method and device for assembling graphics primitives and computer storage medium |
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| CN101779219A (en) * | 2007-07-30 | 2010-07-14 | 高通股份有限公司 | Scheme for varying packing and linking in graphics systems |
| CN102799431A (en) * | 2012-07-02 | 2012-11-28 | 上海算芯微电子有限公司 | Graphics primitive preprocessing method, graphics primitive processing method, graphic processing method, processor and device |
| CN106683162A (en) * | 2017-01-18 | 2017-05-17 | 天津大学 | Rear vertex Cache design method of multi-shader architecture for embedded GPU |
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2018
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| CN101779219A (en) * | 2007-07-30 | 2010-07-14 | 高通股份有限公司 | Scheme for varying packing and linking in graphics systems |
| CN102799431A (en) * | 2012-07-02 | 2012-11-28 | 上海算芯微电子有限公司 | Graphics primitive preprocessing method, graphics primitive processing method, graphic processing method, processor and device |
| CN106683162A (en) * | 2017-01-18 | 2017-05-17 | 天津大学 | Rear vertex Cache design method of multi-shader architecture for embedded GPU |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111080505A (en) * | 2019-12-27 | 2020-04-28 | 西安芯瞳半导体技术有限公司 | Method and device for improving primitive assembly efficiency and computer storage medium |
| CN111080505B (en) * | 2019-12-27 | 2024-04-12 | 芯瞳半导体技术(山东)有限公司 | Method and device for improving graphic element assembly efficiency and computer storage medium |
| CN112991143A (en) * | 2021-05-06 | 2021-06-18 | 南京芯瞳半导体技术有限公司 | Method and device for assembling graphics primitives and computer storage medium |
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Application publication date: 20181211 |