CN108984109A - The control method of access efficiency is promoted on flash memory - Google Patents
The control method of access efficiency is promoted on flash memory Download PDFInfo
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- CN108984109A CN108984109A CN201710411960.0A CN201710411960A CN108984109A CN 108984109 A CN108984109 A CN 108984109A CN 201710411960 A CN201710411960 A CN 201710411960A CN 108984109 A CN108984109 A CN 108984109A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- General Engineering & Computer Science (AREA)
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- Techniques For Improving Reliability Of Storages (AREA)
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Abstract
The application is to provide a kind of control method that access efficiency is promoted on flash memory, and it includes the following steps.The one of each multiple memory blocks is read to erase number.When this number of erasing be more than one erase upper limit threshold when, or when detect occur in the error checking correction code mistake position total number be more than or equal to one detect wrong threshold value when, this memory block is converted into a single-layer type cell format, extra memory space is temporarily converted to single-layer type cell format by the data compression technique that in addition can arrange in pairs or groups.The data quick area is added in the memory block for being converted into single-layer type cell format, and wherein this data cache area belongs to single-layer type cell format.
Description
Technical field
The application relates to a kind of control method on flash memory, can be promoted on flash memory in particular to one kind
The control method of data access efficiency.
Background technique
Nand flash memory (Flash) be solid state hard disk (SSD) be used to carry, the memory of storing data, solid state hard disk can pass through
The various calculation process of controller (Controller) progress, and any one of these processes details, are likely to influence
The product performance of solid state hard disk, reliability, stability etc..
Flash memory can be divided into single-layer type storage (Single-Level Cell, SLC), multiple field storage on format
(Multiple-Level Cell, MLC) or three-layer type store (Triple-Level Cell, TLC), are with internal storage location
The mode of array carrys out storing data, and internal storage location is by a float gate transistor (floating-gate transistor)
Implementation is carried out, critical electricity needed for this internal storage location is connected is set by the charge number on control float gate transistor
Pressure, and then at least one or more information is stored, and when a specific voltage is applied on the control grid of float gate transistor
When, the on state of float gate transistor will indicate one or more binary systems stored in float gate transistor
Number.
However, when internal storage location can not support voltage level or voltage level be written to drift about completely
(shift) when the problem of or being stained with glutinous (sticky), then mistake will occur for the write-in of data at this time, and the area of such mistake occurs
Block just claims to be failure block (Bad Block).
In general, failure block can divide into two kinds, and one is the events generated in the manufacturing process of nand flash memory
Hinder block, referred to as early stage bad block (Early Bad Block), it is another then be during use, with being written, erase
Number of operations increases, and gradually generates failure block, and such block is then known as later period bad block (Latter Bad Block).
It is further illustrated, a failure block can be according to error checking correction code (Error Detection and
Correction code, ECC code) number judged.In nand flash memory, each page (page) can be adjoint
The ECC code of a regular length, when be written a data so far page and when mistake occurs, if the bit length that mistake occurs is less than
Regular length, then this data can be repaired using this ECC code, conversely, once be greater than this regular length when, then
This page is not just available ECC code and carrys out self-regeneration, and controller will will be judged as a faulty section using block comprising this page
Block.
Existing failure block management schemes are by being reached using controller, this controller can be detected and indicate NAND
Failure block in flash memory, to promote the reliability (Reliability) of data access.It carefully says, the faulty section of controller
Block administrative mechanism can establish a failure block table (Bad Block Table) when first time starting nand flash memory, thereafter, control
The failure block judged can be also recorded in this table by device processed during use, with prevent any data be written into
The failure block that this failure block table is recorded.
In existing failure block management schemes, it is judged as not made again forever using block for failure block
Therefore value if the use block of failure block can be properly likely to become using those, makes it before becoming failure block
It separately can produce additional function, can will effectively promote the service efficiency of solid state hard disk, and the waste in avoidable cost.
Summary of the invention
The problem of in view of above-mentioned prior art, the purpose of the application are exactly to provide one kind promotion access effect on flash memory
The control method of energy, it includes the following steps.The one of each multiple memory blocks is read to erase number.When this number of erasing is more than
One erase upper limit threshold when, this memory block is converted into a single-layer type cell format.This is converted into single-layer type cell format
Memory block the data quick area is added, wherein this data cache area is to belong to single-layer type cell format.
Preferably, each multiple memory blocks include multiple data memory pages.
Preferably, control method of the invention more may include following steps.Reading each multiple data memory pages is included
An error checking correction code.Wrong threshold is detectd more than or equal to one when detecting the position total number that mistake occurs in error checking correction code
When value, this memory block is converted into the single-layer type cell format.
Preferably, this data quick area is converted by an extra memory space of flash memory.
Preferably, this extra memory space is to execute data contracting by data of the described control unit to a write-in to flash memory
Subtract technology and is formed.
Detailed description of the invention
Fig. 1 is host system and memory storage device depicted in the embodiment of the present application.
Fig. 2 is flash memory and host system depicted in the application.
Fig. 3 is the first step flow chart of the control method that access efficiency is promoted on flash memory of the application.
Fig. 4 is the second step flow chart of the control method that access efficiency is promoted on flash memory of the application.
Specific embodiment
The effect of understanding technical characteristic, content and advantage of the invention for benefit and its can reach, hereby cooperates the application
Attached drawing, and detailed description are as follows with the expression-form of embodiment, and wherein used attached drawing, purport are only to illustrate and assist
The use of specification, actual proportions and precisely configuration after may not implementing for the application, therefore not should just appended attached drawing ratio and
Configuration relation is interpreted, limitation the application is in the interest field in actual implementation, and conjunction is first chatted bright.
Referring to Fig. 1, it is host system and memory storage device depicted in the embodiment of the present application.In general, interior
Depositing storage device 22 may include a controller 221 and memory chip 222, and wherein this memory chip 222 is usually one non-volatile
Memory, and this memory storage device 22 is used in conjunction with a host system 21.Host system 21 data can be written to
This memory storage device 22, or this data is read from memory storage device 22.And this memory storage device 22 generally can be a U
The duplicative non-voltile memory storage device of disk, memory card or solid state hard disk (Solid State Drive, SSD) etc..
As shown, the host system 21 of the application include a computer 211 and an input/output equipment 212, wherein this
Computer 211 may include a central processing unit 2111,2112 (Dynamic Random Access of a dynamic random access memory
Memory, DRAM), a system bus 2113 and a data transmission interface 2114, input/output equipment 212 may include mouse, key
Disk, screen, printer, microphone and loudspeaker etc..It is understood, however, that the input/output equipment 212 of the application is not
It is confined to above-mentioned device, more may include other devices.System bus 2113 can connect central processing unit 2111, a dynamic random
Access memory 2112 and data transmission interface 2114 can be used to reduce cost and promote modularization.
In an embodiment of the present invention, memory storage device 22 is carried out by data transmission interface 2114 and computer 211
Connection.Be further illustrated, computer 211 can by central processing unit 2111, dynamic random access memory 2112 and output/
The operation of input equipment 212 writes data into memory storage device 22, or reads data from memory storage device 22,
Wherein this data transmission interface 2114 may include SCSI (Small Computer System Interface), ATA
(Advanced Technology Attachment), SAS (Serial Attached SCSI) or SATA (Serial
Advanced Technology Attachment) interface.
Referring to Fig. 2, it is flash memory and host system depicted in the application, and also referring to master depicted in Fig. 1
Machine system and memory storage device.In the present embodiment, flash memory 10 is the memory storage device 22 in Fig. 1, and this flash memory 10
It is attached by connector 15 and host system 21, wherein the coffret in this connector 15 includes the data in the 1st figure
Coffret 2114, and this connector 15 itself can be a SATA connector, SAS connector, iSCSI connector, USB connection
Device or M.2 connector, and flash memory 10 itself then flash memory can be stored for a multiple field or a three-layer type stores flash memory.
It in the present embodiment, may include a data quick area 12, a control unit 11 and multiple memory blocks in flash memory 10
13, this control unit 11 be to execute multiple logic gates or control instruction with hardware pattern or firmware pattern implementation, and
And the operation such as the write-in of data is carried out in memory block 13 according to the instruction of host system 21, reads and erases.Memory block
13 be to store the data being written from host, and its control unit 11 carried out in flash memory 10 when data are erased one most
Subsection, in the present embodiment, the format of this memory block 13 can be a multiple field cell format or a three-layer type cell format,
That is, this memory block 13 itself can belong to multiple field storage flash memory or three-layer type storage flash memory.
In this application, data cache area 12 belongs to a single-layer type cell format, by multiple field cell format above-mentioned
Or three-layer type cell format converts.It is described in more detail, in the present embodiment, data quick area 12 belongs to originally in memory block
Multiple field is stored flash memory by the execution of firmware or three-layer type stores flash memory and is modeled to single-layer type cell by 13 some
The writing mode of formula, and then be used as cache.In addition, in the present embodiment, memory block 13 and this data quick area 12 are
Be electrically connected to control unit 11, wherein using firmware simulate single-layer type cell format writing mode be related fields in both
Some prior arts, therefore not in this to go forth.
Fig. 3 and Fig. 4 is please referred to, is the first step stream of the control method for promoting access efficiency on flash memory of the application
Journey figure and second step flow chart.As shown in Fig. 3, the control method that access efficiency is promoted on this flash memory may include following step
Suddenly.
What step S11 read each multiple memory blocks one erases number.
Step S12 be when this number of erasing be more than one erase upper limit threshold when, this memory block is converted into a single-layer type
Cell format, wherein then this upper limit threshold of erasing can be 3000 times when this memory block belongs to multiple field storage flash memory, if
Belong to three-layer type storage flash memory, then upper limit threshold of erasing can be then 500 times.
The data quick area is added in the memory block that step S13 is converted into single-layer type cell format, wherein this data
Cache area belongs to single-layer type cell format.
Above-mentioned step S11~S13 can be operated by control unit.About above-mentioned memory block and data quick
Area may belong to the same memory crystal grain (die) or belong to different memory crystal grain, and each memory block can separately include more
A data memory page.For example, a memory block can be made of 128 data memory pages, it is appreciated, however, that
It is that the application is not limited thereto, memory block can also be by 64 data memory pages or 256 data storage page institute groups
At wherein each data memory page may include the user data position area (user data) and the position area redundancy (redundancy), preceding
Data of the person to store user, the latter is to memory system data, such as an error checking correction code (Error Checking&
Correction Code)。
In addition, the data memory page for belonging to the same memory block can be written independently data, and can be in the same time
Data in same memory block of erasing on all data memory pages.In more detail, data memory page is control unit progress
Minimum unit when write-in and reading.
In a preferred embodiment, the control method of the application more may include following steps.
Step S21 is the error checking correction code for reading each multiple data memory pages and being included.
Step S22 is to detect mistake when the position total number for detecting generation mistake in the error checking correction code is more than or equal to one
When threshold value, this memory block is converted into single-layer type cell format, wherein this size for detecing wrong threshold value can voluntarily be made by user
It is fixed.
In one embodiment, data quick area can be converted by an extra memory space of flash memory, and wherein this extra is deposited
Storage space is to be executed a data reducti techniques by data of the control unit to a write-in to flash memory and formed.
It further explains, this data reducti techniques is to reach higher using the concept of data entropy (Data Entropy)
Efficiency.When transferring data to flash memory using this data reducti techniques, it will use deleting duplicated data technology, compression skill
Art or data alienation (Data Differencing) technology etc. rearrange information, this can allow Global Information to occupy memory block
Less storage position on block.And after data are read from flash memory, data reducti techniques can be complete by original content by designing
Portion recovers in main system, so technology is also known as lossless formula (Loss-less) data reducti techniques.
It is practical at this time to be written to needed for memory block when using this data reducti techniques to transfer data to flash memory
Size must be less than the actual size of this data, and the space being had more is the extra memory space of the application.For example, if
This flash memory is that a multiple field stores flash memory, and the total capacity size of the memory block of this flash memory is 128GB.When an actual size is
After so far memory block is written by data reducti techniques in the data of 128GB, the space size actually occupied is
120GB, the then 8GB for leaving unused out at this time belong to an extra memory space, and user can be by the lattice of this extra memory space
Formula is converted to that service life is longer and the faster single-layer type cell format of writing speed, and fast as the data on this flash memory
The effect of taking area, and then reaching the access efficiency for increasing this flash memory.
In summary, the control method of the application can properly using be likely to become failure block use block,
It is converted into single-layer type cell using the error checking correction code of erase number and the data memory page of memory block
The foundation of formula, the memory block that can will likely become failure is converted to cache block, and then effectively increases whole flash memory
Access efficiency.
The foregoing is merely illustratives, rather than are restricted person.It is any without departing from spirit herein and scope, and to it
The equivalent modifications or change of progress, are intended to be limited solely by claims.
Claims (5)
1. a kind of control method for promoting access efficiency on flash memory, wherein the flash memory belongs to multiple field storage flash memory or three layers
Formula stores flash memory, and the flash memory includes control unit, data quick area and multiple memory blocks, which is characterized in that the control
Method processed includes:
Read the number of erasing of each the multiple memory block；
When the number of erasing is more than to erase upper limit threshold, the memory block is converted into single-layer type cell format；And
The data quick area is added in the memory block for being converted into the single-layer type cell format, wherein the data is fast
Taking area is to belong to the single-layer type cell format.
2. control method as described in claim 1, which is characterized in that each the multiple memory block includes that multiple data are deposited
Store up page.
3. control method as described in claim 1, which is characterized in that further include:
Read the error checking correction code that each the multiple data memory page is included；
It, will be described when detecting the position total number that mistake occurs in the error checking correction code and being more than or equal to one and detect wrong threshold value
Memory block is converted to the single-layer type cell format.
4. control method as described in claim 1, which is characterized in that the data quick area by the flash memory extra storage
Space converts.
5. control method as described in claim 1, which is characterized in that the extra memory space is by described control unit pair
It is written and executes data reducti techniques to the data of the flash memory and formed.
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| CN201710411960.0A CN108984109A (en) | 2017-06-05 | 2017-06-05 | The control method of access efficiency is promoted on flash memory |
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| CN201710411960.0A CN108984109A (en) | 2017-06-05 | 2017-06-05 | The control method of access efficiency is promoted on flash memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112486849A (en) * | 2019-09-12 | 2021-03-12 | 慧荣科技股份有限公司 | Flash memory card opening program method, flash memory controller of flash memory device and electronic device |
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