CN108964658A - Clock generating device and its implementation based on phaselocked loop and gauge delay line - Google Patents
Clock generating device and its implementation based on phaselocked loop and gauge delay line Download PDFInfo
- Publication number
- CN108964658A CN108964658A CN201810662683.5A CN201810662683A CN108964658A CN 108964658 A CN108964658 A CN 108964658A CN 201810662683 A CN201810662683 A CN 201810662683A CN 108964658 A CN108964658 A CN 108964658A
- Authority
- CN
- China
- Prior art keywords
- input terminal
- output
- phase
- frequency divider
- output end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Clock generating device and its implementation based on phaselocked loop and gauge delay line, belong to clock technology field, and the present invention is to solve the problems, such as that the prior art is only able to achieve the conversion from frequency to frequency.The UP output end and DN output end of phase frequency detector of the present invention are separately connected the UP input terminal and DN input terminal of charge pump, the current input terminal of the current output terminal connection filter of charge pump, the input terminal of the output end connection voltage controlled oscillator of filter, the clock signal output terminal of voltage controlled oscillator connects the clock signal input terminal of the first frequency divider and the clock signal input terminal of the second frequency divider simultaneously, the FB input terminal of the Q output connection phase frequency detector of first frequency divider, the input terminal of the QN output end connection gauge delay line of first frequency divider, the output end of gauge delay line is connected to the FBN input terminal of phase frequency detector, output of the output of second frequency divider as clock generating device.The present invention is measured for clock.
Description
Technical field
The present invention relates to a kind of clock generating device constructed based on principle of phase lock loop and gauge delay line and its realizations
Method belongs to clock technology field.
Background technique
With the development of the times, the accuracy of metering military, space flight and in terms of more and more important, the essence of metering
Degree needs the support of reference frequency source, and current most popular a reference source is crystal oscillator and atomic clock.
Crystal oscillator is a kind of electronic circuit, it generates mechanical resonance using the piezoelectricity effectiveness of crystalline material, is just obtained
One electrical signal of the frequency.If not taking the measures such as temperature-compensating in crystal oscillator, the frequency stability of crystal oscillator only has 10-5Amount
Grade is added after temperature-compensation circuit, and the frequency stability of crystal oscillator can achieve 10-6~10-8Magnitude, the stabilization of constant-temperature crystal oscillator
Du Genggao can reach 10-8~10-10Magnitude.
The shortcomings that crystal oscillator of high stability is expensive and frequency point is restricted.General high-end constant-temperature crystal oscillator generally requires
Individually debugging, can not produce in batches, so that the price is very expensive.Crystal oscillating circuit is generally around a few frequency standard
Come what is manufactured, such as 10MHz, 10MHz, 33.33MHz and 40MHz.
It is using the quantum leap spectral line between atom and intramolecule energy level as reference, by servo loop by crystal
On the Frequency Locking of oscillator (or laser source) to the jump frequency of the atom or molecule, make crystal oscillator (or
Laser source) frequency have frequency stability identical with atom or molecular transition frequency.The frequency stabilization of general atomic clock
Degree can reach 10-12~10-15Magnitude, newly developed atom light clock frequency stability are 10-16~10-17Magnitude, but atom
Master slave system realizes that difficulty is very big, compared with high stability crystal oscillator cost also than it is expensive many, and volume is big, can not carry, it is general only
Just have at national time service center.
The application circuit of crystal oscillator and atomic clock is as shown in Figure 1, the external frequency source in Fig. 1 is crystal oscillator or atomic clock, Fig. 1
Principle be exactly to pass through negative-feedback, adjust the output clock of voltage controlled oscillator, finally make the output clock signal frequency of frequency divider
Rate is consistent with the clock frequency of external frequency source, this is a conversion from frequency to frequency.
Summary of the invention
The invention aims to solve the problems, such as that the prior art is only able to achieve the conversion from frequency to frequency, one is provided
Clock generating device and its implementation of the kind based on phaselocked loop and gauge delay line.
Clock generating device of the present invention based on phaselocked loop and gauge delay line, the clock generating device include mark
Object staff delay line and phaselocked loop；Phaselocked loop includes phase frequency detector, charge pump, filter, voltage controlled oscillator, the first frequency divider and
Second frequency divider；
The UP output end and DN output end of phase frequency detector are separately connected the UP input terminal and DN input terminal of charge pump, charge
The current output terminal I of pumpoutConnect the current input terminal of filter, the output end V of filterctrlConnect the defeated of voltage controlled oscillator
Enter end, the clock signal output terminal Vout of voltage controlled oscillator connect simultaneously the first frequency divider clock signal input terminal and second point
The clock signal input terminal of frequency device, the FB input terminal of the Q output connection phase frequency detector of the first frequency divider, the first frequency divider
QN output end connects the input terminal of gauge delay line, and the FBN that the output end of gauge delay line is connected to phase frequency detector is defeated
Enter end, output of the output OUT of the second frequency divider as clock generating device.
The implementation method of clock generating device of the present invention based on phaselocked loop and gauge delay line, the clock occur
The detailed process of the implementation method of device are as follows:
Step 1, loop power on, and voltage controlled oscillator is started to work；
Step 2, start-up circuit are by phase frequency detector, the first frequency divider and the second divider reset；
Step 3, the UP output end of phase frequency detector, DN output end, the Q output of the first frequency divider, QN output end, second
The output OUT of frequency divider is 0；
Step 4, power up terminate, enabling signal failure；
Step 5, the first frequency divider divide the output clock signal of voltage controlled oscillator；
Step 6, the first frequency divider Q output connection phase frequency detector FB input terminal, the first frequency divider QN output
The input terminal of end connection gauge delay line, gauge delay line do not change the waveform of QN；
Phase difference between step 7, phase frequency detector detection FB input terminal and FBN input terminal:
When phase of the phase-lead of FB input terminal in FBN input terminal, the UP output end of phase frequency detector exports pulse
Signal, the high level time of pulse signal are the phase-lead of FB input terminal in the phase difference of FBN input terminal, phase frequency detector
DN output end is low level；
When the phase of FB input terminal lags behind the phase of FBN input terminal, the DN output end of phase frequency detector exports pulse
Signal, the high level time of pulse signal are that the phase of FB input terminal lags behind the phase difference of FBN input terminal, phase frequency detector
UP output end is low level；
Step 7, the UP output end of phase frequency detector and DN output end are separately connected UP input terminal and the DN input of charge pump
End:
When UP output end is high level, charge pump charges to filter, and the control voltage of voltage controlled oscillator increases, voltage-controlled
The clock signal frequency of the clock signal output terminal Vout output of oscillator becomes smaller, and the clock cycle is elongated；
When DN output end is high level, to filter discharge, the control voltage of voltage controlled oscillator reduces charge pump, voltage-controlled
The clock signal frequency of the clock signal output terminal Vout output of oscillator becomes larger, and clock signal period shortens；
Complete the negative feedback control of whole loop.
Advantages of the present invention: crystal oscillator and atomic clock are all to find a reference frequency in fact, then by this reference frequency
It extracts as time reference, the benchmark of the clock generating device of the present invention based on phaselocked loop and gauge delay line is
One segment mark object staff delay line completes the conversion from delay to frequency.The present invention is realized from delay information to clock signal
Conversion, benchmark of the delay time of gauge delay line as entire clock generating device, signal are passing through gauge delay line
Afterwards, delayed phase, phase frequency detector detection phase information are simultaneously output to charge pump, and phase information is converted to electricity by charge pump
Current information is converted to information of voltage by stream information, filter, and information of voltage is converted to clock signal by voltage controlled oscillator, frequency dividing
Clock signal is transmitted to gauge delay line again by device, to realize the negative feedback control of whole loop.
The present invention is based on the clock generating device that locking phase principle and gauge delay line construct, principle is different from crystal oscillator and original
Secondary clock, gauge delay line can be made zero-temperature coefficient, therefore can achieve very high stability, and the frequency for exporting clock takes
Certainly in the delay time of gauge delay line, that is, the length of gauge delay line, it is possible to obtain a wide range
Interior any time frequency, circuit of the invention all use CMOS technology, can integrate, and batch production has small in size, weight
Light and at low cost advantage.
Detailed description of the invention
Fig. 1 is crystal oscillator or atomic clock application circuit structure chart；
Fig. 2 is the structural schematic diagram of the clock generating device of the present invention based on phaselocked loop and gauge delay line；
Fig. 3 is the first frequency divider output clock cycle to be less than each signal timing diagram when 10ns；
Fig. 4 is signal timing diagram when the first frequency divider output clock cycle being greater than 10ns；
Fig. 5 is the electrical block diagram of voltage controlled oscillator；
Fig. 6 is the structural schematic diagram of the first frequency divider；
Each signal timing diagram of the frequency divider of prior art when Fig. 7；
Each signal timing diagram of frequency divider when Fig. 8 using Fig. 6.
Specific embodiment
Specific embodiment 1: illustrating present embodiment below with reference to Fig. 2, phaselocked loop and mark are based on described in present embodiment
The clock generating device of object staff delay line, the clock generating device include gauge delay line 1 and phaselocked loop 2；Phaselocked loop 2 includes
Phase frequency detector 201, charge pump 202, filter 203, voltage controlled oscillator 204, the first frequency divider 205 and the second frequency divider 206；
The UP output end and DN output end of phase frequency detector 201 are separately connected UP input terminal and the DN input of charge pump 202
End, the current output terminal I of charge pump 202outConnect the current input terminal of filter 203, the output end V of filter 203ctrlEven
The input terminal of voltage controlled oscillator 204 is connect, the clock signal output terminal Vout of voltage controlled oscillator 204 connects the first frequency divider simultaneously
The clock signal input terminal of 205 clock signal input terminal and the second frequency divider 206, the Q output connection of the first frequency divider 205
The FB input terminal of phase frequency detector 201, the input terminal of the QN output end connection gauge delay line 1 of the first frequency divider 205, standard
The output end of ruler delay line 1 is connected to the FBN input terminal of phase frequency detector 201, the output OUT of the second frequency divider 206 as when
The output of clock generating device.
Specific embodiment 2: illustrating that present embodiment, present embodiment make into one embodiment one below with reference to Fig. 2
Step explanation, which further includes start-up circuit 3；
The reset output terminal of start-up circuit 3 connects the RESET input, the first frequency divider 205 of phase frequency detector 201 simultaneously
The RESET input and the second frequency divider 206 the RESET input.
In present embodiment, the original state of phase frequency detector 201, the first frequency divider 205 and the second frequency divider 206 is very
Important, start-up circuit 3 is for guaranteeing that original state does not malfunction.
Specific embodiment 3: present embodiment is described further embodiment one, the first frequency divider 205 is loop
Interior frequency divider, the Q output and QN output end of the first frequency divider 205 are symmetrical.
In present embodiment, the first frequency divider 205 is as the frequency divider in loop, using two-divider, two-way export Q and
QN will have the symmetry of height, it may be assumed that QN signal is not simply to obtain in the phase inverter that is followed by of Q signal.In this hair
In bright, two-divider is made of eight three input nand gates plus a phase inverter.
Specific embodiment 4: present embodiment is described further embodiment one, the second frequency divider 206 is external
The frequency divider of load.
Specific embodiment 5: illustrating present embodiment below with reference to Fig. 2, phaselocked loop and mark are based on described in present embodiment
The implementation method of the clock generating device of object staff delay line, the detailed process of the implementation method of the clock generating device are as follows:
Step 1, loop power on, and voltage controlled oscillator 204 is started to work；
Step 2, start-up circuit 3 reset phase frequency detector 201, the first frequency divider 205 and the second frequency divider 206；
Step 3, the UP output end of phase frequency detector 201, DN output end, the Q output of the first frequency divider 205, QN output
It holds, the output OUT of the second frequency divider 206 is 0；
Step 4, power up terminate, enabling signal failure；
Step 5, the first frequency divider 205 divide the output clock signal of voltage controlled oscillator 204；
Step 6, the first frequency divider 205 Q output connection phase frequency detector 201 FB input terminal, the first frequency divider 205
QN output end connection gauge delay line 1 input terminal, gauge delay line 1 do not change the waveform of QN；
Step 7, phase frequency detector 201 detect the phase difference between FB input terminal and FBN input terminal:
When phase of the phase-lead of FB input terminal in FBN input terminal, the UP output end of phase frequency detector 201 exports arteries and veins
Signal is rushed, the high level time of pulse signal is the phase-lead of FB input terminal in the phase difference of FBN input terminal, phase frequency detector
201 DN output end is low level；
When the phase of FB input terminal lags behind the phase of FBN input terminal, the DN output end of phase frequency detector 201 exports arteries and veins
Signal is rushed, the high level time of pulse signal is that the phase of FB input terminal lags behind the phase difference of FBN input terminal, phase frequency detector
201 UP output end is low level；
Step 7, the UP output end of phase frequency detector 201 and DN output end be separately connected charge pump 202 UP input terminal and
DN input terminal:
When UP output end is high level, charge pump 202 charges to filter 203, the control voltage of voltage controlled oscillator 204
It increases, the clock signal frequency of the clock signal output terminal Vout output of voltage controlled oscillator 204 becomes smaller, and the clock cycle is elongated；
When DN output end is high level, charge pump 202 discharges to filter 203, the control voltage of voltage controlled oscillator 204
It reduces, the clock signal frequency of the clock signal output terminal Vout output of voltage controlled oscillator 204 becomes larger, and clock signal period becomes
It is short；
Complete the negative feedback control of whole loop.
In present embodiment, the FB input terminal of the Q output connection phase frequency detector 201 of the first frequency divider 205, first point
The input terminal of the QN output end connection gauge delay line 1 of frequency device 205, gauge delay line 1 do not change the waveform of QN, it may be assumed that mark
For the input signal and output signal of object staff delay line 1 other than phase difference, remaining information is identical.
In the present invention, external clock signal is not needed, be connected to 201 two input terminals of phase frequency detector is all feedback letter
Number.
In the present invention, when loop stability, there is no phase difference between the input FB and FBN of phase frequency detector 201, first point
Phase difference between the two-way output Q and QN of frequency device 205 is half period, it is assumed that 1 delay time of gauge delay line is TD, mark
Object staff delay line 1 makes QN postpone TDAfter there is no phase difference between Q, so the delay time T of gauge delay line 1DIt can
To be the first frequency divider 205 output clock cycle (N+0.5) times, N can take the arbitrary integer more than or equal to 0, then just having can
It can cause loop-locking in a wrong frequency, N is bigger, and the period that the first frequency divider 205 exports clock is shorter, then when
Clock frequency is bigger, that is, voltage controlled oscillator output clock frequency is bigger, thus N take it is 0 the most suitable.
Occur the mistake of loop-locking frequency in order to prevent, the output clock frequency of voltage controlled oscillator 204 can be carried out
Limitation, as N=0, gauge postpones the delay time T of 1 lineDIt is 0.5 times of the first frequency divider 205 output clock cycle, that
, the first frequency divider 205 output clock cycle is 2TD, the T of the output clock cycle of voltage controlled oscillator 204D, that is, frequency is
1/TD；As N=1, the delay time T of gauge delay line 1DIt is 1.5 times of the first frequency divider 205 output clock cycle, that
, the first frequency divider 205 output clock cycle is TD/ 1.5, the T of the output clock cycle of voltage controlled oscillator 204D/ 3, that is,
Frequency is 3/TD, when N takes greater value, 204 output clock frequency of voltage controlled oscillator is higher, so only needing voltage controlled oscillator
204 highest output clock frequency is limited in 3/TDUnder, loop would not be locked in the frequency of mistake.
In voltage controlled oscillator 204, a current source 2041 joined, even if control voltage VctrlSo that metal-oxide-semiconductor M1 is turned off,
Voltage controlled oscillator will not stop working.
In the present invention, the frequency for exporting clock signal is 100MHz, and the delay time of gauge delay line 1 is 5ns, is being marked
In object staff delay line 1, the spread speed of signal is the light velocity, so the length of gauge delay line 1 is 1.5m.
As shown in figure 3, QN signal is in the delay by 5ns when the first frequency divider 205 output clock cycle being less than 10ns
Later, phase lags behind Q signal, that is, FB signal phase-lead in FBN, so 201 output signals UP of phase frequency detector
For high level, DN is low level, then charge pump 202 just charges to filter 203, the control voltage of voltage controlled oscillator 204
VctrlIt increases, 204 output clock frequency of voltage controlled oscillator becomes smaller, and the period is elongated；As shown in figure 4, when the first frequency divider 205 exports
When clock cycle is greater than 10ns, QN signal is after the delay by 5ns, and phase-lead is in Q signal, that is, FBN signal
Phase-lead is in FB, so 201 output signal DN of phase frequency detector is high level, UP is low level, then charge pump 202 is just right
Filter 203 discharges, the control voltage V of voltage controlled oscillator 204ctrlIt reducing, 204 output clock frequency of voltage controlled oscillator becomes larger,
Period becomes smaller；When the second frequency divider 206 output clock cycle is 10ns, entire loop completes locking.
In the present invention, the circuit structure of voltage controlled oscillator 204 is as shown in figure 5, control electricity is crimped on M1The grid of pipe, works as control
When voltage change processed, M is flowed through1Electric current also change, M2And M3、M4And M5Two groups of current mirrors are constituted, M is replicated1Electric current,
M6And M7、M8And M9、M10And M11, constitute three groups of phase inverters, M5Electric current to this three groups of phase inverters charging, to be shaken
Sine wave, the size of electric current controls the period of sine wave, and phase inverter 2042 and phase inverter 2043 play shaping, will just
String wave V1Become square wave Vout.When the voltage difference between control voltage and VDD is less than M1When the threshold voltage of pipe, M1Pipe shutdown, adds
The effect for entering current source 2041 is exactly to work as M1When shutdown, voltage controlled oscillator 204 can still export a clock signal.In order to
Prevent loop-locking in the frequency of mistake, to the output clock frequency of voltage controlled oscillator 204 system of being limited in scope, when gauge prolongs
When the slow delay of line 1 is 5ns, when loop-locking, desired 204 output clock frequency of voltage controlled oscillator is 200MHz, and first can
The frequency that mistake can occur is 600MHz, remaining frequency for being likely to occur mistake is all larger than 600MHz, as long as so guaranteeing voltage-controlled
204 maximum output clock frequency of oscillator is less than 600MHz, so that it may avoid the occurrence of mistake.
The structure of first frequency divider 205 is as shown in fig. 6, in order to improve the accuracy of output clock signal, and the two of frequency divider
Road export Q and QN must high degree of symmetry, first frequency divider 205 is by eight three input nand gates (2051 --- 2058) and instead
Phase device 2059 is constituted.
The input of phase inverter 2059 terminates CLK, and output terminates to an input terminal of three input nand gates 2051 and three defeated
Enter an input terminal of NAND gate 2055；
Three input terminals of three input nand gates 2051 meet S, the output end and D of phase inverter 2059 respectively, and output terminates to
One input terminal of three input nand gates 2052；
Three input terminals of three input nand gates 2052 connect R, the output end of three input nand gates 2051 and three inputs respectively
The output end of NAND gate 2056 exports the one of the input terminal and three input nand gates 2056 that are connected to three input nand gates 2053
A input terminal；
Three input terminals of three input nand gates 2053 meet S respectively, and the output end and CLK of three input nand gates 2052 are defeated
An input terminal of three input nand gates 2054 is terminated to out；
Three input terminals of three input nand gates 2054 connect R, the output end of three input nand gates 2053 and three inputs respectively
The output end of NAND gate 2058, output terminate to an input terminal of three input nand gates 2058, and three input nand gates
Output Q of 2054 output end as frequency divider 205；
Three input terminals of three input nand gates 2055 meet DN, the output end and R of phase inverter 2059 respectively, and output terminates to
One input terminal of three input nand gates 2056；
Three input terminals of three input nand gates 2056 connect the output end of three input nand gates 2052 respectively, three inputs with it is non-
The output end and S of door 2055, output terminate to the input of the input terminal and three input nand gates 2057 of three input nand gates 2052
End；
Three input terminals of three input nand gates 2057 meet CLK respectively, and the output end and R of three input nand gates 2056 are defeated
The input terminal of three input nand gates 2058 is terminated to out；
Three input terminals of three input nand gates 2058 connect the output end of three input nand gates 2054 respectively, three inputs with it is non-
The output end and S of door 2057, output terminate to an input terminal of three input nand gates 2054, and three input nand gates 2058
Output QN of the output end as frequency divider 205；
The output Q of first frequency divider 205 is connected to DN, and QN is connected to D；
The input CLK of first frequency divider 205 is connected to the output V of voltage controlled oscillator (4)out；
The input S of first frequency divider 205 is connected to VDD, and R is connected to the output POR of electrification reset module.
It is all to be followed by a phase inverter in Q signal and obtain QN signal, conventional divider for conventional divider
For each signal timing diagram as shown in fig. 7, when CLK signal rising edge 1 arrives, Q signal becomes low level by high level, and Q believes later
Number pass through phase inverter, obtain QN signal, T1For the transmission time of CLK signal to Q signal, T2It is the transmission time of phase inverter, when
When next rising edge 4 of CLK arrives, Q signal becomes high level from low level, and the clock cycle of CLK is T, then rising edge 3
Time difference between rising edge 5 is exactly T-T1-T2+T1, or by taking gauge delay line delay time is 5ns as an example, it is assumed that ring
Road is stable, and the output clock frequency intentionally got at this time is 100MHz, then the output clock frequency of voltage controlled oscillator is
200MHz, that is, period are 5ns, at this time time difference of the QN signal after 5ns delay, between rising edge 3 and rising edge 5
It is exactly (5-T2+ 5) ns is deposited between the input FB and FBN of phase frequency detector at this time because the period of Q and QN is all 10ns
In phase difference, that is to say, that loop is not stable, thus assume it is invalid, then the frequency of obtained output clock is not just
100MHz, but there are a deviations.
For the present invention, this two-way of Q and QN is full symmetric, and timing diagram is as shown in figure 8, when CLK rising edge 1 arrives
When coming, Q signal becomes low level from high level, and QN signal becomes high level, T from low level later1For CLK signal to Q signal
Transmission time, that is, phase inverter 2059, in addition the transmission time of four three input nand gates, T2Be one three input with it is non-
The transmission time of door, when next rising edge 4 of CLK arrives, QN signal first changes, and becomes low level from high level,
Q signal becomes high level from low level later, and the transmission time between rising edge 4 and failing edge 6 is phase inverter 2059, in addition four
The transmission time of a three input nand gate, that is, T1, the transmission time between failing edge 6 and rising edge 5 is one three input
The transmission time of NAND gate, that is, T2, then the time difference between rising edge 3 and rising edge 5 is exactly T-T1-T2+T1+T2, also
It is so that gauge delay line delay time is 5ns as an example, it is assumed that loop is stable, the output clock frequency intentionally got at this time
It is 100MHz, then the output clock frequency of voltage controlled oscillator is 200MHz, that is, the period is 5ns, and QN signal passes through at this time
After 5ns delay, the time difference between rising edge 3 and rising edge 5 is exactly (5+5) ns, because the period of Q and QN is all 10ns,
So phase difference is not present between the input FB and FBN of phase frequency detector at this time, that is to say, that loop is stable, to assume
It sets up, then the frequency of obtained output clock is exactly 100MHz, deviation is not present.
Claims (5)
1. the clock generating device based on phaselocked loop and gauge delay line, which is characterized in that the clock generating device includes mark
Object staff delay line (1) and phaselocked loop (2)；Phaselocked loop (2) includes phase frequency detector (201), charge pump (202), filter
(203), voltage controlled oscillator (204), the first frequency divider (205) and the second frequency divider (206)；
The UP output end and DN output end of phase frequency detector (201) are separately connected UP input terminal and the DN input of charge pump (202)
End, the current output terminal I of charge pump (202)outConnect the current input terminal of filter (203), the output end of filter (203)
VctrlConnect the input terminal of voltage controlled oscillator (204), the clock signal output terminal Vout of voltage controlled oscillator (204) connects the simultaneously
The clock signal input terminal of one frequency divider (205) and the clock signal input terminal of the second frequency divider (206), the first frequency divider
(205) the QN output end of the FB input terminal of Q output connection phase frequency detector (201), the first frequency divider (205) connects standard
The input terminal of ruler delay line (1), the output end of gauge delay line (1) are connected to the FBN input terminal of phase frequency detector (201),
Output of the output OUT of second frequency divider (206) as clock generating device.
2. the clock generating device according to claim 1 based on phaselocked loop and gauge delay line, which is characterized in that should
Clock generating device further includes start-up circuit (3)；
The reset output terminal of start-up circuit (3) connects the RESET input, the first frequency divider of phase frequency detector (201) simultaneously
(205) the RESET input of the RESET input and the second frequency divider (206).
3. the clock generating device according to claim 1 based on phaselocked loop and gauge delay line, which is characterized in that the
One frequency divider (205) is the frequency divider in loop, and the Q output and QN output end of the first frequency divider (205) are symmetrical.
4. the clock generating device according to claim 1 based on phaselocked loop and gauge delay line, which is characterized in that the
Two-divider (206) is the frequency divider of external load.
5. special based on the implementation method of the clock generating device based on phaselocked loop and gauge delay line described in claim 2
Sign is, the detailed process of the implementation method of the clock generating device are as follows:
Step 1, loop power on, and voltage controlled oscillator (204) is started to work；
Step 2, start-up circuit (3) reset phase frequency detector (201), the first frequency divider (205) and the second frequency divider (206)；
Step 3, the UP output end of phase frequency detector (201), DN output end, the Q output of the first frequency divider (205), QN output
It holds, the output OUT of the second frequency divider (206) is 0；
Step 4, power up terminate, enabling signal failure；
Step 5, the first frequency divider (205) divide the output clock signal of voltage controlled oscillator (204)；
Step 6, the first frequency divider (205) Q output connection phase frequency detector (201) FB input terminal, the first frequency divider
(205) input terminal of QN output end connection gauge delay line (1), gauge delay line (1) do not change the waveform of QN；
Phase difference between step 7, phase frequency detector (201) detection FB input terminal and FBN input terminal:
When phase of the phase-lead of FB input terminal in FBN input terminal, the UP output end of phase frequency detector (201) exports pulse
Signal, the high level time of pulse signal are the phase-lead of FB input terminal in the phase difference of FBN input terminal, phase frequency detector
(201) DN output end is low level；
When the phase of FB input terminal lags behind the phase of FBN input terminal, the DN output end of phase frequency detector (201) exports pulse
Signal, the high level time of pulse signal are that the phase of FB input terminal lags behind the phase difference of FBN input terminal, phase frequency detector
(201) UP output end is low level；
Step 7, the UP output end of phase frequency detector (201) and DN output end be separately connected charge pump (202) UP input terminal and
DN input terminal:
When UP output end is high level, charge pump (202) charges to filter (203), the control electricity of voltage controlled oscillator (204)
Pressure increases, and the clock signal frequency of the clock signal output terminal Vout output of voltage controlled oscillator (204) becomes smaller, and the clock cycle becomes
It is long；
When DN output end is high level, charge pump (202) discharges to filter (203), the control electricity of voltage controlled oscillator (204)
Pressure drop is low, and the clock signal frequency of the clock signal output terminal Vout output of voltage controlled oscillator (204) becomes larger, clock signal period
It shortens；
Complete the negative feedback control of whole loop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810662683.5A CN108964658A (en) | 2018-06-25 | 2018-06-25 | Clock generating device and its implementation based on phaselocked loop and gauge delay line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810662683.5A CN108964658A (en) | 2018-06-25 | 2018-06-25 | Clock generating device and its implementation based on phaselocked loop and gauge delay line |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108964658A true CN108964658A (en) | 2018-12-07 |
Family
ID=64486594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810662683.5A Pending CN108964658A (en) | 2018-06-25 | 2018-06-25 | Clock generating device and its implementation based on phaselocked loop and gauge delay line |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108964658A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112858780A (en) * | 2020-12-31 | 2021-05-28 | 广东大普通信技术有限公司 | Method, device and system for measuring crystal oscillation frequency |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1482601A (en) * | 2002-08-02 | 2004-03-17 | 三洋电机株式会社 | Voltage controlled oscillator |
| CN102684688A (en) * | 2011-03-09 | 2012-09-19 | 株式会社东芝 | Voltage controlled oscillator circuit |
| CN104821822A (en) * | 2014-01-31 | 2015-08-05 | 三星显示有限公司 | Circuit for generating clock signal from frontward clock signal, and display device thereof |
| CN106933090A (en) * | 2017-04-12 | 2017-07-07 | 哈尔滨工业大学 | Based on the time timing means that gauge and the permanent principle of light velocity build |
-
2018
- 2018-06-25 CN CN201810662683.5A patent/CN108964658A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1482601A (en) * | 2002-08-02 | 2004-03-17 | 三洋电机株式会社 | Voltage controlled oscillator |
| CN102684688A (en) * | 2011-03-09 | 2012-09-19 | 株式会社东芝 | Voltage controlled oscillator circuit |
| CN104821822A (en) * | 2014-01-31 | 2015-08-05 | 三星显示有限公司 | Circuit for generating clock signal from frontward clock signal, and display device thereof |
| CN106933090A (en) * | 2017-04-12 | 2017-07-07 | 哈尔滨工业大学 | Based on the time timing means that gauge and the permanent principle of light velocity build |
Non-Patent Citations (1)
| Title |
|---|
| 51电子网: "《主从觖发器》", 《51电子网》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112858780A (en) * | 2020-12-31 | 2021-05-28 | 广东大普通信技术有限公司 | Method, device and system for measuring crystal oscillation frequency |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103684438B (en) | Delay phase-locked loop | |
| CN102361456B (en) | Clock phase alignment and adjustment circuit | |
| CN101309079B (en) | Charge pump construction for phase lock loop circuit | |
| CN100501423C (en) | High-frequency clock jitter measuring circuit and calibration method thereof | |
| WO2021068326A1 (en) | Control signal pulse width extraction-based phase-locked acceleration circuit and phase-locked loop system | |
| CN102832930A (en) | Digital phase locked loop system and method | |
| CN102957422A (en) | Digital time delay lock loop circuit | |
| CN110838845B (en) | TDC based on multiphase ring oscillator and ring pulse shrinkage delay chain | |
| CN104113303A (en) | 50% duty ratio clock generation circuit | |
| CN103257569A (en) | Circuit, method and system for time measurement | |
| CN106209038A (en) | Digital pulse width modulator based on IODELAY firmware | |
| CN101409553A (en) | Phase delay line structure | |
| CN104620532A (en) | Clock-generating device and clock data recovery device | |
| CN107528567A (en) | Injection locked oscillator and the semiconductor devices for including it | |
| CN103427798A (en) | Multiphase clock generation circuit | |
| CN103141029A (en) | Sampler circuit | |
| CN103795375B (en) | Dutyfactor adjustment circuit and method thereof | |
| CN110212915B (en) | Coupling type frequency multiplication delay phase-locked loop circuit with uniform split-phase output | |
| CN108964658A (en) | Clock generating device and its implementation based on phaselocked loop and gauge delay line | |
| CN107809240A (en) | Loop filter and phase-locked loop circuit for phase-locked loop circuit | |
| CN104601116B (en) | Frequency multiplier based on delay locked loop structure | |
| CN109150178A (en) | A kind of device and method that no inductance realizes decimal orthogonal frequency division | |
| CN101719767B (en) | Phase-locked loop with quick response | |
| US11275344B2 (en) | Time to digital converter | |
| CN201985842U (en) | Local frequency generation circuit for microwave bandwidth folding receiver |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |