CN108962850B - Array substrate, display device and mask plate - Google Patents
Array substrate, display device and mask plate Download PDFInfo
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- CN108962850B CN108962850B CN201810835808.XA CN201810835808A CN108962850B CN 108962850 B CN108962850 B CN 108962850B CN 201810835808 A CN201810835808 A CN 201810835808A CN 108962850 B CN108962850 B CN 108962850B
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- 239000000758 substrate Substances 0.000 title claims abstract description 112
- 239000000463 material Substances 0.000 claims description 14
- 238000013021 overheating Methods 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 27
- 238000010586 diagram Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000017525 heat dissipation Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 230000032683 aging Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Abstract
The invention provides an array substrate, a display device and a mask plate, relates to the technical field of display, and aims to solve the problem that an insulating layer above a first power line lead is burnt due to the fact that a local overheating phenomenon occurs on the first power line lead. The array substrate comprises a binding area, wherein the binding area is provided with a first power line lead and a signal line lead positioned on one side, far away from a substrate, of the first power line lead, and the binding area is also provided with a heat conduction pattern which is arranged on one side, far away from the substrate, of the first power line lead; an orthographic projection of the signal line lead on the substrate covers a part of an orthographic projection of the first power line lead on the substrate, and an orthographic projection of the heat conductive pattern on the substrate overlaps another part of the orthographic projection of the first power line lead on the substrate.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display device and a mask plate.
Background
An OLED (Organic Light-Emitting Diode) display device has been classified as a next-generation display technology with a development prospect because of its advantages of thinness, lightness, wide viewing angle, active Light emission, continuously adjustable Light emission color, low cost, high color gamut, high contrast, fast response speed, low energy consumption, low driving voltage, wide working temperature range, simple production process, high Light-Emitting efficiency, flexible display, and the like.
In the prior art, the display panel which is prepared preliminarily has the following problems: on one hand, free electrons exist in the display panel, so that the display panel has a plurality of quantum dots; on the other hand, the display panel is fast in early attenuation, so that the display is unstable. Therefore, before the display panel leaves the factory, the Aging treatment needs to be performed on the display panel by inputting larger voltage and current, so that electrons in the display panel are orderly arranged, and the display panel passes through a stage of fast attenuation, so as to improve the yield of products.
However, during the Aging process, a large amount of heat is generated due to a large current transmitted on the first power line lead, and as shown in fig. 1, a part of the first power line lead 20 located in the bonding region is not provided with any metal layer on the side away from the substrate 10, and only some insulating layers (such as the interlayer insulating layer ILD, the planarization layer PLN, and the pixel defining layer PDL in fig. 1) are provided, so that the heat generated by the part of the first power line lead 20 cannot be uniformly dispersed, and a local overheating phenomenon occurs, which causes the insulating layer above the part of the first power line lead 20 to burn, and affects signal transmission.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a display device and a mask plate, which are used for solving the problem that an insulating layer above a first power line lead is burnt due to the fact that a local overheating phenomenon occurs on the first power line lead.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in a first aspect, an array substrate is provided, which includes a bonding region, where the bonding region is provided with a first power line lead and a signal line lead located on a side of the first power line lead away from a substrate, and the bonding region is further provided with a heat-conducting pattern, where the heat-conducting pattern is located on a side of the first power line lead away from the substrate; an orthographic projection of the signal line lead on the substrate covers a part of an orthographic projection of the first power line lead on the substrate, and an orthographic projection of the heat conductive pattern on the substrate overlaps another part of the orthographic projection of the first power line lead on the substrate.
Optionally, an orthographic projection of the heat conducting pattern on the substrate covers at least another part of an orthographic projection of the first power line lead on the substrate.
Optionally, an orthographic projection of the signal line lead on the substrate does not overlap with an orthographic projection of the heat conducting pattern on the substrate.
Optionally, the signal line lead and the heat conducting pattern are made of the same material in the same layer.
Optionally, the array substrate further includes a gate line and a data line; the first power line lead and the gate line are made of the same material in the same layer, and the signal line lead and the heat conducting pattern are made of the same material in the same layer as the data line.
Optionally, the signal line includes a data line lead and a second power line lead.
Optionally, the voltage transmitted on the first power supply lead is a high power supply voltage relative to the voltage transmitted on the second power supply lead.
In a second aspect, a display device is provided, which includes the array substrate of the first aspect.
In a third aspect, a mask plate is provided, where the mask plate is used to prepare the heat conducting pattern in the array substrate of the first aspect.
Optionally, in a case that the signal line lead and the heat conductive pattern in the array substrate are of the same layer and material, the mask plate is used for simultaneously preparing the signal line lead and the heat conductive pattern.
The embodiment of the invention provides an array substrate, a display device and a mask plate. In this way, a large amount of heat generated from the second power line lead due to a large current is dispersed by the good heat dissipation property of the heat conductive pattern, that is, the heat conductive pattern can disperse the heat generated on the second portion of the first power line lead. The phenomenon of local overheating can be avoided, and the problem that the insulating layer above the first power line lead is burnt due to the phenomenon of local overheating on the first power line lead can be solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a bonding region of an array substrate provided in the prior art;
fig. 2 is a region dividing view of an array substrate according to an embodiment of the present invention;
fig. 3 is a first schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 4 is a second schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a bonding region of an array substrate according to an embodiment of the present invention;
fig. 6 is a third schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 7 is a fourth schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a mask plate provided in the prior art;
fig. 9 is a schematic structural diagram of a mask blank according to an embodiment of the present invention.
Reference numerals
01-a display area; 02-non-display area; 03-a binding region; the 04-Pad region; 10-a substrate; 20-a first power line lead; 30-signal line lead; 40-thermally conductive pattern.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 2, the array substrate is divided into a display area 01 and a non-display area 02, the non-display area 02 includes a bonding area 03, and the bonding area 03 includes a Pad area 04. A region for bonding an IC (Integrated Circuit) in the non-display region 02 is referred to as a bonding region 03, and a region of the bonding region 03 where the IC is connected to traces on the array substrate is referred to as a Pad region 04.
As shown in fig. 3, a portion of the first power line lead 20 located in the bonding region 03 is provided with a signal line lead 30 on a side away from the substrate 10, and a portion is not provided with the signal line lead 30, that is, a portion outlined by a dotted line in the drawing, which is a burn area of the first signal line lead 20, the burn area being generally located near an overlapping area of the power line lead for transmitting the VDD signal and the power line lead for transmitting the VSS signal, without burning the overlapping area of the two. Because the insulating layer above the burn area blackens due to local overheating or organic matters in the insulating layer are locally decomposed, bubbles and byproducts appear, and the insulating layer becomes thin or falls off due to local deformation after serious treatment, thereby affecting signal transmission.
To this end, an embodiment of the present invention provides an array substrate, as shown in fig. 4, including a bonding region, where the bonding region is provided with a first power line lead 20 and a signal line lead 30 located on a side of the first power line lead 20 away from a substrate 10, and the bonding region is further provided with a heat conduction pattern 40, where the heat conduction pattern 40 is provided on a side of the first power line lead 20 away from the substrate 10; an orthogonal projection of the signal line lead 30 on the substrate 10 covers a portion of an orthogonal projection of the first power line lead 20 on the substrate 10, and an orthogonal projection of the heat conductive pattern 40 on the substrate 10 overlaps another portion of an orthogonal projection of the first power line lead 20 on the substrate 10.
First, a part of the signal lines in the array substrate are connected to the IC through the signal line leads 30, and the signal line leads 30 are not limited to specific types, but may be disposed on the side of the first power line lead 20 away from the substrate 10, and may not be disposed on the same layer as the first power line lead 20, and the plurality of types of signal line leads 30 may be disposed in different layers.
As shown in fig. 4, the signal line leads 30 and the first power line leads 20 are not in a one-to-one correspondence relationship, and the first power line leads 20 are not disposed below some of the signal line leads 30.
Second, the first power line lead 20 may be divided into two parts, the first part is that the signal line lead 30 is disposed on the side of the first power line lead 20 away from the substrate 10, the second part is that the signal line lead 30 is not disposed on the side of the first power line lead 20 away from the substrate 10, and the heat conductive pattern 40 is disposed on the second part.
The specific shape of the heat conductive pattern 40 is not limited, and it is sufficient that an orthogonal projection of the heat conductive pattern 40 on the substrate 10 overlaps an orthogonal projection of the second portion of the first power line lead 20 on the substrate 10. The overlapping may be that the orthographic projection of the second portion of the first power line lead 20 on the substrate 10 covers the orthographic projection of the heat-conducting pattern 40 on the substrate 10, that the orthographic projection of the heat-conducting pattern 40 on the substrate 10 covers the orthographic projection of the second portion of the first power line lead 20 on the substrate 10, that neither the orthographic projection of the heat-conducting pattern 40 on the substrate 10 nor the orthographic projection of the second portion of the first power line lead 20 on the substrate 10 covers the other, that only a partial area overlaps, or other possible cases. Of course, the relationship between the orthographic projection of the heat conducting pattern 40 on the substrate 10 and the orthographic projection of the first portion of the first power line lead 20 on the substrate 10 is not limited and may be set as appropriate. In either case, as shown in fig. 5, a heat conductive pattern 40 is necessarily provided over the second portion of the first power line lead 20.
Third, the position of the thermal conductive pattern 40 is not limited, and the thermal conductive pattern may be disposed on the same layer as the signal line lead 30, or may be disposed on a different layer from the signal line lead 30, and disposed on the side of the first power line lead 20 away from the substrate 10. It will be understood by those skilled in the art that when the heat conductive pattern 40 is disposed in the same layer as the signal line leads 30, the shape of the heat conductive pattern 40 should avoid making connections between the signal line leads 30, resulting in signal crosstalk between the signal line leads 30.
The material of the thermal conductive pattern 40 is not limited, and may have thermal conductivity, and may be, for example, a metal material.
According to the array substrate provided by the embodiment of the invention, the heat conducting pattern 40 is additionally arranged in the binding region, and the heat conducting pattern 40 is arranged above the second part of the first power line lead 20, so that a large amount of heat generated by the second power line lead due to a large current is dispersed by utilizing the good heat dissipation performance of the heat conducting pattern 40, that is, the heat generated by the second part of the first power line lead 20 can be dispersed by the heat conducting pattern 40. The phenomenon of local overheating can be avoided, and the problem that the insulating layer above the first power line lead 20 is burnt due to the phenomenon of local overheating on the first power line lead 20 can be solved.
In order to ensure a heat dissipation effect over the second portion of the first power supply line lead 20, in some embodiments, as shown in fig. 6, an orthographic projection of the heat conductive pattern 40 on the substrate 10 covers at least another portion of the orthographic projection of the first power supply line lead 20 on the substrate 10.
That is, the orthographic projection of the heat conductive pattern 40 on the substrate 10 covers the second portion of the orthographic projection of the first power supply line lead 20 on the substrate 10.
Here, the heat conductive pattern 40 may cover the entire first power line lead 20, may cover just the second portion of the first power line lead 20, or may cover a portion of the first power line lead 20 in addition to the second portion of the first power line lead 20. Of course, those skilled in the art will appreciate that the provision of the thermally conductive pattern 40 avoids the need for signal crosstalk between the signal wire leads 30.
In order to avoid unnecessary parasitic capacitance between the signal line wire 30 and the heat conductive pattern 40, as shown in fig. 7, in some embodiments, the orthographic projection of the signal line wire 30 on the substrate 10 does not overlap with the orthographic projection of the heat conductive pattern 40 on the substrate 10.
That is, if the signal line lead 30 is present above the first power line lead 20, the thermal conductive pattern 40 is not present, and if the thermal conductive pattern 40 is present, the signal line lead 30 is not present.
Metal is a good heat conductive material, and thus, in order to simplify the manufacturing process, reduce the production cost, and improve the production efficiency, in some embodiments, as shown in fig. 7, the signal line leads 30 and the heat conductive patterns 40 are made of the same material in the same layer.
That is, both the signal line lead 30 and the heat conductive pattern 40 are prepared by the same patterning process, and a new step is not required to be added when the heat conductive pattern 40 is prepared, and only the mask plate is required to be changed when the signal line lead 30 is prepared. In consideration of the layout of the traces, the signal line leads 30 may be directly connected to the heat conductive pattern 40, but may be connected only to the signal line leads 30 for transmitting the same kind of signals, if necessary.
In theory, the signal line lead 30 and the heat-conducting pattern 40 completely cover the first power line lead 20 after being combined, but in the preparation process, when the signal line lead 30 and the heat-conducting pattern 40 are made of the same material in the same layer, in order to avoid signal crosstalk, the signal line lead 30 and the heat-conducting pattern 40 are not arranged in a small part of the area above the first power line lead 20.
In order to simplify the manufacturing process, in some embodiments, the array substrate further includes a gate line and a data line; the first power line lead 20 and the gate line are made of the same material in the same layer, and the signal line lead 30 and the thermal conductive pattern 40 are made of the same material in the same layer as the data line.
That is, when the gate line is prepared, the first power line lead 20 located in the bonding region 03 is simultaneously prepared, or the gate line lead may be simultaneously prepared; when the data line is manufactured, the signal line lead 30 and the heat conductive pattern 40 located in the bonding region 03 are simultaneously manufactured.
To facilitate the layout of the signal line leads 30, in some embodiments, the signal line includes a data line lead and a second power line lead.
The data line lead is electrically connected with the data line, and the second power line lead is electrically connected with the second power line.
In some embodiments, the voltage transmitted on the first power supply lead is a high supply voltage relative to the voltage transmitted on the second power supply lead.
The power supply voltage of the array substrate includes a VDD power supply voltage and a VSS power supply voltage, the first power line lead 20 is electrically connected to the VDD line for transmitting a VDD signal, and the second power line is electrically connected to the VSS line for transmitting a VSS signal.
The embodiment of the invention also provides a display device which comprises the array substrate.
The display device may be a display panel, or a display device including a display panel, for example, an OLED (Organic Light Emitting Diode) display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, a navigator and other products or components having any display function.
When the Display device is a Liquid Crystal Display (LCD), it includes the above array substrate, the opposite box substrate and the Liquid Crystal layer between them. The array substrate may include a TFT (thin film Transistor), a pixel electrode electrically connected to a drain electrode of the TFT; further, a common electrode may be included. The opposite-box substrate can comprise a black matrix and a color film. Here, the color film may be disposed on the box alignment substrate or on the array substrate; the common electrode may be disposed on the array substrate or the pair of cell substrates.
When the display device is an OLED display device, the display device comprises the array substrate and the packaging substrate. The array substrate may include a TFT, an anode electrically connected to a drain electrode of the TFT, a cathode, and an organic material functional layer between the anode and the cathode.
The display device provided by the embodiment of the invention comprises the array substrate, and the beneficial effects of the display device are the same as those of the array substrate, and are not repeated herein.
The embodiment of the invention also provides a mask plate, and the mask plate is used for preparing the heat conducting patterns 40 in the array substrate.
Here, the shape of the opening region of the mask may be the same as the shape of the heat conductive pattern 40, or the shape of the non-opening region of the mask may be the same as the shape of the heat conductive pattern 40. The photoresist used in the preparation of the thermal conductive pattern 40 is different according to the shape of the opening area of the mask.
The mask plate provided by the embodiment of the invention is used for preparing the heat conducting patterns 40 in the array substrate, the prepared array substrate can avoid the problem that the first power line lead 20 is locally overheated, and the yield of products can be improved by adopting the array substrate prepared by the mask plate.
In some embodiments, the signal line leads 30 and the heat conductive patterns 40 in the array substrate are made of the same material in the same layer, and a mask is used to simultaneously prepare the signal line leads 30 and the heat conductive patterns 40.
To explain by way of example that the shape of the opening area of the mask plate is the same as the shape of the pattern to be formed, as shown in fig. 8, the shape of the opening area of the mask plate in the related art is only the same as the shape of the signal line lead 30. The mask plate provided by the embodiment of the invention can simultaneously prepare the signal wire 30 and the heat conducting pattern 40, as shown in fig. 9, the shape of the opening area of the mask plate corresponds to the shapes of the signal wire 30 and the heat conducting pattern 40, and the shapes of the signal wire 30 and the heat conducting pattern 40 in fig. 8 and 9 are only schematic.
That is, the shape of the opening area or the non-opening area of the mask is the same as the shape of the signal line lead 30 and the heat conducting pattern 40 in the array substrate, and the signal line lead 30 and the heat conducting pattern 40 can be simultaneously prepared by using the mask provided by the embodiment of the invention without replacing the mask in a one-time composition process. Therefore, the array substrate prepared by the mask plate provided by the embodiment of the invention can simplify the preparation process.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. An array substrate comprises a binding area, wherein the binding area is provided with a first power line lead and a signal line lead positioned on one side, far away from a substrate, of the first power line lead;
an orthographic projection of the signal line lead on the substrate covers a part of an orthographic projection of the first power line lead on the substrate, and an orthographic projection of the heat conductive pattern on the substrate overlaps another part of the orthographic projection of the first power line lead on the substrate.
2. The array substrate of claim 1, wherein an orthographic projection of the thermal conductive pattern on the substrate covers at least another portion of an orthographic projection of the first power line lead on the substrate.
3. The array substrate of claim 1, wherein an orthographic projection of the signal line lead on the substrate does not overlap with an orthographic projection of the thermal conductive pattern on the substrate.
4. The array substrate of claim 1, wherein the signal line leads and the thermal conductive pattern are of the same layer and material.
5. The array substrate of claim 1, wherein the array substrate further comprises a gate line and a data line;
the first power line lead and the gate line are made of the same material in the same layer, and the signal line lead and the heat conducting pattern are made of the same material in the same layer as the data line.
6. The array substrate of claim 1, wherein the signal lines comprise data line leads and second power line leads.
7. The array substrate of claim 6, wherein a voltage transmitted on the first power supply lead is a high power supply voltage relative to a voltage transmitted on the second power supply lead.
8. A display device comprising the array substrate according to any one of claims 1 to 7.
9. A mask plate, wherein the mask plate is used for preparing a heat conducting pattern in the array substrate according to any one of claims 1 to 7.
10. A mask according to claim 9, wherein in the case where the signal line leads and the heat conductive patterns in the array substrate are of the same layer of the same material, the mask is used to simultaneously prepare the signal line leads and the heat conductive patterns.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810835808.XA CN108962850B (en) | 2018-07-26 | 2018-07-26 | Array substrate, display device and mask plate |
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| CN201810835808.XA CN108962850B (en) | 2018-07-26 | 2018-07-26 | Array substrate, display device and mask plate |
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| CN108962850B true CN108962850B (en) | 2020-06-26 |
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| KR100583138B1 (en) * | 2004-10-08 | 2006-05-23 | 삼성에스디아이 주식회사 | Light Emitting Display |
| CN103578418B (en) * | 2012-07-23 | 2016-08-10 | 乐金显示有限公司 | Display device and the method forming display device |
| KR102086644B1 (en) * | 2013-12-31 | 2020-03-09 | 엘지디스플레이 주식회사 | Flexible display device and manufacturing method thereof |
| JP2017181594A (en) * | 2016-03-28 | 2017-10-05 | パナソニック液晶ディスプレイ株式会社 | Display device |
| KR102592955B1 (en) * | 2016-06-17 | 2023-10-24 | 삼성디스플레이 주식회사 | Display panel, and electronic apparatus including the same |
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