CN108962323B - Sequential control circuit - Google Patents

Sequential control circuit Download PDF

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CN108962323B
CN108962323B CN201710379189.3A CN201710379189A CN108962323B CN 108962323 B CN108962323 B CN 108962323B CN 201710379189 A CN201710379189 A CN 201710379189A CN 108962323 B CN108962323 B CN 108962323B
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transistor
circuit
reference current
inverter
control circuit
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CN108962323A (en
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彭家旭
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

The invention discloses a time sequence control circuit, which comprises a reference current module, a time sequence control module and a time sequence control module, wherein the reference current module is used for outputting a reference current according to an induced external environment, and the reference current changes along with the difference of the external environment; and the time sequence circuit module is used for receiving the reference current and outputting the reference current after generating time sequence change on the received control signal, wherein the time sequence change is the time difference between the receiving and the outputting of the control signal. Because the reference current output by the reference current module in the invention can change along with the difference of external environment, the time sequence circuit module receives the reference current to realize the generation of different time sequences for different time sequence modules, which is beneficial to reducing the time sequence change of the time sequence control circuit, namely reducing the time difference of receiving and outputting the control signal, so as to improve the speed of reading operation of the flash memory product.

Description

Sequential control circuit
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a sequential control circuit.
Background
With the continuous application of Flash (Flash) products, the market has higher and higher requirements on the reading speed of the Flash, and the design adopted by the current timing control circuit of Flash is basically RC (resistance capacitance) charging and discharging or different timing sequences are generated by a given constant current mirror image to a timing module. Due to the fact that the design does not relate to the change of devices in the sequential control circuit under the external environment (different process angles, different temperatures and voltages), the sequential change (timing variation) of the designed sequential control circuit is very large, the reading performance index of the Flash is limited by the maximum value of the sequential change, and the performance of a Flash product is influenced. Therefore, how to reduce the timing variation becomes one of the important issues.
Disclosure of Invention
The present invention provides a timing control circuit capable of reducing timing variation to increase the speed of reading operation of flash memory products.
To solve the above technical problems and related problems, the present invention provides a timing control circuit, including:
the reference current module is used for outputting a reference current according to the sensed external environment, and the reference current changes along with the difference of the external environment;
and the time sequence circuit module is used for receiving the reference current and outputting the reference current after generating time sequence change on the received control signal, wherein the time sequence change is the time difference between the receiving and the outputting of the control signal.
Optionally, the reference current module includes a loop circuit, the loop circuit includes at least a first transistor, a second transistor, and a resistor, one end of the resistor and a source of the first transistor are both grounded, the other end of the resistor and a gate of the first transistor are connected to a source of the second transistor, a gate of the second transistor is connected to a drain of the first transistor, and a drain of the second transistor outputs the reference current.
Optionally, the reference current module further includes a third transistor and a fourth transistor, a drain of the third transistor is connected to a gate of the second transistor, a source of the third transistor is connected to a constant current, a source of the fourth transistor is connected to a power line, and a drain and a gate of the fourth transistor are connected to a drain of the second transistor to output the reference current.
Optionally, the sequential circuit module includes a signal input terminal for receiving the control signal; a signal output terminal for outputting the control signal; a fifth transistor and a sixth transistor for converting the reference current into a charging current; a seventh transistor and an eighth transistor for generating timing variations.
Further, in the timing control circuit, a source of the fifth transistor is connected to a power line, a gate of the fifth transistor is connected to the reference current, a drain of the fifth transistor is connected to a source of the sixth transistor, the gate of the sixth transistor is controlled by the control signal, and the drain of the sixth transistor outputs the charging current; the grid electrode of the seventh transistor and the grid electrode of the eighth transistor are both connected with the charging current, the drain electrode and the source electrode of the seventh transistor are both connected with a ground wire, the drain electrode of the eighth transistor outputs a first control signal, and the source electrode of the eighth transistor is connected with a ground wire.
Optionally, in the timing control circuit, the first transistor, the second transistor, the seventh transistor, and the eighth transistor are all NMOS, and the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all PMOS.
Optionally, in the timing control circuit, the threshold voltages of the first transistor and the eighth transistor are equal.
Optionally, the reference current module further includes a first enable circuit, where the first enable circuit includes a first inverter, and an output terminal of the first inverter is connected to a gate of the third transistor.
Optionally, the reference current module further includes a first non-operating circuit, where the first non-operating circuit includes a ninth transistor and a tenth transistor, a gate of the ninth transistor is equal to an input end of the first inverter, a source of the ninth transistor is connected to the power line, and a drain of the ninth transistor is connected to a gate of the fourth transistor; the grid electrode of the tenth transistor is at the same potential as the output end of the first inverter, the source electrode of the tenth transistor is grounded, and the drain electrode of the tenth transistor is connected with the drain electrode of the first transistor.
Further, in the timing control circuit, the ninth transistor is a PMOS, and the tenth transistor is an NMOS.
Furthermore, the sequential circuit module further includes a second enable circuit, the second enable circuit includes a second inverter, an input end of the second inverter is connected to the control signal, and an output end of the second inverter is connected to the gate of the sixth transistor.
Furthermore, the sequential circuit module further includes a second non-operating circuit, and when the input end of the second inverter is at a low level, the second non-operating circuit is turned on, and the second non-operating circuit has an initialization delay function.
Optionally, the sequential circuit module further includes an initialization delay circuit, where the initialization delay circuit includes an even number of inverters and eleventh transistors connected in series, an input end of the initialization delay circuit is connected to an output end of the second inverter, an output end of the last inverter is connected to a gate of the eleventh transistor, a source of the eleventh transistor is connected to the ground line, and a drain of the eleventh transistor is connected to a drain of the sixth transistor.
Further, in the timing control circuit, the eleventh transistor is an NMOS.
Optionally, the sequential circuit module further includes a third inverter, an input end of the third inverter is connected to the first control signal, and an output end of the third inverter is the signal output end.
Compared with the prior art, the invention has the following beneficial effects:
the time sequence control circuit comprises a reference current module, a time sequence control module and a time sequence control module, wherein the reference current module is used for outputting a reference current according to an induced external environment, and the reference current changes along with the difference of the external environment; and the time sequence circuit module is used for receiving the reference current and outputting the reference current after generating time sequence change on the received control signal, wherein the time sequence change is the time difference between the receiving and the outputting of the control signal. Because the reference current output by the reference current module in the invention can change along with the difference of external environment, the time sequence circuit module receives the reference current to realize the generation of different time sequences for different time sequence modules, which is beneficial to reducing the time sequence change of the time sequence control circuit, namely reducing the time difference of receiving and outputting the control signal, so as to improve the speed of reading operation of the flash memory product.
Furthermore, the reference current module comprises a loop circuit, the loop circuit at least comprises a first transistor, a second transistor and a resistor, one end of the resistor and the source electrode of the first transistor are grounded, the other end of the resistor and the grid electrode of the first transistor are connected with the source electrode of the second transistor, the grid electrode of the second transistor is connected with the drain electrode of the first transistor, and the drain electrode of the second transistor outputs the reference current; the sequential circuit module comprises a seventh transistor and an eighth transistor which are used for generating sequential variation, and the threshold voltages of the eighth transistor and the first transistor are equal. Therefore, the time sequence control circuit can achieve the minimum time sequence change under different external environments (process environments) by only selecting proper resistors, and can further improve the reading performance of the flash memory product by applying the time sequence control circuit to the reading operation of the flash memory product.
Drawings
FIG. 1a is a circuit diagram of a timing control circuit;
FIG. 1b is a timing waveform diagram of the input/output of the timing control circuit shown in FIG. 1 a;
FIG. 1c is simulation data for the timing control circuit shown in FIG. 1 a;
FIG. 2a is a circuit diagram of the timing control circuit according to the embodiment of the present invention;
FIG. 2b is a timing waveform diagram of the input/output of the timing control circuit according to the embodiment of the present invention;
FIG. 2c is a diagram illustrating simulation data of the timing control circuit according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1a, 1b and 1c, fig. 1a is a circuit connection diagram of a timing control circuit, and fig. 1b is a timing waveform diagram of input/output of the timing control circuit shown in fig. 1 a; FIG. 1c is simulation data of the timing control circuit shown in FIG. 1 a. The sequential control circuit comprises two modules: a first reference current module A1 and a first timing circuit module A2, the first reference current module A1 outputting a constant first reference current DelayBias1 through a first constant current InBias1 of an external circuit; the first timing circuit block a2 receives the constant first reference current DelayBias 1.
Specifically, the timing control circuit is shown in fig. 1 a: the first reference current module a1 is composed of a first inverter I11, three PMOS and 2 NMOS, wherein a source of the first PMOS MP11 is connected to a power line VDD, a drain of the first PMOS MP11 is connected to a drain of the first NMOS MN11, a source of the first NMOS MN11 is connected to a first constant current InBias1 of an external circuit, and a drain of the first NMOS MN11 and a gate of the first PMOS MP11 output a first reference current DelayBias 1. In addition, the circuit connection of the other two PMOS and one NMOS in the first reference current module a1 is as follows: the source electrode of the second PMOS MP12 and the source electrode and the drain electrode of the third PMOS MP13 are both connected with a power supply line VDD, the grid electrode of the second PMOS MP12 is equipotential with the input end EN of the first inverter I11, and the drain electrode of the second PMOS MP12 and the grid electrode of the third PMOS MP13 are connected with the grid electrode of the first PMOS MP 11; the gate of the second NMOS MN12 is equipotential with the output ENb of the first inverter I11, the source of the second NMOS MN12 is connected to the ground line VSS, and the drain of the second NMOS MN12 is connected to the gate of the first NMOS MN 11.
Thus, when the input end EN of the first inverter I11 is at a high level (i.e., the first inverter I11 is equivalent to an enable switch), the first PMOS MP11 and the first NMOS MN11 in the first reference current block a1 are in an operating state (i.e., in a conducting state), and a constant first reference current DelayBias1 is output at the connection end between the drain of the first NMOS MN11 and the gate of the first PMOS MP 11. When the input end EN of the first inverter I11 is at a low level, the first reference current module a1 is in a non-operating state, and the second NMOS MN12, the second PMOS MP12, and the third PMOS MP13 in the first reference current module a1 are turned on.
The first timing circuit block a2 comprises a signal input terminal IN1 and a signal output terminal OUT1, wherein the signal input terminal IN1 is used for receiving a control signal, and the signal output terminal OUT1 outputs the control signal (which is an enable signal or a delay signal); the source of the fourth PMOS MP14 in the first timing circuit block a2 is connected to the power line VDD, and the gate of the fourth PMOS MP14 is connected to the constant first reference current DelayBias 1; the input end of the second inverter I12 is a signal input end IN1, the output end of the second inverter I12 is connected with the gate of a fifth PMOS MP15, the source of the fifth PMOS MP15 is connected with the drain of a fourth PMOS MP14, the drain of the fifth PMOS MP15 is connected with the gate of a third NMOS MN13, and the source and the drain of the third NMOS MN13 are both grounded to a line VSS; the control signal is then output through two inverters (one inverter consisting of a sixth PMOS MP16 and a fourth NMOS MN14, and the other inverter I13). Of course, the first timing circuit block a2 further includes a first initialization delay circuit, where the first initialization delay circuit includes an even number of inverters connected in series and a fifth NMOS MN15, for example, includes 4 inverters connected in series (e.g., the fourth inverter I14, the fifth inverter I15, the sixth inverter I16, and the seventh inverter I17 in fig. 1 a), an input end of the first initialization delay circuit is connected to an output end of the second phase I12, an output end of the seventh inverter I17 is connected to a gate of the fifth NMOS MN15, a source ground line of the fifth NMOS MN15, and a drain of the fifth NMOS MN15 is connected to a drain of the fifth PMOS MP 15.
Accordingly, when the control signal received by the input terminal IN1 of the second phase shifter I12 is at a high level, the fourth PMOS MP14, the fifth PMOS MP15 and the third NMOS MN13 start to operate, and the constant first reference current DelayBias1 passes through the fourth PMOS MP14 and the fifth PMOS MP15, so that a charging current is output at the drain of the fifth PMOS MP15, and the charging current charges the third NMOS MN13, so that the timing of the control signal output by the signal output terminal OUT1 exists (i.e., the signal output terminal OUT1 outputs a delay signal). When the control signal received by the input terminal IN1 of the second inverter I12 is at a low level, the first initialization delay circuit and the sixth PMOS MP16 IN the first timing circuit block a2 operate to output a low level signal at the signal output terminal OUT 1.
Then, under certain conditions, the timing control circuit is simulated to obtain the timing waveform diagram of the input (IN 1)/output (OUT1) as shown IN fig. 1b, for example, the first constant current InBias1 provided by the external circuit is 2.5uA, as shown IN fig. 1b, when t is 320ns, a rising edge signal appears IN the control signal of the signal input terminal IN1, i.e., the input signal V is shown IN fig. 1bInFrom 0 to 1.8V, as indicated by the dots (320ns, 0.9V), the signal output terminal OUT1 outputs a signal V around t-323 nsOutFrom 0 to 1.8V, as noted in the figurePoint (323ns, 0.904V). The timing waveform illustrates that there is a delay of about 3ns at the output during this rising edge of the input signal. Further, simulation data of the timing control circuit under different external environments (different Process environments PVT, Process Voltage temperature) is shown in fig. 1c, and the data shows: the time difference (Delay) between the input signal IN1 and the output signal OUT1 of the timing control circuit at five different process corners, such as that the PMOS and the NMOS are respectively at ff (fast fast fast, fast PMOS and fast NMOS), fs (fast slow, slow PMOS and fast NMOS), ss (slow slow PMOS and slow NMOS), or tt (typicalpitch, typicalPMOS and typicalNMOS), at two different voltages (1.62V, 1.98V) and at two different temperatures (105 ℃, -40 ℃) (Case1), the minimum value MIN of the obtained timing variation is 2.82ns, the maximum value MAX of the timing variation is 3.95ns, and the Ratio of the timing variation (MAX/MIN) is 1.4.
The inventors have found that, because the performance of the transistors (PMOS and NMOS) under different process environments (PVT) may have different, for example, the threshold voltage of the transistor under different PVT conditions varies greatly, and therefore, the timing variation of the timing control circuit is large, which affects the read performance of the flash memory product.
Therefore, based on the above research and findings, the present invention provides a timing control circuit, which includes a reference current module, wherein the reference current module is configured to output a reference current according to a sensed external environment, and the reference current varies with the external environment; and the time sequence circuit module is used for receiving the reference current and outputting the reference current after generating time sequence change on the received control signal, wherein the time sequence change is the time difference between the receiving and the outputting of the control signal.
The reference current output by the current reference module of the time sequence control circuit can change along with different external environments, so that the time sequence circuit module can generate different time sequences for different time sequence modules by receiving the reference current, and the time sequence control circuit is favorable for reducing the time sequence change of the time sequence control circuit, namely reducing the time difference of receiving and outputting the control signal so as to improve the reading operation speed of a flash memory product.
The timing control circuit of the present invention will now be described in more detail with reference to the flow charts and schematic diagrams, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art can modify the invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The following embodiments of the timing control circuit are presented for clarity of illustration of the present invention, and it should be understood that the present invention is not limited to the following embodiments, and other modifications by conventional means of ordinary skill in the art are within the scope of the idea of the present invention.
Referring to fig. 2a, fig. 2a shows a circuit connection diagram of the timing control circuit according to the embodiment of the invention, the timing control circuit includes two major modules, a reference current module B1 and a timing circuit module B2, the reference current module B1 is configured to output a reference current DelayBias2 according to the sensed external environment, and the reference current DelayBias2 varies with the external environment; the sequential circuit module B2 receives the reference current DelayBias2, and outputs a sequential change of the received control signal, where the sequential change is a time difference between receiving and outputting the control signal.
Specifically, the reference block B1 includes a loop circuit, which includes at least a first transistor, a second transistor and a resistor, and preferably, the reference current block B1 further includes a third transistor and a fourth transistor. As shown in fig. 2a, preferably, the first transistor and the second transistor are both NMOS, the first transistor is a first NMOS MN21, and the second transistor is a second NMOS MN 22; the third transistor and the fourth transistor are both PMOS, the third transistor is a first PMOS MP21, and the fourth transistor is a second PMOS MP 22. One end of the resistor R0 and a source electrode of the first NMOS MN21 are both grounded to a ground line VSS, the other end of the resistor R0 and a gate electrode of the first NMOS MN21 are connected with a source electrode of the second NMOS MN22, a drain electrode of the first PMOS MP21 and a gate electrode of the second NMOS MN22 are connected with a drain electrode of the first NMOS MN21, a source electrode of the first PMOS MP21 is connected with a constant current InBias2, and the constant current InBias2 can be provided by an external circuit; the source of the second PMOS MP22 is connected to a power line VDD, and the drain of the second PMOS MP22 is connected to the drain of the second NMOS MN22 to output the reference current DelayBias 2.
Obviously, the reference current module B1 further includes a first enable circuit including a first inverter I21, an output end ENb of the first inverter I21 being connected to a gate of the first PMOS MP 21. In order to further optimize the circuit structure of the reference current module B1, the reference current module B1 further includes a first inactive circuit, for example, the reference current module B1 further includes a third PMOS MP23 (i.e., a ninth transistor), a gate of the third PMOS MP23 is equipotential with the input end EN of the first inverter I21, a source of the third PMOS MP23 is also connected to the power line VDD, and a drain of the third PMOS MP23 is connected to the gate of the second PMOS MP 22; the reference current module B1 further includes a third NMOS MN23 and a fourth NMOS MN24 (i.e., a tenth transistor), the source and the drain of the third NMOS MN23 and the source of the fourth NMOS MN24 are both connected to the ground line VSS, the gate of the third NMOS MN23 and the drain of the fourth NMOS MN24 are both connected to the drain of the first NMOS MN21, and the gate of the fourth NMOS MN24 is equipotential to the output end ENb of the first inverter I21.
Therefore, when the input end EN of the first inverter I21 is at a high level, the reference current block B1 is in an operating state (i.e., the first PMOS MP21, the first NMOS MN21, the second NMOS MN22, and the second PMOS MP22 are turned on), and the voltage V across the resistor R0 is then detectedRApproximately equal to the threshold voltage of the first NMOS MN21VT1, therefore, the reference current DelayBias2 outputted by the reference block B1 is equal to VT1 divided by R (R is the resistance of the resistor R0), and the reference current DelayBias2 varies with the first NMOS MN21 under different PVT conditions (i.e., according to the sensed external environment) (i.e., the reference current DelayBias2 outputted by the reference current block B1 is different), which is beneficial to reducing the timing variation of the timing variable control circuit.
Further, a sequential circuit block B2 IN the sequential control circuit includes a signal input terminal IN for receiving a control signal and a signal output terminal OUT for outputting the control signal (which is an enable signal or a delay signal); the sequential circuit block B2 further includes a fifth transistor and a sixth transistor for converting the reference current DelayBias2 into a charging current; a seventh transistor and an eighth transistor for generating timing variation. In this embodiment, the fifth transistor and the sixth transistor of the sequential circuit module B2 are both PMOS, the fifth transistor is a fourth PMOS MP24, and the sixth transistor is a fifth PMOS MP 25; the seventh transistor and the eighth transistor of the sequential circuit module B2 are both NMOS, the seventh transistor is a fifth NMOS MN25, and the eighth transistor is a sixth NMOS MN 26. The source of the fourth PMOS MP24 is connected to the power line VDD, and the gate of the fourth PMOS MP24 is connected to the reference current DelayBias 2; the source of the fifth PMOS MP25 is connected to the drain of the fourth PMOS MP24, and the drain of the fifth PMOS MP25 outputs the charging current; the gate of the fifth NMOS MN25 and the gate of the sixth NMOS MN26 are both connected to the charging current, the source and the drain of the fifth NMOS MN25 are both grounded to VSS, the drain of the sixth NMOS MN26 outputs a first control signal, the source of the sixth NMOS MN26 is grounded to VSS, wherein the sixth PMOS MP26 and the sixth NMOS MN26 form an inverter, and the control signal is output through a third inverter I23.
Obviously, the sequential circuit module further includes a second enable circuit, the second enable circuit includes a second inverter I22, an input terminal IN of the second inverter I22 is connected to the control signal, and an output terminal of the second inverter I22 is connected to the gate of the fifth PMOS MP 25. In addition, the timing circuit module B2 further includes an initialization delay circuit, the initialization delay circuit includes an even number of inverters connected in series and an eleventh transistor, in this embodiment, the initialization delay circuit includes 4 inverters connected in series (e.g., the fourth inverter I24, the fifth inverter I25, the sixth inverter I26, and the seventh inverter I27 in fig. 2 a), the eleventh transistor is a seventh NMOS MN27, an input terminal of the initialization delay circuit is connected to an output terminal of the second inverter I22, an output terminal of the last inverter (i.e., the seventh inverter) I27 of the 4 inverters connected in series is connected to a gate of the seventh NMOS MN27, a source ground line VSS of the seventh NMOS MN27, and a drain of the seventh NMOS MN27 is connected to a drain of the fifth PMOS MP 25.
Accordingly, when the control signal received by the input terminal IN of the second inverter I22 is at a high level, the fourth PMOS MP24, the fifth PMOS MP25 and the fifth NMOS MN25 operate, the drain of the fifth PMOS MP25 outputs the charging current to charge the fifth NMOS MN25, and when the gate of the fifth NMOS MN25 reaches the threshold voltage VT2 of the sixth NMOS MN26, the first control signal output by the drain of the sixth NMOS MN26 is flipped from "1" to "0", and then the control signal (delay signal) is output through the third inverter I23. When the control signal received at the input terminal IN of the second inverter I22 is at a low level, the initialization delay circuit and the sixth PMOS MP26 IN the sequential circuit block B2 operate (corresponding to a second non-operating state circuit), and a low level signal is output at the signal output terminal OUT.
The circuit connection condition of the timing control circuit described in this embodiment is theoretically analyzed as above, when the input signal V is inputInRising edge to output signal VOutThe timing variation ∑ T produced by the rising edge is primarily:
v T ═ R ═ C VT2/VT1, wherein: c is the capacitance of the gate terminal of the fifth NMOS MN25, so in the timing control circuit of the present embodiment, it is only necessary to design VT1 equal to VT2 (i.e., match the first NMOS MN21 and the sixth NMOS MN 26), and the timing variation ∑ T expression can be simplified to ∑ T ═ R C, because the temperature coefficient variation of the resistance R of the resistor R0 is relatively small (compared to the threshold voltage of the transistor), therefore, in the timing control circuit of the present embodiment, it is only necessary to select the appropriate type of resistor R0, and the minimum timing variation can be designed under different PVT conditions.
Referring to fig. 2b and fig. 2c, fig. 2b is a waveform diagram of input/output of the timing control circuit in this embodiment obtained by simulation under certain conditions, for example, the constant current InBias2 provided by the external circuit is 1.0uA, as shown in fig. 2b, when t is 920ns, a rising edge signal appears in the control signal, i.e., the input signal V is VInFrom 0 to 1.8V, as indicated by the point (920ns, 0.9V), the output terminal OUT outputs a signal V around t 923nsOutFrom 0 to 1.8V, as indicated by the dots (923ns, 0.905V). Further, the timing control circuit of this embodiment is simulated under the same PVT condition (Case2) as Case1, and the obtained simulation data shows that the minimum value MIN of the obtained timing variation is 3.16ns, the maximum value MAX of the timing variation is 3.70ns, and the Ratio (MAX/MIN) of the timing variation is 1.17, as shown in fig. 2 c.
Therefore, by the timing control circuit of the embodiment, only by matching the first NMOS MN21 and the sixth NMOS MN26 with each other (the threshold voltage of the first NMOS MN21 is equal to the threshold voltage of the sixth NMOS MN 26), the influence of the threshold voltage of the transistor on the timing control circuit can be eliminated, the timing variation can be effectively improved, the Ratio (MAX/MIN) of the timing variation is reduced from 1.4 to 1.17, the reading speed of the flash memory product is improved by 16.4%.
In summary, the present invention provides a timing control circuit, which includes a reference current module, wherein the reference current module is configured to output a reference current according to an external environment sensed by the reference current module, and the reference current varies with the external environment; and the time sequence circuit module is used for receiving the reference current and outputting the reference current after generating time sequence change on the received control signal, wherein the time sequence change is the time difference between the receiving and the outputting of the control signal.
Furthermore, the reference current module comprises a loop circuit, the loop circuit at least comprises a first transistor, a second transistor and a resistor, one end of the resistor and the source electrode of the first transistor are grounded, the other end of the resistor and the grid electrode of the first transistor are connected with the source electrode of the second transistor, the grid electrode of the second transistor is connected with the drain electrode of the first transistor, and the drain electrode of the second transistor outputs the reference current; and the sequential circuit module comprises a seventh transistor and an eighth transistor for generating sequential variation, and the threshold voltages of the eighth transistor and the first transistor are equal. Therefore, the time sequence control circuit can achieve the minimum time sequence change under different process environments only by selecting a proper resistor, and can further improve the reading performance of the flash memory product when being applied to the reading operation of the flash memory product.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (14)

1. A timing control circuit, comprising:
the reference current module is used for outputting a reference current according to the sensed external environment, the reference current changes along with the difference of the external environment, the reference current module comprises a loop circuit, the loop circuit at least comprises a first transistor, a second transistor and a resistor, one end of the resistor and the source electrode of the first transistor are both grounded, the other end of the resistor and the grid electrode of the first transistor are connected with the source electrode of the second transistor, the grid electrode of the second transistor is connected with the drain electrode of the first transistor, and the drain electrode of the second transistor outputs the reference current;
the time sequence circuit module is used for receiving the reference current and outputting the reference current after generating reduced time sequence change to the received control signal, the time sequence change is time difference of receiving and outputting the control signal, the time sequence circuit module comprises a seventh transistor and an eighth transistor, the seventh transistor and the eighth transistor are used for generating time sequence change, a grid electrode of the seventh transistor and a grid electrode of the eighth transistor are both connected with the charging current formed after the reference current is converted, a drain electrode and a source electrode of the seventh transistor are both connected with a ground wire, a drain electrode of the eighth transistor outputs the first control signal, and a source electrode of the eighth transistor is connected with a ground wire.
2. The timing control circuit according to claim 1, wherein the reference current module further includes a third transistor and a fourth transistor, a drain of the third transistor is connected to a gate of the second transistor, a source of the third transistor is connected to a constant current, a source of the fourth transistor is connected to a power line, and a drain and a gate of the fourth transistor are connected to a drain of the second transistor to output the reference current.
3. The timing control circuit of claim 2, wherein the timing circuit module includes a signal input to receive the control signal; a signal output terminal for outputting the control signal; a fifth transistor and a sixth transistor for converting the reference current into a charging current.
4. The timing control circuit according to claim 3, wherein a source of the fifth transistor is connected to a power line, a gate of the fifth transistor is connected to the reference current, a drain of the fifth transistor is connected to a source of the sixth transistor, a gate of the sixth transistor is controlled by the control signal, and a drain of the sixth transistor outputs the charging current.
5. The timing control circuit of claim 4, wherein the first transistor, the second transistor, the seventh transistor, and the eighth transistor are all NMOS, and the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all PMOS.
6. The timing control circuit of claim 5, wherein threshold voltages of the first transistor and eighth transistor are equal.
7. The timing control circuit according to any of claims 2 to 6, wherein the reference current module further comprises a first enable circuit, the first enable circuit comprises a first inverter, and an output terminal of the first inverter is connected to a gate of the third transistor.
8. The timing control circuit of claim 7, wherein the reference current block further comprises a first inactive circuit comprising a ninth transistor and a tenth transistor, wherein the gate of the ninth transistor is at the same potential as the input terminal of the first inverter, the source of the ninth transistor is connected to the power line, and the drain of the ninth transistor is connected to the gate of the fourth transistor; the grid electrode of the tenth transistor is at the same potential as the output end of the first inverter, the source electrode of the tenth transistor is grounded, and the drain electrode of the tenth transistor is connected with the drain electrode of the first transistor.
9. The timing control circuit of claim 8, wherein the ninth transistor is PMOS and the tenth transistor is NMOS.
10. The timing control circuit according to any one of claims 3 to 6, wherein the timing circuit module further comprises a second enable circuit, the second enable circuit comprises a second inverter, an input end of the second inverter is connected to the control signal, and an output end of the second inverter is connected to the gate of the sixth transistor.
11. The timing control circuit of claim 10, wherein the timing circuit block further comprises a second inactive circuit, the second inactive circuit turning on when the input of the second inverter is low, the second inactive circuit having an initialization delay function.
12. The timing control circuit of claim 11, wherein the timing circuit block further comprises an initialization delay circuit, the initialization delay circuit comprises an even number of inverters and eleventh transistors connected in series, an input terminal of the initialization delay circuit is connected to an output terminal of the second inverter, an output terminal of the last one of the inverters is connected to a gate of the eleventh transistor, a source of the eleventh transistor is connected to the ground, and a drain of the eleventh transistor is connected to a drain of the sixth transistor.
13. The timing control circuit of claim 12, wherein the eleventh transistor is an NMOS.
14. The timing control circuit according to any of claims 4 to 6, wherein the timing circuit module further comprises a third inverter, an input terminal of the third inverter is connected to the first control signal, and an output terminal of the third inverter is the signal output terminal.
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