CN108933722B - Vlan frame processing method, device and server - Google Patents
Vlan frame processing method, device and server Download PDFInfo
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- CN108933722B CN108933722B CN201710395344.0A CN201710395344A CN108933722B CN 108933722 B CN108933722 B CN 108933722B CN 201710395344 A CN201710395344 A CN 201710395344A CN 108933722 B CN108933722 B CN 108933722B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/46—Interconnection of networks
- H04L12/4641—Virtual LANs, VLANs, e.g. virtual private networks [VPN]
- H04L12/4645—Details on frame tagging
- H04L12/4666—Operational details on the addition or the stripping of a tag in a frame, e.g. at a provider edge node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/46—Interconnection of networks
- H04L12/4641—Virtual LANs, VLANs, e.g. virtual private networks [VPN]
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Abstract
The invention provides a Vlan frame processing method, a device and a server, wherein n +1 register units which are sequentially connected are arranged for a Vlan frame which comprises a Vlan tag and has a Vlan tag length of n bytes, the Vlan frame is analyzed after being acquired, data obtained by analysis are sequentially written into a register unit 0 by taking 1 byte as a step length and 1 clock as a writing period, and data in a previous register unit is written into a next register unit in each clock period; when data is written into the register unit n, judging whether the data in the register unit n is Vlan tag data or not, and if not, reading the data from the register unit n; otherwise, reading data from the register unit 0 in each subsequent clock cycle, and stopping writing the data in the previous register unit into the next register unit, the invention can effectively strip the Vlan tag data in the Vlan frame by using n +1 register units, FIFO logic resources are not needed, the read-write control is relatively simpler, and the hardware and control maintenance cost can be reduced.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a Virtual Local Area Network (Vlan) frame processing method, a Vlan frame processing device, and a Vlan frame processing server.
Background
When the method is applied to the communication field, in some communication scenarios, the Vlan tag (virtual local area network tag) is carried in the Vlan frame, so that the Vlan tag in the Vlan frame is stripped, and data without the Vlan tag is output. In this case, since the output data is less in bytes of the vlan tag data than the input data, it is necessary to devise a Field-Programmable Gate Array (FPGA) so as not to affect the continuity of the output data when the vlan tag is peeled off.
For example, when the length of the Vlan tag data in the Vlan frame is 4 bytes. The current processing method is to add a FIFO (First Input First output) queue, write the Input Vlan frame into a FIFO that buffers 1 byte bit width, when encountering Vlan tag byte data, stop writing into the buffer FIFO within the 4 clocks, and then continue writing data after Vlan tag into the buffer FIFO, so that the message data written in the buffer FIFO is the message data from which Vlan tag has been stripped. The read control logic of the buffer FIFO always determines the depth of the data stored in the FIFO and can start reading when the data stored in the FIFO exceeds 4 bytes, because the amount of data buffered in the FIFO ensures that the output data will be continuous even if the data in the FIFO is not written in 4 clocks because of the stripping of vlan tag. When the read control logic reads an end-of-packet tag from the buffer FIFO, it stops immediately. The stored data in the FIFO is again waited for more than 4 bytes. Referring to fig. 1, the process includes:
s101: and acquiring a Vlan frame for analysis.
S102: the parsed data is continuously written into the FIFO in a unit length of 1 byte.
S103: judging whether the data to be written into the FIFO currently is vlan tag data or not, if so, turning to S104; otherwise, go to S105.
S104: the writing into the FIFO is suspended for 4 clock cycles and then goes to S105.
S105: data is continuously written to the FIFO.
S106: the continuous read-out starts after the amount of data in the FIFO is greater than 4 bytes.
Through the process, the read data can be ensured to be the message data stripped from the vlan tag. For example, assume the Vlan frame input data is: 0x 010 x 020 x 030 x 040 x 050 x 810 x 000 x0a 0xbc 0x 060 x07, wherein the vlan tag data requiring peeling is: 0x 810 x 000 x0a 0xbc, see fig. 2, where the symbol ↓ in fig. 2 denotes writing to or reading from the FIFO, and the symbol-denotes suspending reading from the FIFO. As can be seen from fig. 2, the output data was 0x 010 x 020 x 030 x 040 x 050 x 060 x07, and vlan tag data 0x 810 x 000 x0a 0xbc was effectively peeled off.
Although the current processing method can strip off the Vlan tag in the Vlan frame, a cache FIFO queue is required, so that the use of logic resources is increased, the cost is high, the read-write control of the cache FIFO is complex, and the difficulty in debugging and maintenance is increased.
Disclosure of Invention
The Vlan frame processing method, the Vlan frame processing device and the Vlan frame processing server mainly solve the technical problems that the cost is high and the control is complex due to the fact that Vlan tag stripping in a Vlan frame is conducted through an FIFO cache queue in the prior art.
To solve the foregoing technical problem, an embodiment of the present invention provides a Vlan frame processing method, including:
acquiring a Vlan frame containing a Vlan tag, wherein the length of the Vlan tag is n bytes;
analyzing the Vlan frame, sequentially writing the analyzed data into a register unit 0 by taking 1 byte as a step length and 1 clock as a writing period, wherein the register unit 0 is sequentially connected with the register units 1 and … and register units i and …, and in the writing process, the method further comprises the step of writing the data in the previous register unit into the next register unit in each clock period;
when data is written into the register unit n, judging whether the data in the register unit n is Vlan tag data or not in each clock cycle, if not, reading the data from the register unit n, and continuously writing the data in the previous register unit into the next register unit in each clock cycle; otherwise, reading data from the register unit 0 in each subsequent clock cycle, and stopping writing the data in the previous register unit into the next register unit.
In order to solve the above problem, the present invention further provides a Vlan frame processing apparatus, including an analysis unit, a reading unit, and a register unit 0, a register unit 1, …, a register unit i, and a register unit n …, which are connected in sequence;
the analysis unit is used for analyzing the Vlan frame containing the Vlan tag, sequentially writing the analyzed data into the register unit 0 by taking 1 byte as a step length and 1 clock as a writing period, and writing the data in the previous register unit into the next register unit in each clock period;
the reading unit is used for judging whether the data in the register unit n is Vlan tag data or not in each clock cycle when the data is written in the register unit n, if not, reading the data from the register unit n, and continuously informing the analysis unit to write the data in the previous register unit into the next register unit in each clock cycle; otherwise, reading data from the register unit 0 in each subsequent clock cycle, and informing the parsing unit to stop writing the data in the previous register unit into the next register unit in each subsequent clock cycle.
In order to solve the above problem, the present invention further provides a server including the Vlan frame processing apparatus as set forth in the above.
In order to solve the above problem, the present invention also provides a storage medium storing a program, and the stored program executes the Vlan frame processing method as described above when called.
The invention has the beneficial effects that:
according to the Vlan frame processing method, device and server provided by the embodiments of the present invention, for a Vlan frame including Vlan tag and having a Vlan tag length of n bytes, a register unit 0, register units 1 and …, and register units i and … are sequentially connected, and after the Vlan frame including the Vlan tag is acquired, the Vlan frame is analyzed, data obtained by the analysis is sequentially written into the register unit 0 with 1 byte as a step length and 1 clock as a write cycle, and data in a previous register unit is written into a subsequent register unit in each clock cycle; when data is written into the register unit n, judging whether the data in the register unit n is Vlan tag data or not, if not, reading the data from the register unit n, and continuously writing the data in the previous register unit into the next register unit; otherwise, reading data from the register unit 0 in each subsequent clock cycle, and stopping writing the data in the previous register unit into the next register unit, the invention can effectively strip the Vlan tag data in the Vlan frame by using n +1 register units, FIFO logic resources are not needed, the read-write control is relatively simpler, and the hardware and control maintenance cost can be reduced.
Drawings
FIG. 1 is a schematic diagram illustrating a conventional flow for implementing vlan tag data stripping using FIFO;
FIG. 2 is a diagram illustrating the result of the prior art VLAN tag data stripping using FIFO;
fig. 3 is a schematic flow chart of a Vlan frame processing method according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a Vlan frame processing apparatus according to a second embodiment of the present invention;
fig. 5 is a schematic diagram of a Vlan frame structure according to a third embodiment of the present invention;
fig. 6 is a schematic flow chart of a Vlan frame processing method according to a third embodiment of the present invention;
fig. 7 is a schematic diagram illustrating the result of performing vlan tag data stripping by using a register according to a third embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The first embodiment is as follows:
in the Vlan frame processing method provided in this embodiment, for a Vlan frame including Vlan tag and having a Vlan tag length of n bytes, register unit 0, register units 1 and …, and register unit i and register unit n of … are sequentially connected. Then after a Vlan frame containing a Vlan tag is acquired, analyzing the Vlan frame, sequentially writing the analyzed data into a register unit 0 by taking 1 byte as a step length and 1 clock as a write cycle, and writing the data in the previous register unit into the next register unit in each clock cycle; when data is written into the register unit n, judging whether the data in the register unit n is Vlan tag data or not, if not, reading the data from the register unit n, and continuously writing the data in the previous register unit into the next register unit; otherwise, reading data from the register unit 0 in each subsequent clock cycle, and stopping writing the data in the previous register unit into the next register unit, the invention can effectively strip the Vlan tag data in the Vlan frame by using n +1 register units, FIFO logic resources are not needed, the read-write control is relatively simpler, and the hardware and control maintenance cost can be reduced.
It should be understood that the specific length of the Vlan tag may be different according to different application scenarios and different protocol specifications, and the specific structure of the Vlan frame in this embodiment may also be flexibly set according to the specific application scenarios and different protocol specifications. Based on the foregoing solution provided in this embodiment, the Vlan frame processing method provided in this embodiment, as shown in fig. 3, includes:
s301: a Vlan frame is obtained that contains a Vlan tag that is n bytes in length.
S302: and analyzing the obtained Vlan frame, sequentially writing the analyzed data into the register unit 0 by taking 1 byte as a step length and 1 clock as a writing period, and writing the data in the previous register unit into the next register unit in each clock period.
S303: when data is written in the register unit n, judging whether the data in the register unit n is Vlan tag data or not in each clock cycle, if not, going to S304; otherwise, go to S305.
S304: reading data from the register unit n and continuing to write data in the previous register unit into the next register unit in each clock cycle, and then going to S303.
S305: and reading data from the register unit 0 in each subsequent clock cycle, and stopping writing the data in the previous register unit into the next register unit until the data reading of the Vlan frame is completed. At this time, the data in register cells 1 and … and register cells i and … and register cell n remains unchanged until the data in the Vlan frame is completely read, and particularly, the data in register cell n remains Vlan tag data, so that it is possible to determine whether or not the data in register cell n is Vlan tag data in the subsequent clock cycle, and it is needless to say that the determination may be made, but the determination results are Vlan tag data.
According to the scheme provided by the embodiment, the storage size of the register unit 0, …, register unit i, …, register unit n is theoretically only required to be larger than or equal to 1 byte, and in order to control the cost as much as possible, the storage size of each register unit 0, …, register unit i, …, register unit n can be set to 1 byte.
Generally, the length of the Vlan tag data in the Vlan frame and its numerical content may be substantially predetermined, for example, the length of the Vlan tag data may be 4 bytes, for example, 0x 810 x 000 x0a 0xbc in one example.
In an example of the present embodiment, the determining in S303 whether the data in the register unit n is Vlan tag data includes:
comparing the data in the register unit n with the nth byte data in the Vlan tag, and determining that the data in the register unit n is Vlan tag data when the data in the register unit n is consistent with the nth byte data in the Vlan tag;
or comparing the data in the register unit n with the byte data in the Vlan tag, and determining that the data in the register unit n is Vlan tag data when the data in the register unit n is judged to be consistent with the byte data in the Vlan tag.
In this embodiment, after the data obtained by analyzing the Vlan frame is written, the method further includes performing zero clearing processing on the data in the register units 1 and … and the register units i and … to prepare for processing the next Vlan frame.
In this embodiment, the Vlan tag data with the byte length n in the Vlan frame can be effectively stripped by using n +1 register units, FIFO logic resources are not needed, read-write control is relatively simpler, and hardware and control maintenance costs can be reduced.
Example two:
the present embodiment provides a Vlan frame processing apparatus in which a register unit 0, a register unit 1, …, a register unit i, and a register unit …, which are connected in this order, are provided for a Vlan frame including Vlan tag and having a Vlan tag length of n bytes. Then after a Vlan frame containing a Vlan tag is acquired, analyzing the Vlan frame, sequentially writing the analyzed data into a register unit 0 by taking 1 byte as a step length and 1 clock as a write cycle, and writing the data in the previous register unit into the next register unit in each clock cycle; when data is written into the register unit n, judging whether the data in the register unit n is Vlan tag data or not, if not, reading the data from the register unit n, and continuously writing the data in the previous register unit into the next register unit; otherwise, data is read from register unit 0 every subsequent clock cycle, and writing of data in the previous register unit to the subsequent register unit is stopped, so that the read data does not include vlan tag data.
Referring to fig. 4, the Vlan frame processing apparatus provided in this embodiment includes an analyzing unit 41, a reading unit 42, and a register unit 0, a register unit 1, an register unit …, a register unit i, and a register unit n …, which are connected in sequence;
the parsing unit 41 is configured to parse a Vlan frame including a Vlan tag, sequentially write parsed data into the register unit 0 in 1 byte as a step length and 1 clock as a write cycle, and write data in a previous register unit into a subsequent register unit in each clock cycle. The specific duration of the clock in this embodiment can be flexibly set according to a specific application scenario.
The reading unit 42 is configured to, when data is written in the register unit n, determine, every clock cycle, whether the data in the register unit n is Vlan tag data, if not, read the data from the register unit n, and continuously notify the analyzing unit 41 to write the data in the previous register unit into the next register unit in every clock cycle; otherwise, data is read from register unit 0 at each subsequent clock cycle, and parsing unit 41 is notified to stop writing data in the previous register unit into the next register unit at each subsequent clock cycle. . At this time, the data in register cells 1 and … and register cells i and … and register cell n remains unchanged until the data in the Vlan frame is completely read, and particularly, the data in register cell n remains Vlan tag data, so that the reading unit 42 may not determine whether the data in register cell n is Vlan tag data or not in the subsequent clock cycle, and may of course determine that the data in register cell n is Vlan tag data, but the determination result is Vlan tag data.
It should be understood that the specific length of the Vlan tag may be different according to different application scenarios and different protocol specifications, and the specific structure of the Vlan frame in this embodiment may also be flexibly set according to the specific application scenarios and different protocol specifications.
The storage size of the register unit 0, …, i, … in this embodiment is theoretically only required to be 1 byte or more, and in order to control the cost as much as possible, the storage size of the register unit n of each of the register units 1, …, i, … may be set to 1 byte.
Generally, the length of the Vlan tag data in the Vlan frame and its numerical content may be substantially predetermined, for example, the length of the Vlan tag data may be 4 bytes, for example, 0x 810 x 000 x0a 0xbc in one example.
In an example of the present embodiment, the determining in S303 whether the data in the register unit n is Vlan tag data includes:
comparing the data in the register unit n with the nth byte data in the Vlan tag, and determining that the data in the register unit n is Vlan tag data when the data in the register unit n is consistent with the nth byte data in the Vlan tag;
or comparing the data in the register unit n with the byte data in the Vlan tag, and determining that the data in the register unit n is Vlan tag data when the data in the register unit n is judged to be consistent with the byte data in the Vlan tag.
In this embodiment, after the data obtained by analyzing the Vlan frame is completely written, the reading unit 42 further performs zero clearing processing on the data in the register units 1 and …, i and … to prepare for processing the next Vlan frame; of course, the zero clearing process may be performed on the register unit 0.
The Vlan-frame processing apparatus provided in this embodiment can be applied to a server, and as a part for receiving and processing a Vlan frame by the server, it can effectively strip Vlan tag data having a byte length of n in the Vlan frame by using n +1 register units, and does not need to use FIFO logic resources, and the read-write control is relatively simpler, and hardware and control maintenance costs can be reduced.
Example three:
to facilitate understanding of the present invention, the present embodiment is exemplified by the Vlan tag data included in the Vlan frame being 4 bytes in length, and the specific data being 0x 810 x 000 x0a 0 xbc. The structure of the Vlan frame is shown in fig. 5, where the Vlan Tag 802.1Q Vlan Tag in the Vlan frame takes 4 bytes. Assuming that all data analyzed and output by the Vlan frame are input data: 0x 010 x 020 x 030 x 040 x 050 x 810 x 000 x0a 0xbc 0x 060 x07
The inserted Vlan tag data is: 0x 810 x 000 x0a 0xbc,
the processed output data is: 0x 010 x 020 x 030 x 040 x 050 x 060 x 07;
setting 5 registers, which are numbered as 0, 1, 2, 3 and 4 in sequence, wherein the registers 1, 2, 3 and 4 are respectively written with four bytes of a Vlan tag, fig. 6 shows control of each register in FPGA logic, an arrow in fig. 7 shows a data transmission direction, the registers 0, 1, 2, 3 and 4 perform pipelining operation, that is, input data is always written to the register 0, data of the register 0 is always written to the register 1, and so on. The data in register 4 is output until the Vlan tag data appears in register 4. After the Vlan tag appears in register 4, the data of register 0 is switched to be output. Thus, the processing result that the Vlan tag in the output data is stripped is realized.
The method for stripping the Vlan tag from the Vlan frame in the FPGA shown in fig. 6 includes the following steps:
s601: the ethernet data parsed from the Vlan frame is continuously written directly to register 0.
S602: the data in register 0 is written directly to register 1.
S603: the data in register 1 is written directly to register 2.
S604: the data in register 2 is written directly to register 3.
S605: the data in register 3 is written directly to register 4.
S606: in the output control logic, continuously judging the data in the register 4, and judging whether the data in the register 4 is Vlan tag data, if so, going to S607; otherwise, go to S608.
S607: the contents of register 4 are output directly until the Vlan tag is present.
S608: and the output is directly output by switching to the register 0, so that a Vlan tag does not appear in the output data, the function of peeling the Vlan tags in the registers 1 to 4 is realized, and the continuity of the output data is ensured.
As shown in fig. 7, the specific data flow is that the input packet data is 0x01, 0x02, 0x03, 0x04, 0x05, 0x81, 0x00, 0x0a, 0xbc, 0x06, and 0x07 … …, and the packet data sequentially passes through the register 0, the register 1, the register 2, the register 3, and the register 4 in a pipeline manner from the beginning and is output, but when Vlan tag data (0x81, 0x00, 0x0a, and 0xbc) appears in the register 4, the register 3, the register 2, and the register 1, the output control is switched from the register 4 to the register 0, and the Vlan tag data of the registers 4 to 1 is no longer output. Thus, the function of peeling off the Vlan tag is realized through a simple output switch, so that the FIFO and the complex read-write control logic in the conventional scheme are not needed. By adopting the scheme, the method can be realized only by a plurality of registers, so that the use of logic resources is reduced, a better time sequence is obtained after compiling, the complexity of logic is reduced, and debugging and maintenance are facilitated.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling an application device (such as a mobile phone, a computer, a server, an air conditioner, or a network application device) to execute the method according to the embodiments of the present invention.
The foregoing is a more detailed description of embodiments of the present invention, and the present invention is not to be considered limited to such descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A Vlan frame processing method, comprising:
acquiring a Vlan frame containing a Vlan tag, wherein the length of the Vlan tag is n bytes;
analyzing the Vlan frame, sequentially writing the analyzed data into a register unit 0 by taking 1 byte as a step length and 1 clock as a writing period, wherein the register unit 0 is sequentially connected with the register units 1 and … and register units i and …, and in the writing process, the method further comprises the step of writing the data in the previous register unit into the next register unit in each clock period;
when data is written into the register unit n, judging whether the data in the register unit n is Vlan tag data or not in each clock cycle, if not, reading the data from the register unit n, and continuously writing the data in the previous register unit into the next register unit in each clock cycle; otherwise, reading data from the register unit 0 in each subsequent clock cycle, and stopping writing the data in the previous register unit into the next register unit.
2. The Vlan frame processing method according to claim 1, wherein determining whether data in said register unit n is Vlan tag data comprises:
and comparing the data in the register unit n with the nth byte data in the Vlan tag, and determining that the data in the register unit n is Vlan tag data when the data in the register unit n is consistent with the nth byte data in the Vlan tag.
3. A Vlan frame processing method according to claim 1 or 2, wherein said method further comprises:
and after the data obtained by analyzing the Vlan frame is written, clearing the data in the register units 1 and …, i and n, ….
4. A Vlan frame processing method according to claim 1 or 2, wherein said n is equal to 4.
5. A Vlan frame processing method according to claim 1 or 2, wherein a storage size of said register unit 0, …, register unit i, … register unit n is 1 byte.
6. A Vlan frame processing device is characterized by comprising an analysis unit, a reading unit, a register unit 0, a register unit 1, a register unit …, a register unit i and a register unit … n which are connected in sequence;
the analysis unit is used for analyzing the Vlan frame containing the Vlan tag, sequentially writing the analyzed data into the register unit 0 by taking 1 byte as a step length and 1 clock as a writing period, and writing the data in the previous register unit into the next register unit in each clock period;
the reading unit is used for judging whether the data in the register unit n is Vlan tag data or not in each clock cycle when the data is written in the register unit n, if not, reading the data from the register unit n, and continuously informing the analysis unit to write the data in the previous register unit into the next register unit in each clock cycle; otherwise, reading data from the register unit 0 in each subsequent clock cycle, and informing the parsing unit to stop writing the data in the previous register unit into the next register unit in each subsequent clock cycle.
7. The Vlan frame processing apparatus according to claim 6, wherein said reading unit is configured to compare data in said register unit n with data of an nth byte in said Vlan tag, and determine that the data in said register unit n is Vlan tag data when the data in said register unit n and the data of an nth byte in said Vlan tag are identical.
8. The Vlan frame processing apparatus according to claim 6 or 7, further comprising a clearing unit configured to clear data in the register unit 1, …, register unit i, or register unit n … after the data obtained by the analysis of the Vlan frame by the analyzing unit is written.
9. A Vlan frame processing apparatus as claimed in claim 6 or 7, wherein said register unit 0, …, register unit i, … register unit n has a storage size of 1 byte.
10. A server, characterized by comprising a Vlan frame processing apparatus according to any one of claims 6-9.
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| CN103475559A (en) * | 2013-09-18 | 2013-12-25 | 北京锐安科技有限公司 | Method and system for processing and transmitting message according to contents of message |
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| CN108933722A (en) | 2018-12-04 |
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