CN108924074B - Equalizer and channel estimation method - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2689—Link with other circuits, i.e. special connections between synchronisation arrangements and other circuits for achieving synchronisation
- H04L27/2695—Link with other circuits, i.e. special connections between synchronisation arrangements and other circuits for achieving synchronisation with channel estimation, e.g. determination of delay spread, derivative or peak tracking
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/067—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing soft decisions, i.e. decisions together with an estimate of reliability
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2689—Link with other circuits, i.e. special connections between synchronisation arrangements and other circuits for achieving synchronisation
- H04L27/2692—Link with other circuits, i.e. special connections between synchronisation arrangements and other circuits for achieving synchronisation with preamble design, i.e. with negotiation of the synchronisation sequence with transmitter or sequence linked to the algorithm used at the receiver
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/38—Demodulator circuits; Receiver circuits
- H04L27/3845—Demodulator circuits; Receiver circuits using non - coherent demodulation, i.e. not using a phase synchronous carrier
- H04L27/3854—Demodulator circuits; Receiver circuits using non - coherent demodulation, i.e. not using a phase synchronous carrier using a non - coherent carrier, including systems with baseband correction for phase or frequency offset
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0024—Carrier regulation at the receiver end
- H04L2027/0026—Correction of carrier offset
- H04L2027/0038—Correction of carrier offset using an equaliser
- H04L2027/0042—Correction of carrier offset using an equaliser the equaliser providing the offset correction per se
Abstract
Disclosed herein are an equalizer and a channel estimation method, including: an equalizer, comprising: the system comprises a first signal processing module, a second signal processing module, an FEC encoding module, a first FEC decoding module, a second FEC decoding module, an additional pilot frequency module, a data mapping module, a data synthesizing module and a symbol mapping module; a channel estimation method is also disclosed. The invention carries out secondary signal processing on the soft judgment result and the hard judgment result, thereby solving the problems that the training sequence can not carry out difference operation or the measurement result is not accurately influenced by noise and the result obtained by only utilizing the channel estimation information at the training sequence is not ideal under the condition of a short burst structure or a channel with larger noise in a communication system.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to channel estimation and equalizer design for a communication system.
Background
Modern communication systems, such as optical communication systems, terrestrial mobile communication systems, satellite communication systems, etc., transmit signals that are transmitted through space or other media and received by communication terminals. The amplitude and phase of the signal are affected by multiplicative interference during spatial transmission, and in order to be able to correctly recover the bit data sent by the originating receiver, the receiver must estimate and compensate for the effect of the channel.
The channel estimation comprises methods such as non-blind estimation, blind estimation and semi-blind estimation. In general, in a communication system, training symbols (or referred to as pilots) are inserted at appropriate positions of a signal transmitted from a transmitting end, and channel information is estimated at a receiving end using the training symbols for phase compensation, signal equalization, and the like. Although the above method is effective for long bursts, the equalization effect is not ideal for short bursts, few training symbols and low signal-to-noise ratio, and a new equalization structure is needed. Therefore, a novel equalizer structure based on the Turbo idea is produced. According to the invention, the soft judgment result and the hard judgment result are subjected to secondary signal processing, and the soft judgment information is subjected to FEC cyclic decoding according to the soft judgment result, so that the confidence coefficient is higher, the information is more reliable, and the information is closer to the true value of the originating terminal, therefore, the data and the hard judgment data are called to carry out secondary signal processing, and according to experimental data, the requirement of 1dB @1e-4 BER can be improved by using the mode.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide an equalizer and a channel estimation method, which can solve the problems that in a communication system, under the condition of a short burst structure or a channel with larger noise, a training sequence is only one section and is short, difference operation cannot be carried out, or a measurement result is influenced by the noise and is inaccurate, and the result obtained by only utilizing channel estimation information at the training sequence is not ideal. .
The purpose of the invention is realized by the following technical scheme:
an equalizer, comprising: the system comprises a first signal processing module, a second signal processing module, an FEC encoding module, a first FEC decoding module, a second FEC decoding module, an additional pilot frequency module, a data mapping module, a data synthesizing module and a symbol mapping module;
the first signal processing module is used for carrying out signal processing on input data and outputting the input data to the first FEC decoding module for FEC decoding;
the hard judgment information output by the first FEC decoding module is output to the FEC encoding module for FEC encoding;
the coded data output by the FEC coding module is output to the pilot adding module and inserted into a pilot sequence;
the pilot frequency increasing module outputs a sequence containing pilot frequency to the symbol mapping module and carries out modulation mapping;
the data mapping module performs data mapping on the soft judgment information output by the first FEC decoding module, and the mapping mode is set according to the code pattern transmitted in the channel;
the output data of the data mapping module is output to the data synthesis module, and the output data and the pilot frequency data output by the first signal processing module are synthesized;
the output data of the data synthesis module is output to the second signal processing module, the data output by the data synthesis module is used as data to be processed, the data output by the symbol mapping module is used as target data, and the data to be processed is subjected to signal processing according to the target data;
and the output data of the second signal processing module is output to the second FEC decoding module, and the output data is FEC decoded.
Further, the ways of outputting the sequence containing the pilot frequency to the symbol mapping module and performing modulation mapping by the pilot frequency adding module include ASK, mPSK, mQAM, FSK;
the data mapping module maps the soft decision information output by the first FEC decoding module in a data mapping mode including ASK, mPSK, mQAM, and FSK.
Further, the output data of the second signal processing module is output to the second FEC decoding module, and performing FEC decoding on the output data further includes: the decoding method comprises Turbo decoding, Viterbi decoding and LDPC decoding.
Further, the first signal processing module is configured to perform signal processing on the input data and output the processed input data to the first FEC decoding module for FEC decoding, and the FEC decoding module further includes: the signal processing comprises filtering, clock synchronization, data synchronization, polarization correction, frequency offset estimation, phase offset estimation and equalization processing.
The invention also discloses a channel estimation method, which comprises the following steps:
s1, performing signal processing on input data and performing FEC decoding;
s2, performing FEC encoding on the hard judgment information output by the FEC decoding;
s3, inserting the FEC coding data into a pilot frequency sequence;
s4, modulating and mapping the FEC coding data inserted into the pilot frequency sequence;
s5, performing data mapping on the soft judgment information output in the step S1, wherein the mapping mode is set according to the code pattern transmitted in the channel;
s6, synthesizing the output data of the step S5 and the pilot frequency data output after the signal processing in the step S1;
s7, taking the synthesized data as data to be processed, taking the data output in the step S4 as target data, and performing signal processing on the data to be processed according to the target data;
and S8, performing FEC decoding on the output data of the step S7.
Further, the modulation mapping manner in step S4 includes ASK, mPSK, mQAM, FSK;
the data mapping manner in step S5 includes ASK, mPSK, mQAM, and FSK.
Further, the FEC decoding includes Turbo decoding, viterbi decoding, and LDPC decoding.
Further, the signal processing includes filtering, clock synchronization, data synchronization, polarization correction, frequency offset estimation, phase offset estimation, and equalization processing.
The invention has the beneficial effects that: in the field of communication systems, aiming at the situation of a short burst structure or a channel with large noise, because a training sequence has only one section, and the difference operation cannot be carried out in a short period, or the difference result is not accurate, and the result obtained by only utilizing the channel estimation information at the training sequence is not ideal, the invention carries out inverse mapping on the channel estimation soft judgment result by carrying out inverse coding on the initial channel estimation hard judgment result, which is equivalent to increasing the number of effective training symbols participating in channel estimation, and utilizes the soft judgment information to improve the reliability of data, thereby greatly improving the performance under a Gaussian channel.
Drawings
FIG. 1 is a block diagram of system modules according to one embodiment.
Detailed Description
In order to more clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will now be described with reference to the accompanying drawings.
The first signal processing module 101 receives data from a receiver and processes the received data, and the current general process is as follows: filtering, clock synchronization, data synchronization, polarization correction, frequency offset estimation, phase offset estimation and equalization processing, and partial damage in the data transmission process can be compensated after the processes.
The first FEC decoding module 201 performs FEC decoding on the compensated data, including CRC and decoding processes, where the selection of the decoding mode may include all types currently covered, such as Turbo decoding, viterbi decoding, LDPC decoding, and the like, according to different scene requirements.
The FEC encoding module 301 encodes the decoded data output by the first FEC decoding module 201, including CRC and decoding processes, where the selection of the decoding mode corresponds to the decoding mode of the first FEC decoding module 201, including but not limited to all types currently covered, such as Turbo encoding, viterbi encoding, and LDPC encoding.
The pilot adding module 401 synthesizes data of the FEC encoding module 301 and pilot data, if the system has no pilot, the module can ignore the data, and if the system has pilot, the module adds pilot information to the data according to the requirement of the system.
The symbol mapping module 402 modulates and maps the data output by the pilot frequency increasing module 401, and maps the data into various modes such as QPSK, mQAM, mPSK, ASK, FSK and the like according to the system requirements.
Meanwhile, when decoding the data output by the first signal processing module 101, the first FEC decoding module 201 outputs soft decision information for each data besides outputting hard decision information to the FEC encoding module 301, where the soft decision information represents a confidence of each data, the soft decision information is input to the data mapping module 202, and the data mapping module 202 maps the soft decision data, where the mapping may be set to an mQAM modulation format according to a system modulation format.
The data output by the data mapping module 202 enters the data synthesis module 203 and is merged with the pilot data output from the first signal processing module 101, because the pilot data does not participate in FEC decoding, the first signal processing module 101 separates the pilot from the data after signal processing, the data information enters FEC, the pilot enters the data synthesis module 203 and is merged with the data output by the data mapping module 202, if the system has no pilot, the module is not needed, if the system has a pilot, the pilot is inserted into the data according to the system requirement, and a required frame format is formed.
The data output by the data synthesis module 203 and the data output by the symbol mapping module 402 enter the second signal processing module 302 at the same time, the data synthesis module 203 corresponds to the symbol mapping module 402 one by one, the data synthesis module 203 can be used as the target data of the symbol mapping module 402 to process the data output by the symbol mapping module 402, the processing mode can include steps of polarization correction, frequency offset estimation, phase offset estimation, equalization processing and the like, and the data synthesis module 203 can be used as the target information of the data of the symbol mapping module 402, so the signal processing can be performed with full pilot processing. Different from the previous processing mode of the first signal processing module 101, due to the limitation of the number of the pilot frequencies, the number of the pilot frequencies is the same as the number of the inserted pilot frequencies, and the first signal processing module 101 can only perform blind estimation, semi-blind estimation or pilot frequency estimation, so the estimation accuracy is not high, but if the output of the data synthesis module 203 is taken as target information, each data has a corresponding pilot frequency value, and full pilot frequency estimation is performed, so the estimation value is more accurate, and the performance is further improved.
The data output by the second signal processing module 302 enters the second FEC decoding module 403 for decoding, the decoding mode is the same as that of the first FEC decoding module 201, and the result can be output after decoding.
If the output result does not meet the requirement, multiple iterations can be performed. .
It should be noted that, as those skilled in the art should appreciate, the embodiments described in the specification are preferred embodiments, and the actions and elements referred to are not necessarily required for the present application.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a ROM, a RAM, etc.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention, and it is therefore to be understood that the invention is not limited by the scope of the appended claims.
Claims (8)
1. An equalizer, comprising: the system comprises a first signal processing module, a second signal processing module, an FEC encoding module, a first FEC decoding module, a second FEC decoding module, an additional pilot frequency module, a data mapping module, a data synthesizing module and a symbol mapping module;
the first signal processing module is used for carrying out signal processing on input data and outputting the input data to the first FEC decoding module for FEC decoding, and the decoding mode comprises Turbo decoding, Viterbi decoding and LDPC decoding;
outputting the hard judgment information output by the first FEC decoding module to the FEC encoding module for FEC encoding, wherein the selection of the encoding mode corresponds to the decoding mode of the first FEC decoding module, and the encoding mode comprises Turbo encoding, Viterbi encoding and LDPC encoding;
the coded data output by the FEC coding module is output to the pilot adding module and inserted into a pilot sequence;
the pilot frequency increasing module outputs a sequence containing pilot frequency to the symbol mapping module and carries out modulation mapping;
the data mapping module performs data mapping on the soft judgment information output by the first FEC decoding module, the mapping mode is set according to the code pattern transmitted in the channel, and the mapping can be set into an mQAM (quadrature amplitude modulation) modulation format according to a system modulation format;
the output data of the data mapping module is output to the data synthesis module, and the output data and the pilot frequency data output by the first signal processing module are synthesized;
the output data of the data synthesis module is output to the second signal processing module, the data output by the data synthesis module is used as data to be processed, the data output by the symbol mapping module is used as target data, and the data to be processed is subjected to signal processing according to the target data;
and the output data of the second signal processing module is output to the second FEC decoding module, and the output data is FEC decoded, wherein the decoding mode of the second FEC decoding module is the same as that of the first FEC decoding module.
2. The equalizer of claim 1, wherein the manner of outputting the sequence containing the pilot frequency to the symbol mapping module and performing modulation mapping by the pilot frequency adding module comprises ASK, mPSK, mQAM, FSK;
the data mapping module maps the soft decision information output by the first FEC decoding module in a data mapping mode including ASK, mPSK, mQAM and FSK, and the mapping may be set to an mQAM modulation format according to a system modulation format.
3. The equalizer of claim 1, wherein the output data of the second signal processing module is output to the second FEC decoding module, and FEC decoding the output data further comprises: the decoding method comprises Turbo decoding, Viterbi decoding and LDPC decoding.
4. The equalizer of claim 1, wherein the first signal processing module for signal processing the input data and outputting to the first FEC decoding module for FEC decoding further comprises: the signal processing comprises filtering, clock synchronization, data synchronization, polarization correction, frequency offset estimation, phase offset estimation and equalization processing.
5. A method of channel estimation, comprising:
s1, performing signal processing on input data and performing FEC decoding, wherein the decoding mode comprises Turbo decoding, Viterbi decoding and LDPC decoding;
s2, performing FEC encoding on the hard judgment information output by the FEC decoding, wherein the encoding mode corresponds to the decoding mode and comprises Turbo encoding, Viterbi encoding and LDPC encoding;
s3, inserting the FEC coding data into a pilot frequency sequence;
s4, modulating and mapping the FEC coding data inserted into the pilot frequency sequence;
s5, data mapping is carried out on the soft judgment information output in the step S1, the mapping mode is set according to the code pattern transmitted in the channel, and the mapping can be set into an mQAM (quadrature amplitude modulation) modulation format according to the system modulation format;
s6, synthesizing the output data of the step S5 and the pilot frequency data output after the signal processing in the step S1;
s7, taking the synthesized data as data to be processed, taking the data output in the step S4 as target data, and performing signal processing on the data to be processed according to the target data, further, enabling the data S7 to correspond to the data S5 one by one, enabling the data S7 to serve as the target data of S5, and processing the data output in the step S5;
and S8, performing FEC decoding on the output data of the step S7, wherein the decoding mode is the same as the decoding mode in the step S1.
6. The channel estimation method according to claim 5, wherein the modulation mapping manner in step S4 includes ASK, mPSK, mQAM, FSK;
the data mapping manner in step S5 includes ASK, mPSK, mQAM, FSK, and the mapping may be set to an mQAM modulation format according to a system modulation format.
7. The channel estimation method according to claim 5, wherein the FEC decoding includes Turbo decoding, Viterbi decoding, LDPC decoding.
8. The channel estimation method according to claim 5, wherein the signal processing includes filtering, clock synchronization, data synchronization, polarization correction, frequency offset estimation, phase offset estimation, equalization processing.
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